Low power resistive random access memory using interface-engineered dielectric stack of SiOx/a-Si/TiOy with 1D1R-like structure

Low power resistive random access memory using

interface-engineered dielectric stack of SiO

_x

/a-Si/TiO

_y

with 1D1R-like structure

Chun-Hu Cheng

_{, K.I. Chou}

_{, Zhi-Wei Zheng}

_{, Hsiao-Hsuan Hsu}

a_{Department of Mechatronic Technology, National Taiwan Normal University, Taipei 106, Taiwan, ROC} b_{Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, ROC} c_{Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China}

a r t i c l e i n f o

Received 2 September 2013 Received in revised form 17 October 2013 Accepted 23 October 2013 Available online 31 October 2013

Keywords:

Resistive random access memory (RRAM) SiO2

TiO2

Current distribution

a b s t r a c t

In this study, we report a resistive random access memory (RRAM) using trilayer SiOx/a-Si/TiOyfilm structure. The low switching energy of<10 pJ, highly uniform current distribution (<13% variation), fast 50-ns speed and stable cycling endurance for 106_{cycles are simultaneously achieved in this RRAM} de-vice. Such good performance can be ascribed to the use of interface-engineered dielectric stack with 1D1R-like structure. The SiOxtunnel barrier in contact with top Ni electrode to form diode-like rectifying element not only lowers self-compliance switching currents, but also improves cycling endurance, which is favorable for the application of high-density 3D memory.

Ó 2013 Elsevier B.V. All rights reserved.

1. Introduction

With continued scaling down into sub-20 nm of non volatile

memory (NVM), theflash NVM faces a physical limitation on charge

storage in the scaled cell size[1,2]. Recently, resistive random

ac-cess memories (RRAMs) [3e14] with simple metaleinsulatore

metal (MIM) structure and embedded function are the promising candidates for next-generation NVM. However, the large switching power and poor switching distributions are the major challenges for production. To address these issues, we have proposed low

power RRAMs[11e14]based on hopping conduction mechanism

[15]. Unfortunately, the current distribution related to carrier

transport at the electrode/dielectric interface still cannot be

well-controlled. To further improve the uniformity, 1D1R (one-diodee

one-resistor)[16,17]structure is an alternative approach due to the

crosstalk suppression, especially for the crossbar arrays. In this work, we adopt a novel 1D1R-like RRAM structure with good rectifying behavior to improve the switching characteristics. This

RRAM device using trilayer SiOx/a-Si/TiOyfilms can achieve a low

switching power of 85

m

cycling, tight current distribution (coefficient of variation <13%)

and robust pulse cycling endurance (106 cycles at 50 ns). The

excellent switching characteristics are ascribed to the use of bilayer SiOx/a-Si capping layer that forms a diode-like rectifying behavior

(Ni/SiOx/a-Si) to modify resistive switching characteristics of TiOy

resistor. Compared to the previous RRAM device [18] using

covalent-bond oxide for uniformity improvement, the proposed low-power RRAM with 1D1R structure achieves good rectifying property to suppress the sneak current for crossbar array applica-tion. The present results show that such low-power RRAM with 1D1R-like structure design has the potential for the application of next-generation memory device.

2. Experimental procedure

First, a 200-nm-thick SiO2was formed on the Si substrate as a

buffer layer. Then, a 100-nm-thick TaN was deposited by dc sput-tering as the bottom electrodes. Next, the stacked layers of 2-nm-thick SiOx, 6-nm-2-nm-thick amorphous Si (a-Si) and 15-nm-2-nm-thick TiOy

(SiOx/a-Si/TiOy ¼ 2/6/15) were deposited as resistive switching

layers. To investigate the switching function of each layer, we also

deposit different thickness ratios of SiOx/a-Si/TiOy(3/6/15, 2/8/15

and 2/6/18) on bottom TaN for performance comparison. Because

the thickness increase on SiOx and a-Si layers would generate

strong serial resistance effect and apparently affect the resistive switching (fast resistance window shrinking), we only select opti-mized thickness ratios for a fair comparison to investigate the switching mechanism and current distribution characteristics here.

* Corresponding author. Tel.: þ886 2 7734 3514; fax: þ886 2 2358 3074. E-mail address:[email protected](C.-H. Cheng).

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1567-1739/$e see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.cap.2013.10.019

Finally, a 50-nm-thick Ni was deposited and patterned to form the top electrode by a metal mask. The schematics of fabrication

pro-cess are shown inFig. 1. All electrical characteristics of the

fabri-cated devices were measured by an Agilent 4156 semiconductor parameter analyzer.

3. Results and discussion

For typical RRAM devices, the resistance changes from high-resistance state (HRS) to low-high-resistance state (LRS) during set process and returns to HRS during reset process. To study the

switching characteristics of the Ni/TiOy/TaN RRAM device,Fig. 2(a)

shows the currentevoltage (IeV) curve. The forming-free and

self-compliance characteristics for set and reset processes are

measured. The asymmetric I_{eV curves is originated from the}

different work functions of the bottom TaN (4.6 eV) and top Ni

(5.1 eV) electrodes. The TiOyRRAM device is biased at 2.5 V for set

with a LRS current of 0.9 mA. For the reset process, the LRS is

recovered to HRS using a bias of2 V (36

m

of 0.9 mA induces high power consumption and also leads to an unstable resistance switching during cycling, which is unsuitable

for the requirement of low power operation.Fig. 2(b) shows the

repeated cycling result after 50 cycles. During set process, the

defective TiOywith narrow bandgap generates a low barrier

po-tential at the TiOy/TaN interface, which induces easy formation of

leakage paths and thus increases HRS current. The fast degradation of HRS current under stress leads to poor endurance. The increased HRS current with pulse cycles would result in a fast window shrinking that is not permitted for RRAM device.

To improve the performances of TiOyRRAM, we adopted afilm

stack of SiOx/a-Si on TiOyto form a 1D1R-like memory structure.

The Ni/SiOx/a-Si acts as a doide-like rectifying element where the

ultra-thin SiOx layer is used as tunneling barrier. As shown in

Fig. 3(a), the Ni/SiOx/a-Si/TiOy/TaN RRAM can be set and reset by different bias conditions. Although the HRS/LRS ratio read

at0.5 V becomes larger with increasing set and reset voltages

from 2 V to 3 V, the tradeoff between HRS/LRS ratio and switching power needs to be considered for practical application. Moreover,

the rectification behavior is clearly observed in LRS. Compared to

single TiOyRRAM, this RRAM using SiOx/a-Sifilm stack with

diode-like function largely lower set power from 2.3 mW to 84

m

reset power from 72

m

m

power is due to the rectifying effect of SiOxtunnel barrier. The

rectifying 1D1R-like structure is also favorable for the fabrication of high-density crossbar array. Fig. 3(b) shows the continued

cycling result after 100 cycles in Ni/SiOx/a-Si/TiOy/TaN RRAM. Apparently, the switching stability of HRS and LRS is much

improved through the incorporation of diode-like Ni/SiOx/a-Si

structure.

To further study the conduction mechanism, we plotted the

schematic band diagrams under set and reset conditions inFig. 4.

During the set process with a positive voltage, the charged oxygen vacancies are formed via injected electrons from the bottom TaN electrode. The bottom injection of electron carriers from TaN

electrode can pass through SiOxtunnel barrier to form a LRS

cur-rent. Here, the metal/tunnel barrier (Ni/SiOx) contact plays a key role to provide the self-compliance function for set process. Ac-cording to our previous research results, the low self-compliance LRS current not only lowers set power, but also improves the

switching uniformity[18]. Under a negative reset bias, the SiOx

tunnel barrier with high conduction band offset forms a large po-tential barrier (in contact with top Ni) to break conductive paths in LRS and fast recover to HRS at a low driving power of micro-Watt. Thus, the combined effect of electrode work function tuning and interface-engineered dielectric stacks is important to reduce switching power.

Deposit wet oxide isolation (200 nm) and sputtered TaN (100 nm) electrode on Si wafer

15~18-nm-thick TiOydeposition

by egun system

6~8-nm-thick a-Si deposition by egun system (with optimized )

2~3-nm-thick SiOxlayer

deposition by egun system

50-nm-thick Ni was pattern as top electrode and RRAM device finished TiOy a-Si/TiOy SiOx/a-Si/TiOy SiOx/a-Si/TiOy Ni TaN

Fig. 1. Schematics of fabrication process of Ni/SiOx/a-Si/TiOy/TaN RRAM.

10-11 10-9 10-7 10-5 10-3 10-1 4 3 1

Ni/TiO_y/TaN RRAM

Abs. (I) (A)

Voltage (V)

(a)

Abs.(I) (A)

Number of Switching (cycle)

HRS LRS

(b)

Fig. 2. (a) Swept IeV and (b) repeated cycling characteristics of Ni/TiOy/TaN RRAM devices.

To further study the switching function of each layer, the RRAM devices with different thickness (THK) for SiOx, a-Si and

TiOyare also fabricated. The thickness ratios of trilayer SiOx/a-Si/

TiOyare 3/6/15 (increment of SiOxTHK), 2/8/15 (increment of a-Si

THK) and 2/6/18 (increment of TiOyTHK), respectively.Fig. 5(a)

and (b) shows the swept IeV curves of RRAM devices with

different THK conditions. In comparison with original structure, the set current decreases with THK increment of each layer,

especially for large bandgap SiOx. This result proves that the SiOx

tunnel barrier dominates the self-compliance set current, even

only a slight THK increment (w1 nm). Correspondingly, the

lowest reset current of 100 nA is also measured for the case of

increased SiOxTHK in opposite bias direction, but accompanies

with severe interface trapping that is clearly observed near zero

bias. The interface trapping phenomena near SiOxtunnel barrier

may lead to a decreased LRS current due to electron pile-up

during cycling and finally shrink memory window. Fig. 5(c)

summarizes the forwardereverse ratios of different thickness

conditions. From the rectifying characteristics, the 404 of

increased TiOyTHK case is better than 368 of increased SiOxone,

indicating that the thickness tuning of TiOy with very high

dielectric constant (_>40)[19]to modify interface electric_{field is}

an appropriate approach to achieve both good rectifying property and low switching power.

The switching uniformity is important for RRAM to replace

commercialflash memory.Fig. 6(a) shows repeated cycling

char-acteristics (100 cycles) under different THK conditions. The case of

increased SiOxTHK exhibits poor endurance with a small memory

window of 5  after 100 cycles, which can be attributed to the

interface trapping effect as discussed above (Fig. 5(b)). In contrast,

the original structure maintains a consistent memory window of

27 after 100 repeated cycles. The cycle-to-cycle current

distri-butions are shown inFig. 6(b) and (c). The coefficient of variation

(CV) is defined as the ratio of standard deviation (

s

(

m

s

m

very uniform switching for LRS (12.7%) and HRS (11.7%) in original structure, but it cannot be reached in other control samples.

Moreover, it is worth to note that the case of increased TiOyTHK

with larger memory window of 33 presents the poor CV values for

both LRS (18.9%) and HRS (16.3%), suggesting that is related to the increase of oxygen vacancy and interstitial Ti atom in thicker TiOy

case, which induces randomly distributedfilaments and leads to

poor distributions. Therefore, it is clear that the current distribution of this trilayer RRAM is much better than those of our previously

reported 1R memories (GeOx/SrTiO [11] and GeOx/HfON [12]

RRAMs) with lower switching powers due to the use of rectifying

1D1R-like structure, as shown inFig. 7(a).

-3 -2 -1 0 1 2 3 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 Ni/TiO y/TaN (1R) Ni/SiO

x/a-Si/TiOy/TaN (1D1R-like) (swept from 2V to -2V)

Ni/SiO_x/a-Si/TiO_y/TaN (1D1R-like) (swept from 3V to -3V)

Abs.

(I

)

)(

(A)

Voltage (V)

(a)

Abs.(I) (A)

Number of Switching (cycle)

HRS LRS

27X

(b)

Fig. 3. (a) Swept IeV and (b) repeated cycling characteristics of Ni/SiOx/a-Si/TiOy/TaN RRAM devices.

SET

TaN

TiO

Ni SiO

a-Si

1D-like

(a)

Ni

RESET

TiO

SiO

a-Si

1D-like

TaN

(b)

Good endurance characteristics with uniform switching and fast

speed are necessary for RRAM. As shown in Fig. 7(b), a

>20  resistance window and a small LRS/HRS decay are measured

for 106cycles under 5 V set/5 V reset voltages with 50 ns pulse.

The fast switching speed is due to electron hopping conduction in

LRS that has been demonstrated in our previous works[11e14].

Thus, the good endurance performance can be ascribed to a self-compliance switching current, pronounced LRS rectifying effect

0.0 0.5 1.0 1.5 2.0 2.5 3.0 10n 100n 1 10 100 1m SET Original Structure Increase SiO_x THK Increase a-Si THK Increase TiO_y THK

Abs.

(I)

)(

(A)

)

Voltage (V)

(a)

Abs.(I)

)(

(A)

Voltage (V)

(b)

Forward-Re

verse

Ratio

(c)

Fig. 5. Swept IeV curves of Ni/SiOx/a-Si/TiOy/TaN RRAM with different THK conditions for (a) set and (b) reset processes. (c) Repeated cycling characteristics of Ni/SiOx/a-Si/ TiOy/TaN RRAM with different THK conditions.

1 10 100 10-10 10-9 10-8 10-7 5X 18X 27X Increase a-Si THK Increase SiO_x THK Original Structure Increase TiO_y THK

Abs.

(I) (A

)

Number of Switching (cycle)

(a)

1

10

100

Cumulative pr

obability (%)

Abs. I (A)

Low-Resistance State

(b)

Original Structure

(CV=11.7%)

Increase SiO

THK

(CV=2.5%)

Increase a-Si THK

(CV=11.2%)

Increase TiO

THK

(CV=16.3%)

Cumulative pr

obability

(%)

Abs. I (A)

High-Resistance State

(c)

Fig. 6. (a) 50-ns-pulse cycling characteristics, (b) LRS and (c) HRS current distributions (cycle-to-cycle) of Ni/SiOx/a-Si/TiOy/TaN RRAM with different THK conditions.

and very low switching energy of<10 pJ to stabilize electric filed stress across over dielectric stacks.

4. Conclusions

We reported a novel RRAM device using trilayer SiOx/a-Si/TiOy

film stack. This RRAM device exhibits low operating voltage of

2 V, highly uniform current distribution of<13% variation, fast

speed of 50-ns, low switching energy of <10 pJ, and good

endurance. The good performances can be attributed to the incorporation of Ni/SiOx/a-Si with diode-like function on TiOy resistor, which lowers switching current through the combined

effect of SiOx tunnel barrier and hopping conduction in LRS.

Moreover, the switching function of each layer was investigated.

The results show that the thickness tuning of SiOx to reduce

interface trapping and TiOyto modify interface electricfield is an

appropriate approach to achieve both good rectifying property and low switching power. Such low-power RRAM with interface-engineered dielectric stack and 1D1R-like structure design has the potential for a number of applications in the future, such as high-density 3D memory, programmable logic, and adaptive neuromorphic circuits.

Acknowledgment

This work was supported by the National Science Council (NSC) of Taiwan, Republic of China, under contract no. NSC 102-2221-E-003-019.

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GeO_x/HfON [12]

Cumulative probability (%)

Abs. (I) (A)

(a)

Abs.

(I

) (A)

Pulse cycles

(b)

Fig. 7. (a) Current distributions of Ni/SiOx/a-Si/TiOy/TaN RRAM and previous Ni/GeOx/ HfON/TaN RRAM devices and (b) endurance characteristic of Ni/SiOx/a-Si/TiOy/TaN RRAM device.