Influence of channel layer and passivation layer on the stability
of amorphous InGaZnO thin film transistors
Runze Zhan
a,⇑, Chengyuan Dong
a, Po-Tsun Liu
b, Han-Ping D. Shieh
a,b aNational Engineering Lab for TFT-LCD Materials and Technologies, Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
b
Department of Photonics & Display Institute, National Chiao Tung University, Hsinchu, Taiwan
a r t i c l e
i n f o
Article history:
Received 29 September 2012 Received in revised form 14 May 2013 Accepted 15 May 2013
Available online 10 June 2013
a b s t r a c t
The electrical stability of amorphous InGaZnO (a-IGZO) TFTs with three different channel layers was investigated. Compared with the single channel layer, the a-IGZO TFT with double stacked channel layer showed the lowest threshold voltage shift with slightly change in field effect mobility and sub-threshold swing under positive and negative gate bias stress tests. Moreover, sputtered SiNxthin film was served as
passivation layer where the Vthshift in bias stress effect evidently became less. It was found that the
pas-sivated a-IGZO TFT with double stacked channel layer still exhibited the best stability. The results prove that the stability of a-IGZO TFTs can be effectively improved by using double stacked channel layer and passivation layer.
Ó 2013 Elsevier Ltd. All rights reserved.
1. Introduction
Amorphous oxide semiconductors especially amorphous InG-aZnO (a-IGZO) are being used as channel materials in thin film transistors(TFTs) for the applications of next generation active ma-trix flat panel displays because of their advantages including high mobility, room temperature deposition, excellent uniformity, high flexibility, and good transparency to visible light, etc.[1]. Recently, several prototype displays, such as high definition liquid crystal displays (LCDs), active matrix (AM) flexible displays, and active matrix organic light emitting diode (AMOLED) displays, with a-IGZO TFTs used as driving circuits have been demonstrated[2,3]. Despite of the great progress in the device and process develop-ment, the instability of a-IGZO TFTs is still a concern for their prac-tical applications[3,4].
To produce good and stable TFTs, appropriate deposition condi-tions for channel layer should be considered. For the n-type oxide semiconductor, it is well known that oxygen plays an important role in the properties of thin films and TFT devices[5–7]. For in-stance, the electrical stability of a-IGZO TFTs with excess oxygen in their active layers degrades due to the defects in the channel layer/gate insulator layer interface and/or acceptor-like defects in the bulk of channel layer[8,9]. Moreover, because of the instability induced by ambient effect for the TFTs with exposed back channel, passivation layer is usually used to improve the stability of oxide semiconductor TFTs[10–12]. However, the effect of the passivation process on the performance of channel layer from plasma damage should be considered in depth.
In this work, the electrical stability of a-IGZO TFTs with three types of channel layers was investigated. More specifically, we fab-ricated a double stacked channel layer with different deposition conditions and studied their influence on the performance of TFTs. The bias stress effect for the TFTs was studied. Furthermore, TFTs with a sputtered SiNxpassivation layer was studied, and the corre-sponding passivation effect was discussed.
2. Experimental
The TFTs with bottom gate staggered structure, as shown in Fig. 1, were fabricated on the substrates of n-type silicon (Si) wa-fers, which were also used as common gate. A 100-nm-thick SiO2 layer was grown by thermal oxidation of Si wafer. The channel layer and source/drain electrodes were patterned using shadow masks. The fabricated TFTs had a channel length (L) of 200
l
m and width (W) of 1000l
m. As a channel layer, a-IGZO film was deposited by RF magnetron sputtering using a target of polycrys-talline In2Ga2ZnO7(In2O3:Ga2O3:ZnO = 1:1:1, mol%) at room tem-perature. A flow rate of 10 sccm for argon and different oxygen flow rates were used to study the impact of channel layer on the device performance. Three types of channel layers were studied: for sample I, a-IGZO (Ar) thin film as channel layer was deposited without oxygen, called as oxygen-poor IGZO film; for sample II, a-IGZO(Ar + O2) thin film was deposited with an oxygen flow rate of 2.0 sccm, called as oxygen-rich IGZO film; specially, for sample III with a double stacked channel layer, 20-nm-thick oxygen-poor a-IGZO(Ar) and 10-nm-thick oxygen-rich a-IGZO(Ar + O2) thin films were served as the front and back channel layers, respectively. The entire channel thickness for three types of TFTs was 30 nm. In deposition the total pressure was fixed at 3 m Torr and the RF0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.microrel.2013.05.007
⇑ Corresponding author. Tel.: +86 21 34204371.
E-mail addresses:[email protected],[email protected](R. Zhan).
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Microelectronics Reliability
power density was 1.76 W/cm2. Before the deposition of source/drain electrodes, channel layers were annealed to improve the film quality. Annealing process was performed in nitrogen atmosphere with a thermal furnace at 350 °C for 1 h. Then, a 40-nm-thick ITO thin film was deposited by RF magnetron sputter-ing to serve as the source/drain electrodes. For the passivated TFTs, 30-nm-thick SiNxthin films were deposited by RF sputtering using a target of Si3N4(99.99%) at room temperature following the depo-sition of ITO electrodes. Appropriate conditions including an argon flow rate of 10 sccm, a chamber pressure of 3 m Torr and a RF power density of 1.32 W/cm2were selected to reduce the negative effect of passivation process on the TFT performances. Finally, the TFTs were annealed in nitrogen atmosphere at 350 °C for 1 h to improve their electrical properties.
The thickness of channel layer was measured by atomic force microscopy (AFM, Vecco Nanoscope IIIA). X-ray photoemission spectroscopy (XPS, Thermal-fisher ESCLAB 250) was used to ana-lyze the oxygen contents in a-IGZO thin films deposited without and with oxygen incorporation. The electrical performance and stability of a-IGZO TFTs were characterized at room temperature in the ambient atmosphere using Keithley 4200 semiconductor parameter analyzer.
3. Results and discussion 3.1. Thin films’ characteristics
To examine the oxygen contents of a-IGZO thin films deposited without and with oxygen incorporation, we performed XPS
mea-surement. The XPS spectra of O 1 s signals in a-IGZO films depos-ited with and without oxygen are shown inFig. 2. The O 1 s peak can be fitted by three nearly Gaussian distributions, approximately centered at 530.5, 531.6, and 532.4 eV[13,14]. The low binding en-ergy peak (OL) at 530.5 eV was related to the O2ions combined with the Zn, Ga and In atoms in the IGZO compound system. The high binding energy peak (OH) at 532.4 eV was associated with the loosely bonded oxygen on the surface of IGZO film termed the specific chemisorbed oxygen, such as CO3, absorbed H2O or absorbed O2. The binding energy component (OM) at 531.6 eV was attributed to O2ions that were in oxygen deficient region in the IGZO matrix. Compared with the oxygen-poor film, the de-crease in the OMpeak for the oxygen-rich film was attributed to the reduction in oxygen vacancies, where the film was compen-sated with O atoms. The result implies that a-IGZO thin films deposited without oxygen possess more oxygen vacancies than those deposited with oxygen.
3.2. Device characterization
Electrical characteristics of the three types of a-IGZO TFTs (sam-ples I, II, and III) are depicted inFig. 3, including the transfer char-acteristics [drain-source current (Ids) versus gate-source voltage (Vgs)] at Vds= 0.1 V (linear region) and Vds= 10 V (saturation re-gion). All devices were n-type enhancement mode TFTs. Threshold voltage was estimated from the intercept of Ids1/2–Vgscurve using the standard saturation current equation in the saturation region [15]. Sub-threshold swing (S) and field effect mobility (
l
FE) were extracted from the Ids–Vgscurve in the linear regime[15]. S is de-fined as the change in Vgs required to change the subthreshold drain current by one decade, given by S = dVgs/d(logIds) (V/dec).Fig. 1. Schematic diagrams of bottom gate structures for three types of a-IGZO TFTs: (a) samples I and II, and (b) III.
Fig. 2. XPS spectra of the O 1 s region in the a-IGZO films.
Fig. 3. Transfer curves for a-IGZO TFTs: samples I, II and III, at (a) Vds= 0.1 V (linear
Here, the S was extracted from one half of the Vgsrequired to in-crease the threshold current by two orders of magnitude (from 1010to 108A).
l
FEwas calculated using the following relation:
l
FE=[gmL/(WVdsCi)], where gmis the maximum channel transcon-ductance, and Ciis gate insulator capacitance per unit area. Ron/off was defined as the ratio of the maximum to the minimum Idswhen Vdswas applied at 10 V. The minimum Idswas given by the maxi-mum leakage current, while the maximaxi-mum Idswas obtained from the highest drain-source current based on the experimental Ids– Vgscurves. Besides, the equivalent maximum interface-state trap density Nssat the channel layer-gate insulator interface can be cal-culated by Nss¼ SigðeÞj
T=q 1 C i q ð1Þwhere q is electron charge,
j
is Boltzmann constant, T is tempera-ture, and Ciis gate insulator capacitance per unit area[16].The electrical parameters of three types of a-IGZO TFTs are sum-marized inTable 1.
l
FEof sample I was 4.00 cm2/Vs, the highest among the three types of devices. It was reported thatl
FE consid-erably increased with the increase of free electron concentration, which was related to the oxygen vacancies in a-IGZO thin films [1]. According to the above XPS results, the a-IGZO thin film depos-ited without oxygen incorporation had more oxygen vacancies leading to a higher free electron concentration. Therefore, thehighest
l
FEwas obtained for sample I, which was consistent with the previous reports[5]. In addition, sample III showed a lowerl
FEand a higher Vththan those of sample I. Compared with sample I, sample III using oxygen-rich IGZO film as the back channel layer, has less oxygen vacancies in the entire channel layer, thereby lead-ing to a lower free electron density in the bulk of channel layer. In this case, a less fraction of interface traps and/or traps in the chan-nel layer could be filled, resulting in a larger density of defects at the channel layer/gate insulator interface and thus a corresponding increase in Vth. Besides, a lowerl
FEfor sample II was not only attributed to a lower free electron density in the channel layer, but also a higher channel resistive and a higher contact resistance between channel layer and source/drain electrodes owing to the oxygen-rich film as the back channel layer [17]. Moreover, the equivalent maximum interface-state trap densities of three types of TFTs were shown in Table 1. It was observed that sample III exhibited a similar interface states with sample I, which was better than that of sample II. For sample II, with the introduction of oxy-gen to produce oxyoxy-gen-rich channel layer more traps could be cre-ated at the channel layer-gate insulator interface by the oxygen plasma damage, causing an increase in Nss[12]. The results indi-cated that an improved interface between channel layer and gate insulator can be achieved by using IGZO film deposited without oxygen incorporation.3.3. Effect of electrical bias stress
To investigate the device stability under electrical bias stress, DC positive and negative gate bias stresses (PBS/NBS) at room tem-perature in the atmosphere for 1500 s were applied. The variation of transfer curves for three types of a-IGZO TFTs under PBS condi-tion of Vgs= 20 V and Vds= 0 V are illustrated inFig. 4a–c respec-tively. All the devices exhibited positive shifts of Vthwith little change in S and
l
FE. The values ofDVthobtained at 1.5 k s for sam-ples I, II, and III were 4.15, 5.19, and 3.08 V, respectively. Generally,Table 1
Electrical characteristics of three a-IGZO TFTs: samples I, II, and III.
Samples I II III lFE(cm2/Vs) 4.00 1.74 3.65 S (V/dec) 0.80 2.62 0.87 Vth(V) 8.76 17.40 11.67 Ron/off 5.20 106 1.26 106 2.39 106 Nss(cm2/eV) 2.68 1012 9.27 1012 2.93 1012
the positive Vthshift with little or no change in S and
l
FEunder PBS is dominantly attributed to the electron trapping at or near the channel layer/gate insulator interface without the creation of new defects[18]. Among the three types of TFTs, the largest inter-face traps for sample II resulted in the largest value of Vthshift. Although samples I and III showed similar interface trap densities, a lower value of Vthshift was obtained for sample III. This might be related to the different back-channel layers between samples I and III, because the surface/ambience interaction can also impact the stability of unpassivated TFTs. It was reported that the adsorbed oxygen atoms on the a-IGZO exposed back-channel surface could introduce an acceptor-like surface state and cause charge trapping [10]. According to the XPS result, it suggested that a-IGZO thin films deposited with oxygen incorporation might show less oxygen adsorption in the ambience due to more oxygen content and less oxygen vacancies in the film. Therefore, a higher stability of Vth was obtained for sample III. The results implied that using IGZO film deposited with high oxygen flow rate as back-channel layer appeared to be as a barrier layer to improve the stability of a-IGZO TFTs.The transfer curves for samples I, II, and III under NBS condition of Vgs= 20 V and Vds= 0 V are shown inFig. 5. Samples I and III exhibited fairly small negative Vthshifts of 0.05 and 0.01 V, with nearly no change in
l
FEand S, which were similar with the report[19]. Contrary to the case in a-Si:H TFTs[20], the hole trapping at either the gate insulator or at the channel layer/gate insulator interface can be ignored under NBS in a-IGZO TFTs due to the neg-ligible holes in the n-type oxide semiconductor valence bands[19]. However, unlike samples I and III, sample II showed a positive shift of 1.54 V with a slight degradation of S and almost no change in
l
FE. These results indicated that the NBS-induced instability was dominated by the variation of oxygen vacancies at or near the channel layer/gate insulator interface. For sample II, sputtering at higher oxygen pressure could passivate oxygen vacancies and create accepter-like defects, e.g. metal vacancies, at or near thechannel layer/gate insulator interface. These defects could easily transform to fix negative charges after trapping electrons [12] and cause an effect of screening the gate voltage. In this case, an additional voltage had to be applied at the gate terminal to form a channel after exciting the trapped electrons, thereby causing a
Fig. 5. Transfer curves for samples (a) I, (b) II, and (c) III as a function of duration time under negative bias stress (Vgs= 20 V, Vds= 0 V).
Fig. 6. Electrical characteristics of a-IGZO TFTs with sputtered SiNxthin film as the
passivation layer: samples I+PL, II+PL, and III+PL. Transfer curves (Ids–Vgs) (a) at
positive shift in Vth. The specific mechanism will be elucidated by further experiments.
3.4. Effect of passivation layer
As oxide semiconductor and source/drain electrodes were deposited by sputtering, a 30 nm-thick SiNx thin film was also deposited by RF sputtering to serve as a passivation layer, achiev-ing all-sputtered a-IGZO TFTs at room temperature. Here, three types of TFTs: samples I+PL, II+PL, and III+PL, were fabricated to study the influence of sputtered SiNxpassivation layer on the de-vice performance.
Fig. 6shows the electrical characteristics of three types of a-IGZO TFTs with passivation layer. Compared with non-passivation TFTs, transfer characteristics of all devices with passivation layers exhibited a negative shift. Electrical parameters of the three types of a-IGZO TFTs with passivation layer are listed inTable 2. Not only the degradation of S but also a lower threshold voltage and a higher mobility were obtained for the passivated TFTs, which could be attributed to the effect of the deposition process of passivation layer [12]. In the deposition process of sputtered SiNxpassivation layer, more defects, such as oxygen vacancies induced by the broken metal–oxygen bond, were generated in the channel layer by the ion bombardment. Therefore, more free electrons were produced in channel layer, which resulted in a higher mobility. In addition, more interface traps could be filled by the increased free electrons,
causing a better interface and a lower Vth. On the other hand, the in-creased defects in the channel layer for passivated TFTs, led to a higher value of S than that of non-passivated ones.
Besides, among the three types of TFTs, sample III+PL showed the least S value. Generally, S value reflects not only the bulk trap density of the channel layer, but also the interface trap density at or near the interface between channel layer and gate insulator [1]. Since samples I+PL and III+PL had similar channel layer-gate insulator interface states, the critical change in the S value for sam-ple I+PL was ascribed to more defect generation in the back chan-nel than that of sample III+PL. Therefore, it can be concluded that using oxygen-rich thin film as back channel layer could reduce the plasma damage to channel layer during the passivation pro-cess. The one reason may be that the defects such as oxygen vacan-cies can be passivated by oxygen atoms in the oxygen-rich IGZO film, which played the same role as that in the post-treatment on the back channel, such as the N2O treatment[21]or the oxygen supply during the passivation process[12].
Figs. 7 and 8exhibit the variation of transfer curves for samples I+PL, II+PL, and III+PL under PBS (Vgs= 20 V and Vds= 0 V) and NBS (Vgs= 20 V and Vds= 0 V) tests, respectively. It was observed that all the devices showed a smaller threshold voltage shift than the devices without passivation layer, which was consistent with the previous report[10]. For PBS, theDVthobtained at 3.0 ks for sam-ples I+PL, II+PL, and III+PL were 0.33, 0.46, and 0.01 V, respectively. For NBS,DVthobtained at 3.0 ks for samples I+PL, II+PL and III+PL were 0.56, 0.77 and 0.54 V, respectively. The results indicated that the improvement in the stability of a-IGZO TFTs was obtained by sputtered SiNxpassivation layer.
The little Vthshift of passivated TFT was supposed to be related to the following reasons. One was that the sputtered SiNx passiv-ation layer could isolate the surface of a-IGZO thin film to the ambience, thus the absorption/desorption of oxygen and/or mois-ture on the a-IGZO can be prevented. The other one may be related to the interface states between channel layer and passivation layer,
Table 2
Electrical characteristics of a-IGZO TFTs with passivation layers: samples I+PL, II+PL, and III+PL.
Samples lFE(cm2/Vs) S (V/dec) Vth(V) Ron/off
I+PL 6.37 4.53 7.38 8.70 106
II+PL 4.17 4.28 4.12 7.00 106
III+PL 5.19 2.40 0.29 2.86 107
Fig. 7. Stress time dependence of transfer curve shifts in three different TFTs with passivation layer under positive gate bias stress (Vgs= 20 V, Vds= 0 V): samples (a) I+PL, (b)
where there existed traps induced by ion bombardment [12]. When the PBS test was applied, the channel layer/passivation layer interface was supposed to be positive charges trapped at the inter-face when electrons were accumulated in the front a-IGZO/insula-tor interface under the PBS, resulting in some free electron accumulated near or in the back channel. The effect compensated the electrons trapped in the a-IGZO/insulator interface or injected to the gate dielectric. Therefore, the devices with passivation layer had a smaller Vthshift under the PBS. While the NBS test was ap-plied, the electrons were trapped at the channel layer/passivation layer interface, resulting in an additional current pathway on the back channel surface and less gate voltage to turn on the device. Thus, it can be deduced that both the channel layer/gate insulator and the channel layer/passivation layer interfaces play important roles in the device stability of passivated TFTs. Since sample III+PL showed the least traps at the channel layer/gate insulator and the channel layer/passivation layer interfaces, as mentioned above, the best stability could be obtained for sample III+PL among the three types of a-IGZO TFTs.
4. Conclusion
In conclusion, it was found that the stability of a-IGZO TFTs was improved by double stacked channel layer. For positive and nega-tive bias stress test, the smallest shift value of Vthfor the TFT with stacked channel layer was achieved (3.08 V for PBS and 0.01 V for NBS). Moreover, with the sputtered SiNx thin film served as the passivation layer, the stability of a-IGZO TFTs was improved effec-tively. For positive and negative bias stress test, the TFT with stacked channel layer still showed the smallest Vthshift (0.0 l V for PBS, 0.54 V for NBS). The improvement in the device charac-teristics was attributed to lower trap density at channel layer/gate insulator interface by using a-IGZO film deposited without oxygen incorporation, and the improvement of back channel layer by using
a-IGZO film deposited with high oxygen incorporation which may behave as a barrier layer to reduce oxygen adsorption induced by ambient effect and/or damage caused by ion bombardment. How-ever, it should be noted that further work to optimize the passiv-ation layer deposition layer process is necessary because inadvertent damage to the TFT due to the insufficiently optimized passivation layer deposition layer process has been observed in our samples. Anyway the experimental results exhibit that the proper control of the front channel and back channel plays an important role in improving the stability of a-IGZO TFTs.
Acknowledgements
This work was supported by National 973 project (Grant No. 2013CB328803) and National Natural Science Foundation of China (Grant No. 61136004). R.Z. Zhan would like to thank L. Gong from Sun Yat-sen University for XPS measurement.
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