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Electrical Properties of High-κ Praseodymium Oxide Polycrystalline Silicon Thin-Film
Transistors with Nitrogen Implantation
View the table of contents for this issue, or go to the journal homepage for more 2008 Jpn. J. Appl. Phys. 47 853
(http://iopscience.iop.org/1347-4065/47/2R/853)
Electrical Properties of High- Praseodymium Oxide Polycrystalline Silicon
Thin-Film Transistors with Nitrogen Implantation
Chih-Kang DENG, Hong-Ren CHANG, and Bi-Shiou CHIOU Institute of Electronics, National Chiao-Tung University, Hsinchu 30010, Taiwan
(Received October 28, 2007; accepted November 25, 2007; published online February 15, 2008)
This paper demonstrates the polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with high- praseodymium oxide (Pr2O3) gate dielectric and nitrogen implantation to achieve high-performance characteristics for the first time. Nitrogen atoms
with various dosages are implanted into amorphous silicon (-Si) film to passivate the grain boundary trap states during solid-phase crystallization (SPC) annealing. From experimental results, the electrical characteristics of the Pr2O3 poly-Si TFT
implanted with the nitrogen dosage of 5 1012cm2could be greatly improved. In addition, a better hot-harrier immunity of
high- Pr2O3poly-Si TFT could be also obtained. [DOI:10.1143/JJAP.47.853]
KEYWORDS: polycrystalline silicon (poly-Si) thin-film transistor (TFT), praseodymium oxide (Pr2O3), nitrogen implantation,
solid-phase crystallization (SPC)
1. Introduction
Recently, polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used for pixel elements and driving circuits in active-matrix liquid-crystal displays (AMLCDs) to realize system-on-panel (SOP) technology.1–3) Because poly-Si TFTs are fabricated on inexpensive glass substrate, low-temperature process is required for the realization of commercial flat-panel displays (FPDs). The solid-phase crystallization (SPC) process with maximum process temperature limiting to 600C is widely used to recrystallize amorphous silicon (-Si) film due to its low production cost and good grain-size uniformity.4,5)However, only by using SPC technology, it is difficult to develop a high-performance poly-Si TFT with low threshold voltage, low subthreshold swing, and high driving current to drive the liquid crystal on a large size panel. In order to break through this challenge, integrating high- gate dielectric into poly-Si TFT was proposed to increase the gate capacitance density for keeping a high current drivability and a low gate leakage.6–8)
In addition, trap states at interface and grain boundaries could be rapidly filled up to improve the subthreshold swing by using high- dielectric applied on poly-Si TFT.7,8) However, such high gate capacitance density would con-tribute to a high electric field at the gate-to-drain overlap area, resulting in rather high field-enhanced emission rates via the grain-boundary trap states.9,10)Therefore, the poly-Si TFTs with high- gate dielectrics would suffer from more undesirable gate-induced drain leakage (GIDL) currents. In order to alleviate the GIDL current issues, the hydrogenated plasma treatment was proposed to introduce the hydrogen atoms into the poly-Si film to effectively passivate the grain-boundary trap states near the drain side.11–13) Nevertheless, the hydrogenated TFTs suffer from a serious instability issue owing to lots of easily breaking Si–H bonds in poly-Si film.14)
In this paper, we successfully demonstrated the nitrogen-implanted technique applied on the poly-Si TFTs with high- gate dielectric praseodymium oxide (Pr2O3). The electrical characteristics and reliability of the Pr2O3 poly-Si TFTs could be significantly improved by employing the
nitrogen-incorporation technique. Therefore, our proposed Pr2O3 poly-Si TFTs with nitrogen-implanted poly-Si films could satisfy the matrix devices and high-speed driving circuit applications.
2. Experimental Procedure
The main fabrication steps are summarized below and shown in Fig. 1. First, the 500-nm thermal oxide was grown on 6-in. Si wafer and used to simulate the glass substrate. And then, an undoped -Si film with 50 nm thick was deposited by using low-pressure chemical vapor deposition (LPCVD) system at 550C. Following, the nitrogen atoms with various dosages of 0 (control sample), 5 1012cm2, and 5 1013cm2, were implanted into the 50-nm -Si film with an ion implantation energy of 10 keV, as shown in Fig. 1(a). The ion implantation energy of 10 keV was chosen so that the projected range of the nitrogen atoms is about 25 nm, the half of the thickness of -Si film. After nitrogen
Fig. 1. The main process steps of the Pr2O3 poly-Si TFT with
nitrogen-implanted poly-Si film.
E-mail address: [email protected] #2008 The Japan Society of Applied Physics
implantation, the conventional SPC annealing was processed at 600C for 24 h in nitrogen ambient to crystallize -Si film into poly-Si film. Subsequently, the active regions were defined, and then the Pr2O3 gate dielectric film was deposited by physical vapor deposition (PVD) system. Following, the Pr2O3 gate dielectric was subjected to rapid thermal annealing (RTA) at 600C for 1 min in oxygen ambient to improve the quality of Pr2O3 gate dielectric, as shown in Fig. 1(b).
The 200-nm tantalum nitride (TaN) film was deposited by PVD system and used to be metal gate electrode of thin-film transistor. After TaN film was deposited, the chlorine-based plasma etching process capable of stopping on the Pr2O3 layer was used to pattern the TaN metal gate electrode. As shown in Fig. 1(c), a self-aligned phosphorus implantation was performed with the dosage and the energy of 5 1015cm2 and 90 keV, respectively. And then, phosphorus dopants in source and drain regions were activated by RTA process at 600C for 1 min in nitrogen ambient. After 300-nm tetraethoxylsilane (TEOS) oxide film used as inter-layer dielectric (ILD) passivation was deposited by plasma-enhanced chemical vapor deposition (PECVD) system at 300C, the contact holes were patterned by two-step contact etching process, as shown in Fig. 1(d). The 300-nm ILD passivation and Pr2O3 gate dielectric on source and drain regions were sequentially removed by buffered oxide etch (BOE) and H3PO4: HNO3 : CH3COOH : H2O (50 : 2 : 10 : 9) mixed solution. Since such mixed solution has rather high etching selectivity of the Pr2O3 film to the ILD passivation, the Pr2O3film could be completely etched away by an excess over etching. After the contact holes were etched, the aluminum (Al) film of 500 nm was deposited by PVD system. Finally, the Al pad was patterned, as shown in Fig. 1(e), and then the nitrogenous poly-Si TFTs with Pr2O3 gate dielectric were accomplished. For comparison, the control poly-Si Pr2O3TFT without the nitrogen implantation (DN¼0) was also prepared by the same process flow. In addition, note that all poly-Si TFTs had no plasma treatment in this work.
3. Results and Discussion
The capacitance–voltage (C–V) characteristic and the leakage current density of the Pr2O3film on Si substrate are shown in Fig. 2. The Pr2O3 films on Si substrate and on poly-Si film are fabricated at the same process. From the cross-sectional transmission electron microscope (TEM) image of the proposed poly-Si TFT in inset of Fig. 2, the thickness of Pr2O3 gate dielectric after RTA treatment in oxygen ambient is about 42 nm and the thickness of poly-Si channel is around 50 nm. The leakage current of the 42-nm Pr2O3 gate dielectric on Si substrate is below 1 mA/cm2 before the thin-film breakdown about 7 MV/cm. The accumulation capacitance density (Cacc) at the applied voltage of VAPP¼ 4 V is 432 nF/cm2. Therefore, the equivalent-oxide thickness (EOT) and the effective dielectric constant value () of 42-nm Pr2O3 gate dielectric extracted from the accumulation capacitance density are 8 nm and 25, respectively. Such high capacitance density and low leakage current represent that the Pr2O3thin film is a good candidate for gate dielectric application. Therefore, it could be expected that the poly-Si TFT with the Pr2O3gate dielectric
has a well gate controllability resulting in better electrical characteristics compared to that with conventional plasma TEOS oxide as gate dielectric.
Figure 3 shows the transfer characteristics (IDS{VGS) of the Pr2O3 poly-Si TFTs with various nitrogen dosages (DN) of 0 (control sample), 5 1012cm2, and 5 1013cm2, which are measured at VDS¼0:1 V. The channel length (L) and the channel width (W) of the Pr2O3 poly-Si TFT are 10 and 5 mm, respectively. When the nitrogen dosage is increased to 5 1012cm2, the performance of the Pr2O3 poly-Si TFTs could be improved, including threshold voltage (VTH) and transconductance (Gm). The transconduc-tance is defined as @VGS=@ ln IDS measured in the switching region. However, the subthreshold swings (S.S.) of the Pr2O3 poly-Si TFTs seem no change with various nitrogen dosages. As the papers reported,15,16) the interface traps states and the grain boundary trap states dominate the electrical characteristics of poly-Si TFT. The deep trap states at grain boundaries mainly affect on threshold voltage but less on transconductance. Besides, the tails states at the interface and grain boundaries mainly contribute to the degradation of transconductance. The subthreshold swing
Fig. 2. The C–V characteristic and leakage current density of the Pr2O3
film on Si substrate. The insert is the cross-sectional TEM image of the proposed Pr2O3poly-Si TFT.
Fig. 3. The transfer characteristics of the Pr2O3poly-Si TFTs with various
nitrogen dosages of 0 (control sample), 5 1012cm2, and 5 1013
cm2under V
DS¼0:1 V.
mainly depends on the deep interface traps states.16) As shown in Fig. 3, such the same subthreshold swings mean that the interface traps states at the Pr2O3 gate dielectric/ poly-Si channel interface are not changed with various nitrogen dosages. Therefore, the electrical improvement of the Pr2O3poly-Si TFT by using nitrogen implantation could be attributed to the reduction of the grain boundary trap states within poly-Si film during conventional SPC anneal-ing. However, when the nitrogen dosage is increased to 5 1013cm2, the electrical characteristics the Pr
2O3 poly-Si TFT would be degraded. The overdose of nitrogen implantation (DN¼5 1013cm2) in -Si film would obstruct -Si film crystallized to poly-Si film compared to that without nitrogen implantation (control sample). There-fore, the turn-on current of the Pr2O3 poly-Si TFT without large size of poly-Si grains is decreased.
Figure 4 compares the transfer characteristics (IDS{VGS) of the Pr2O3 poly-Si TFTs with nitrogen dosages of 0 and 5 1012cm2 under VDS¼0:1 and 1 V. The insert table summarizes the electrical parameters. The threshold voltage (VTH) is defined as the gate voltage required a normalized drain current of IDS ¼ ðW=LÞ 100 nA at VDS¼0:1 V. The ON/OFF current (ION, max=IOFF, min) ratio is defined as that ratio of the maximum on-state current to the minimum off-state current at VDS ¼1 V. The threshold voltage (VTH), field-effective mobility (FE) could be improved from 2.15 to 1.9 V and 34 to 47.4 cm2V1s1, respectively. However, the S.S. and ON/OFF current ratio of them are almost the same with the value about 242 mV/dec and over the sixth power of ten, respectively. Besides, the GIDL current at VDS ¼1 V and VGS ¼0 V could be also suppressed by a half-order magnitude by using nitrogen implantation with suitable dosage of 5 1012cm2. The GIDL current in poly-Si TFT results from the field-enhanced emission through the trap states near the drain side.13)Using moderate dosage of nitrogen atoms implanted into the poly-Si film can effec-tively passivate the trap states at grain boundaries, and thus lead to reduce GIDL current.
The output characteristics (IDS{VDS) of the Pr2O3 poly-Si TFTs with nitrogen dosages of 0 and 5 1012cm2 are shown in Fig. 5. The driving current of the Pr2O3 poly-Si TFT with nitrogen implantation has about 40% improvement
at VGS ¼4 V, compared to the control sample. The pervious studies6–8)have been reported that using various high- gate dielectrics on poly-Si TFTs could quickly fill the trap states in poly-Si channel to improve device electrical character-istics due to its well gate controllability. However, in this work, using the nitrogen implantation technique on the Pr2O3poly-Si TFTs will further passivate these trap states in poly-Si film and improve the device performance.
Finally, the hot-carrier reliability on the Pr2O3 poly-Si TFTs with and without the nitrogen implantation is inves-tigated in Fig. 6. All devices are biased at VGS¼VDS ¼4 V, which is a hot-carrier stress condition. The degradation of drain current is defined as ION=ION,0, where the ION¼ ION,sION,0, ION,0is initial ION, and ION,sis the IONfor each stress time. The degradation of IONof the Pr2O3poly-Si TFT with nitrogen dosages (DN) of 5 1012cm2 is about 5% after 1000-s hot-carrier stress, which is superior to that without nitrogen implantation (control sample). The ION degradation of control sample would be saturated at 70% after 200-s carrier stress. It is reported that the hot-carrier stress easily breaks the weak Si–Si and Si–H bonds (with the bonding energy of 70 kcal/mol) to generate the interface states and grain boundary states in poly-Si film.14,17) If the moderate dosage of nitrogen is implanted
Fig. 4. The transfer characteristics (IDS{VGS) of the Pr2O3poly-Si TFTs
with the nitrogen dosages of 0 and 5 1012cm2under V
DS¼0:1 and
1 V. The inset is the table of the electrical parameters.
Fig. 5. The output characteristics (IDS{VDS) of the Pr2O3 poly-Si TFTs
with nitrogen dosages of 0 and 5 1012cm2.
Fig. 6. The drain current degradation for the Pr2O3poly-Si TFTs with and
into -Si film during SPC annealing, the stronger Si–N bonds with a higher bonding energy of 81 kcal/mol would replace the weak Si–Si and Si–H bonds to achieve excellent hot-carrier endurance.17) It would be note that the Pr
2O3 poly-Si TFT with nitrogen dosages of 5 1013cm2 even has a higher stress current that is under more serious hot-carrier stress condition than that without nitrogen implanta-tion. On the other hand, for the Pr2O3 poly-Si TFT with nitrogen dosages of 5 1013cm2, its ION degradation would be saturated at 50% after 400-s hot-carrier stress, which seems better than control sample (DN¼0). This reason could be attributed to that the overdose of nitrogen implantation would restrict -Si film crystallization and result in the inferior electrical characteristics of the Pr2O3 poly-Si TFT, as shown in Fig. 3. The hot-carrier stress condition on device with nitrogen dosages of 5 1013cm2 is more alleviative than control sample under the same stress biased. In summary, the Pr2O3poly-Si TFT with applicable nitrogen incorporation in poly-Si channel has better im-munity on the hot-carrier stress, compared to the control sample.
4. Conclusions
High-performance poly-Si TFTs integrated nitrogen im-plantation and Pr2O3gate dielectric are demonstrated for the first time. High gate capacitance density and high breakdown electrical field are introduced from the Pr2O3gate dielectric and TaN metal gate. The electrical characteristics and reliability are significantly improved by nitrogen implanta-tion technique into the poly-Si TFT with Pr2O3 gate dielectric without additional plasma treatment. Therefore, the proposed Pr2O3 poly-Si TFT with nitrogen implantation would be a promising candidate for matrix devices and high-speed driving circuit applications in the future.
Acknowledgements
The authors would like to thank the apparatus support form National Nano Device Laboratories (NDL) and the financial support from the National Science Council (NSC) under contact no. NSC-96-2221-E-009-106.
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