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International Journal of Production
Research
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An analysis of the ceiling height
requirement for a large-scale
semiconductor fab
Muh-Cherng Wu a , Chang-Fu Shih a & Chen-Fu Chen a a
Department of Industrial Engineering and Management , National Chiao Tung University , 1001 Dah-Shei Road, Hsin-Chu City, Taiwan (ROC)
Published online: 11 Jun 2009.
To cite this article: Muh-Cherng Wu , Chang-Fu Shih & Chen-Fu Chen (2010) An analysis of the
ceiling height requirement for a large-scale semiconductor fab, International Journal of Production Research, 48:12, 3697-3706, DOI: 10.1080/00207540902814322
To link to this article: http://dx.doi.org/10.1080/00207540902814322
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International Journal of Production Research Vol. 48, No. 12, 15 June 2010, 3697–3706
An analysis of the ceiling height requirement
for a large-scale semiconductor fab
Muh-Cherng Wu*, Chang-Fu Shih and Chen-Fu Chen
Department of Industrial Engineering and Management, National Chiao Tung University, 1001 Dah-Shei Road, Hsin-Chu City, Taiwan (ROC)
(Received 24 September 2008; final version received 8 February 2009) This paper proposes the proposition that the fab ceiling height may become a bottleneck for throughput in a large-scale semiconductor fab. To justify the proposition, we propose a systematic approach for the design of the fab ceiling height. In this approach, we develop a queuing network model to evaluate the cycle time performance of a fab design under a target throughput. This queuing network model is adapted from Connor et al. [1996. A queueing network model for semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing, 9 (3), 412–427] by additionally treating the transportation facilities as finite-capacity resources. Numerical experiments were carried out. The results indicate that a large-scale fab with an inappropriate ceiling height may limit the installation of transportation capacity, which, in turn, limits the utilisation of tool capacity, and thus lowers the fab throughput that can be achieved. Keywords: production management; semiconductor manufacture
1. Introduction
Semiconductor manufacturing is capital intensive. A fab (i.e. a semiconductor factory) for manufacturing 12 inch wafers may cost about 2–3 billion dollars, of which equipment expenditure accounts for about 75%. Therefore, maintaining the equipment at a high utilisation is very important. One may propose to obtain high equipment utilisation by building the fab as large as possible, rather than building multiple small fabs. The rationale behind this is that consolidating multiple functionally identical workstations into one tends to increase equipment utilisation, due to the effect of capacity pooling.
When constructing a new large-scale fab, most companies adopt a space-ahead strategy. That is, the whole space required for the large-scale fab is built in advance and equipment is gradually moved in over time based on market demand. The space-ahead strategy arises due to two concerns. First, the relative cost of equipment is much higher than fab space. Second, the lead time for acquisition of fab space is much longer than that of equipment.
Compared with a small fab, the transportation distance for a large-scale fab would be longer due to the requirement of a larger fab space. As a result, the transportation system for material handling may unexpectedly become the bottleneck for a large-scale fab. One idea for solving this problem is to increase the number of transportation tracks, which
*Corresponding author. Email: mcwu@mail.nctu.edu.tw
ISSN 0020–7543 print/ISSN 1366–588X online ß 2010 Taylor & Francis
DOI: 10.1080/00207540902814322 http://www.informaworld.com
are usually installed overhead in fabs. However, such an installation might not be feasible due to the limit of the fab ceiling height, which was determined in the early stage of fab construction. An appropriate design for the fab ceiling height might thus be very important.
The issue concerning the fab ceiling height limit has not been raised in the literature. In a small fab, such an issue would not arise because the transportation distance is relatively short, and transportation would not be the bottleneck. For a large-scale fab, running at an early stage (i.e. equipment capacity not fully installed), this issue would not arise either because the number of jobs transported in the fab would be relatively small. For a large-scale fab running at a mature stage (i.e. equipment capacity fully installed), the transportation system may unexpectedly become the bottleneck.
This paper proposes the proposition that the fab ceiling height may become a bottleneck for throughput in a large-scale fab. To do so, we propose a systematic approach for the design of the fab ceiling height. In this approach, we use a queuing network model to evaluate the cycle time performance for a fab design under a target throughput. This queuing network model is adapted from Connors et al. (1996) by additionally treating the transportation facilities as finite-capacity resources. Numerical experiments are carried out to support the proposition.
The remainder of this paper is organised as follows. Section 2 reviews the relative literature, including tool planning, transportation design and facility layout for fabs. Section 3 describes the queuing network model. Section 4 presents the systematic approach for the design of the fab ceiling height. Numerical experiments are presented in Section 5 and concluding remarks in Section 6.
2. Literature review
Building a new semiconductor fab involves a sequence of decisions: tool planning, facility layout, and automatic material handling system (AMHS) design and management. Prior studies have established significant milestones, yet the design of the fab ceiling height has rarely been considered. An analysis of prior studies is presented below.
The decision for tool planning is to determine the optimal number of tools (i.e. machines) for a fab with a target performance. Some studies have modeled this decision as an integer program (Swaminathan 2000, Hood et al. 2003). Others have used a queuing network model as a fab performance evaluator in order to obtain an optimal tool portfolio (Connors et al. 1996, Wu et al. 2005).
Two survey papers have been published (Gaurav and Sunderesh 2006, Montoya-Torres 2006) on semiconductor facility layout and AMHS design/management. One decision for the facility layout addresses how to design a fab configuration (Peters and Yang 1997, Pillai et al. 1999). The other addresses how to cluster tools into groups and determine an optimal placement for each tool group (Geiger et al. 1997, Meyersdorf and Taghizadeh 1998, Hseih and Hung 2004).
The decisions for AMHS design involve the layout of transportation networks (Mackulak and Savory 2001, Ting and Tanchoco 2001), determining the number of vehicles (Egbelu 1987, Talbot 2003), and determining the methods for connecting transport (Lin et al. 2003). In contrast, AMHS management is concerned with traffic control issues, such as the dispatching priority of vehicles (Kuo and Huang 2006),
the traffic zone control strategy (Wang and Lin 2004), and the determination of efficient transportation paths for vehicles (Jang et al. 2001).
In contrast to prior studies, we focus on the design of the fab ceiling height; that is, how many layers of transportation networks would be required for a large-scale fab. The greater the number of transportation layers, the higher is the required fab ceiling height.
3. Queuing network model
The queuing network is an analytic method that can be used to model a factory and evaluate its performance. Much literature on the development of the queuing network model for a semiconductor fab has been published (Nazzal and Mcginnis 2007, Shanthikumar et al. 2007). In this research, we propose a queuing network model by adapting that developed by Connors et al. (1996).
In a queuing network, a type of workstation is modeled as a queue, where a workstation denotes a group of functionally identical machines. A job to be processed by a particular workstation is taken to be an entity arriving at the queue that models the workstation. The greater the job arrival rate to a queue, the higher is the utilisation of the queue, and the longer is the job’s cycle time to pass through the queue. A semiconductor fab, comprising a group of workstations, is a network of queues. With a job reentry characteristic, a job in a fab may visit a workstation multiple times. The cycle time for a job to pass through a fab can be obtained by adding all the cycle times of its visiting queues.
Taking the queuing network developed by Connors et al. (1996) as a performance evaluation system for a fab, its input/output relationship can be described as
CT ¼ f ðTh, PX, MX Þ:
The output of the system is CT (the average cycle time for a job to pass through the fab). The input involves three components: Th (throughput of the fab), PX (product mix), and MX(machine mix). The throughput (Th) denotes the number of jobs produced by the fab monthly. The product mix (PX) denotes the relative percentage of each type of product produced. The machine mix (MX) denotes the number of tools for each tool type. For a particular set of MX and PX, the larger Th is, the larger CT is; their relationship is called a throughput–CT curve and is shown in Figure 1. The throughput curve may vary under different sets of MX and PX.
In the queuing network model (Connors et al. 1996), it is implicitly assumed that the transportation capacity is infinite; as a result, the transportation time between any two workstations is zero. We adapted their queuing network model by taking transportation
Cycle Time
Throughput
Figure 1. Relationship between cycle time and throughput.
International Journal of Production Research 3699
facilities as finite-capacity resources. The greater is the traffic rate, the greater is the possibility of having a traffic jam, and the longer is the CT. That is, the input/output relationship of our queuing network model can be described as
CT ¼ f ðTh, PX, MX, TrafficÞ,
where Traffic denotes the transportation capacity installed in the fab.
The modeling of Traffic is done by taking a finite length of transportation track as a queue. Such modeling requires an explicit description of the fab layout. In this research, we assume the fab layout is a spine configuration. As shown in Figure 2, the main transportation system is located in the centre; and several bays are located on the two sides. A bay is a space that accommodates several types of workstation. The main transportation system, designed to be two-way eligible for traffic, is used to transport jobs among different bays. In each bay, a local transportation system, designed to be one-way eligible for traffic, is used to transport jobs within the bay.
In Figure 3, there are several nodes in the transportation layout. A node represents either a station (e.g., node s1 in Bay_1) for loading a job from/to a workstation in a bay, or a turning point (e.g., node t1 in Bay_1) on transportation paths. A transportation path
Bay_1 Bay_2 Bay_3 Bay_4
Bay_5 Bay_6
Bay_7 Bay_8
Main Transportation System
Figure 2. Spine configuration of a semiconductor fab.
Bay_1
Main Transportation System s2 s1 t2 t1 s3 s4 t3 t4
Figure 3. Main transportation is two-way and bay transportation is one-way.
between any two consecutive nodes (also called a transportation segment) is modeled as a queue. The traffic rate over a transportation segment is modeled as the arrival rate of the queue. The traffic rates in different transportation segments may be different, due to varying traffic requirements among different bays. By inclusion of queues for modeling transportation segments, we create a larger queuing network than that reported previously (Connors et al. 1996).
4. Design of the fab ceiling height
Traditionally, each transportation path in a fab layout is a single-layer design. One way to increase the transportation capacity is by changing a single-layer into a multiple-layer transportation system. The more transportation layers there are, the greater the transpor-tation capacity, and the higher the fab ceiling requirement.
As already stated, we have proposed a queuing network model, CT ¼ f ðTh, PX, MX, TrafficÞ. Based on this model, we have developed an approach to design the ceiling height for a fab. Consider such a fab design problem, where Th0(target throughput), PX0
(product mix) and a target CT0 (average cycle time) are given, then we need to determine
MX (the machine mix or the required number of tools for each tool type) and Traffic (the required number of layers for each transportation path).
To describe the fab design approach, we define M ¼ ðm1, . . . , mkÞas a particular MX,
where mi denotes the number of tools for tool type i, and define Tr¼ ðr1, . . . , rqÞ as a
particular Traffic, where rj denotes the number of layers for transportation path j.
We assume that all transportation paths are equipped with the same number of layers, that is ri¼rj for 1 i, j q. For example, Tr¼ ð2, . . . , 2Þ denotes a two-layer
transportation system.
This assumption is based on two rationales. First, given a ceiling height eligible for installing a two-layer transportation system, practitioners would prefer to equip each transportation path with two layers—in a one-stop project. Evolutionally adding the number of transportation paths might seriously interrupt production and is not encouraged. Secondly, the cost of the transportation facility is much less than that of the machine. Therefore, if the fab ceiling is high enough, increasing the transportation capacity by a whole layer might not cost much, compared with the benefit that may arise due to greater machine utilisation. For an advanced 12 inch wafer fab, the total expenditure is about 3.6 billion dollars. The expenditure for adding one more transpor-tation layer (including hardware and software) is around 60 million dollars, about 1.6% of the original total expenditure. That is, it would be beneficial to add one more transportation layer if such a facility enhancement can increase throughput by more than 1.6%.
The fab design approach is described by a procedure called Fab_Ceiling_Design. Procedure Fab_Ceiling_Designs
. Step 1: Design MX by assuming that all transportation times are zero. That is, given Th0, PX0 and CT0, determine MX.
Represent the obtained MX by M ¼ ðm
1, . . . , mkÞ.
. Step 2: Design Traffic by considering the limit of the transportation capacity. That is, given Th0, PX0 and CT0and M, determine Traffic.
Represent the obtained Traffic by T
r ¼ ðr1, . . . , rqÞ, where r1¼ ¼rq.
International Journal of Production Research 3701
In procedure Fab_Ceiling_Design, its two steps are both based on a marginal allocation algorithm (Connors et al. 1996), with only a minor difference. Details of the two steps are described below by two procedures, respectively called Design_MX and Design_Traffic.
Procedure Design_MX
. Step 1: Determine an initial solution M0, not considering the cycle time constraint.
– Given Th0 and PX0, we intend to determine a minimum number of tools for
each tool type.
– Based on the operation times for each product route, we can aggregate all operations associated with each tool type, and compute its monthly required machine time, and in turn determine the required minimum tool number. – Represent the obtained solution by Mð0Þ¼ ðm01, . . ., m0kÞ.
. Step 2: Determine M.
– Given Th0, PX0, CT0 and Mð0Þ, we intend to determine M.
– Transportation times are assumed to be zero. The queuing network for modeling a fab is CT ¼ f ðTh, PX, MX Þ.
– Use the marginal allocation method to add tools Set i ¼ 0 and flag ¼ ‘start’
While (flag ¼ ‘start’) Do CTði Þ¼f ðTh 0, PX0, MXði ÞÞ If CTði Þ> CT 0 then mðiþ1Þj ¼m ði Þ
j þ1 ( j is the tool type with the highest utilisation)
mðiþ1Þj ¼mjði Þ, for j 6¼ j, 1 j k
i ¼ i þ1
Else flag ¼ ‘stop’ Endif
Endwhile Set M ¼Mði Þ
Procedure Design_Traffic
. Step 1: Design Traffic; considering the limit of the transportation capacity. – Given Th0, PX0 and CT0 and M, determine Traffic.
– Use the marginal allocation method to add transportation capacity Set i ¼ 1 and flag ¼ ‘start’
While (flag ¼ ‘start’) Do CTði Þ¼f ðTh
0, PX0, M, Trði ÞÞ, where Trði Þ¼ ði, . . . , i Þ
If CTði Þ4 CT
0 then i ¼ i þ 1
Else flag ¼ ‘stop’ Endif
Endwhile Set T
r ¼Trði Þ.
5. Numerical experiments
Numerical experiments were carried out to justify the importance of the fab ceiling height design. Test data are supported by a fab that manufactures 12 inch wafers, but its identity has been withheld for proprietary reasons. Three types of products are produced. The number of operations for manufacturing products A, B and C are, respectively, 781, 700 and 650. The average processing time for an operation is about 30 min. The fab layout is a spine configuration that involves 15 bays, 60 workstations, and 150 transportation segments. That is, there are 210 servers in the queuing model.
Assumptions associated with the calculation of transportation time are described below. The transportation speed is 4.0 m s1. The area of a fab that produces 45k wafers per month is 100 m 200 m, and its total tool number is about 660 for a particular product mix (A : B : C) ¼ (5 : 2 : 3). The area required for a fab is proportional to the total number of tools. That is, a fab that has 800 tools would require an area of ð800=660Þ 100 m 200 m, which can be interpreted as ½ð800=660Þ1=2100 m ½ð800=660Þ1=2200 m. This implies that the distance of a particular transportation path in a larger fab would be ð800=660Þ1=2¼1:10 times that of a smaller fab. As a result, the transportation time would also become longer, 1.10 times that of the smaller fab.
For a particular product mix (A : B : C) ¼ (5 : 2 : 3) with a target cycle time CT0¼35
days, we attempt to evaluate the fab performance under various transportation layer designs for different target throughput Th0 (number of output wafers per month). As
shown in Table 1, at a lower Th0(e.g., 25k), a single-layer design is sufficient to fully utilise
the tool capacity. Yet, at a higher Th0, using a single-layer design may result in
under-utilisation of tool capacity and yield a low actual throughput—only 80% of the target throughput when Th0¼30k. The larger Th0is, the more serious the tool under-utilisation
problem. Tool under-utilisation is due to the fact that the single-layer transportation system unexpectedly becomes the bottleneck of the manufacturing system. Therefore, increasing the number of transportation layers would overcome this deficiency. For example, to fully utilise tool capacity, we need a two-layer design when Th0 2 f30k, 35k, 40kg and we need a three-layer design when Th02 f45k, 50k, 55k, 60kg.
As stated above, the investment required to add one more transportation layer is about 60 million dollars. To determine how many transportation layers to use for a production scenario, we need to carry out a cost/benefit analysis. Let Qi,iþ1 represent the annual
Table 1. Transportation layer designs for various Th0 (number of output wafers per month) for
a product mix (A : B : C) ¼ (5 : 2 : 3) with CT0¼35 days.
Target (Th0) Tool number Area ratio (%) Transportation time ratio (%) One-layer design actual throughput (k) Two-layer design actual throughput (k) Three-layer design actual throughput (k) 25k 382 57.79 76.02 25 25 25 30k 448 67.78 82.33 24.2 30 30 35k 518 78.37 88.52 27.33 35 35 40k 594 89.86 94.80 25.53 40 40 45k 661 100 100 24.2 44.08 45 50k 727 109.98 104.87 23.08 46.15 50 55k 798 120.73 109.88 22 44 55 60k 875 132.38 115.05 21.03 42.08 60
International Journal of Production Research 3703
increase in throughput on addition of one more layer to a fab originally equipped with i transportation layers. For the case Th0¼45k in Table 1, we can compute
Q1,2¼ ð44:08k 24:2kÞ12 ¼ 238:56k wafers year1
and
Q2, 3¼ ð45:0k 44:08kÞ12 ¼ 11:04k wafers year1:
Let r be the gross margin per wafer and p the average selling price per wafer. According to industry experience, we reasonably assume r ¼ 40%, p ¼ 2500 dollars, and all fab equipment completely depreciates in 5 years. Then, on a 5-year time horizon, the benefit of moving from one layer to two layers is 5Q1, 2rp ¼1192.8 million dollars. The rate
of return in this case is 1192.8/60 ¼ 19.88—a tremendous payback! Accordingly, we obtain that the rate of return by moving from two layers to three layers is only 0.92—it is not so profitable to move to a three-layer design. Table 2 shows the rate of return obtained for each throughput case of Table 1. From Table 2 we can see that adding one more transportation layer can yield a significant payback in many cases. Therefore, we should give thoughtful consideration to the ceiling height for a large-scale semiconductor fab.
Table 1 also reveals an interesting research issue—the optimal scale of a semiconductor fab. At Th0¼60k, 875 tools are needed for a single-fab design, yet 896 (448*2) tools are
required if we build two fabs (each with Th0¼30k). The tool cost for adopting a two-fab
design would be higher. However, a layer transportation design is needed for the two-fab configuration, whereas a three-layer transportation design is needed for a single-two-fab configuration. As a result, the cost of the transportation facility for the two-fab design as well as the operational cost of clean room space would become lower. The trade-off of the aforementioned costs points out the importance of examining the optimal scale for a semiconductor fab.
Note that, at a particular Th0, different product mixes might require different layer
designs. For example, in Table 3, for Th0¼30k, a single-layer design is appropriate
when (A : B : C) ¼ (4 : 3 : 3), but is not so satisfactory when the product mix is (A : B : C) ¼ (5 : 2 : 3). Likewise, when Th0¼45k, we need a three-layer design for
(A : B : C) ¼ (5 : 2 : 3), but only a two-layer design for (A : B : C) ¼ (4 : 3 : 3). Table 2. Rates of return resulting from the addition of one more transportation layer, where Ri!j denotes the rate of
return by moving from i layers to j layers.
Rate of return (r ¼ 40%, p ¼ 2500) Target (Th0) R1!2 R2!3 25k 0 0 30k 5.80 0 35k 7.67 0 40k 14.47 0 45k 19.88 0.92 50k 23.07 3.85 55k 22.00 11.00 60k 21.05 17.92
6. Concluding remarks
This paper highlights the importance of the fab ceiling height when building a new semiconductor fab. To efficiently utilise tool capacity, one trend is to build the fab as large as possible in order to exploit the effect of capacity pooling. Yet, the transportation distance for a large-scale fab is longer; as a result, the transportation facility might unexpectedly become the bottleneck. This in turn would lead to the under-utilisation of tool capacity and decrease the throughput. To install a greater transportation capacity, a higher fab ceiling height might be needed. This point is often ignored even by experienced architects, who are used to designing a single-layer ceiling height for a fab.
We believe that a large-scale fab equipped with only a single-layer transportation system may reduce the fab throughput. We can overcome this deficiency by installing a two- or three-layer transportation system, which in turn requires a higher ceiling height. To justify this proposition, we have developed a queuing network model to evaluate the performance of a fab. This queuing network is adapted from Connors et al. (1996) by additionally considering the transportation facilities as finite-capacity resources. Numerical experiments support our proposition.
One extension of this research would be to examine the optimal scale of a semiconductor fab. The larger the fab, the better its tool capacity utilisation, but the higher are its transportation installation costs as well as the operational cost of clean room space due to the requirement of a higher fab ceiling height.
Acknowledgement
This study was supported financially by the National Science Council, Taiwan, under research contract NSC96-2628-E-009-026-MY3.
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