CHAPTER 2
THE DESIGN OF ACTIVE POLYPHASE FILTER
2.1 INTRODUCTION
The fast growth of wireless applications in recent years has driven intense efforts to design highly integrated, high-performance, low-cost RFICs. Both low-IF [33]-[37]
and double-quadrature [38]-[40] architectures have been adopted as promising receiver topologies to realize these design goals because they combine the advantages of heterodyne and direct-conversion architectures. In the low-IF receiver, the RF signal is amplified and downconverted to a low IF signal in a single step through the quadrature demodulator. After downconversion, polyphase filters [41][42] must be used to filter image signals at the intermediate frequency for both I and Q channels.
To avoid the signal-to-noise ratio (SNR) degradation by image interferences, a polyphase filter should provide high selectivity between the desired and image signals.
Moreover, the power consumption must be low to prolong the lifetime of the batteries for use in portable wireless communications systems. Polyphase filters in some current standard applications require wide bandwidths. For example, a 20MHz channel bandwidth is required for IEEE 802.11a wireless LAN [7] and HIPERLAN2 [8]. Accordingly, the design of high-performance, wideband, and low-power on-chip polyphase filters for these applications are critically needed.
So far, many polyphase filters have been proposed [43]-[47]; they can be divided into two types, namely passive RC polyphase filters and active polyphase filters.
Passive RC polyphase networks are used in passive RC polyphase filters[43][44]. The voltage transfer function of the RC polyphase networks depends on the phase order of the input sequence; it can distinguish between signals with positive frequencies and those with negative frequencies. The passive RC polyphase filter can exhibit a high image rejection ratio (IRR), but has a limited range of operating frequencies. The desirable filtering function can only be obtained in the narrow band around the pole frequency, which depends on the RC time constant. To increase the bandwidth, a multi-stage network is proposed to achieve the broadband response [48].
The expense of the multi-stage passive polyphase filter is that it is lossy, so its output signal decays. Additional buffers should be inserted among the stages to compensate the loss. However, these buffers significantly increase the power consumption because the input impedance of each one-stage passive RC polyphase filter is low. More power is consumed as more stages are used to increase the bandwidth. Furthermore, the variation of resistances and capacitances should be kept within a desired small range to achieve a high IRR. This means large chip area is required because the variations of adjacent on-chip resistances and capacitances are inversely proportional to their surface area [49]. As the area of resistors increases, it also increases the parasitic capacitance and lowers the cut-off frequencies of resistors.
Thus, a critical trade-off must be made among IRR, chip area and maximum operational frequency of passive RC polyphase filters.
Active polyphase filters have the general advantages of low power dissipation, small chip area and high signal gain. All the active polyphase filters proposed so far
[45]-[47] have operating frequencies in the range of several hundreds of KHz to several of MHz. The polyphase filter in [45] provides a good image rejection ratio at 250kHz by using op-amp circuits. In [46], the active gm-c polyphase filter provides a -53dB of image rejection ratio at 3MHz without tuning circuits by using a well-controlled special analog process. In [47], the gm-c polyphase filter with CMFB (common-mode feedback) and CMFF (common-mode feed forward) circuits and frequency-tuning circuits, can achieve more than -45dB of IRR in a bandwidth of 1MHz with a central frequency of 2MHz.
In this chapter, a new broadband CMOS active polyphase filter with a wide range of operating frequencies is proposed and designed by using the basic polyphase filter architecture, which is used to implement passive RC polyphase filter. A constant-gm bias circuit [50] is used to decrease the sensitivities of the filter gain and the bandwidth to temperature and process variations. Additionally, the multi-stage approach is also applied to achieve the wide bandwidth. Due to the high input impedance in each stage, the proposed active polyphase filter can avoid the degradation of gain between pairs of stages when connected in cascade. Thus, power-consuming buffers are not required. Using 0.25µm CMOS 1P5M technology, the proposed four-stage active polyphase phase filter can achieve an IRR of -48dB in the 6.1MHz ~ 30MHz band. The filter consumes 11mW (5.5mW) with a power supply of 2.5V (1V). A higher IRR can be achieved by increasing the number of cascaded stages although the achievable IRR is limited by matching.
The model for the new active polyphase filter is presented in Section 2.2. Section 2.3 describes the circuit design methodology. HSPICE simulation results verify the functions of the circuits. Section 2.4 presents experimental results. Finally, Section 2.5
draws conclusions.
2.2 MODEL FOR THE ACTIVE POLYPHASE FILTER
The polyphase filter is a complex filter because its frequency response is not symmetrical around dc. The transfer function H(s) of a complex filter can be represented as
) ( )
( )
(s H1 s jH2 s
H = + (2.1)
where H1(s) and H2(s) are the real and imaginary parts of the complex transfer function. If a complex signal Ci(s)=Ii(s)+jQi(s) is applied to this complex filter, the output signal Co(s) can be written as
) ( )
( ) ( ) ( )
(s C s H s I s jQ s
Co = i = o + o (2.2)
) ( ) ( - ) ( ) ( )
(s I s H1 s Q s H2 s
Io = i i (2.3)
) ( ) ( ) ( ) ( )
(s I s H2 s Q s H1 s
Qo = i + i (2.4)
where Io(s) and Qo(s) are the real and imaginary parts of Co(s), respectively. If Co(s) can be generated by a circuit from the input complex signal Ci(s) according to (2.3) and (2.4), then the complex transfer function H(s) can be realized by this circuit. Fig.
2.1 shows the signal flowgraph for the realization of H(s) by using (2.3) and (2.4). In this way, any complex filter can be realized by a combination of the real and imaginary parts of its transfer functions.
The transfer function H(s) of the one-stage RC network can be used to implement a polyphase filter, according to the approach presented above. The resultant transfer function H(s) is represented as
P P
P
s j As s
s A jH s H s
H ω ω
ω + +
= + +
= ( ) ( )
)
( 1 2 (2.5)
where A and ωP are the gain and pole frequency, respectively, of the first-order low-pass filter H1(s) and the high-pass filter H2(s). The combination of H1(s) and H2(s) forms a block denoted as the Low-High-Pass filter (LHF) in Fig. 2.1. According to (2.5), the transfer curves of |H(jω)| and |H(-jω)| versus frequency for A=1 and ωP=10MHz are shown in Fig. 2.2 in solid lines. Notably, the desired signal with negative frequency falls in the filter’s passband while the image signal at positive frequency is attenuated. |H(jω)| is lowest at ω=ωP where ωP is also called the rejected frequency. Using the equation in (2.5), the image rejection ratio IRRPPF of the polyphase filter defined as the ratio of the magnitude in the attenuation band to that in the passband, can be derived as
ω ω
ω ω ω ω ω
= +
−
=
= =
p p
PPF H s j
j s
IRR H -
) (
) ) (
( (2.6)
As may be seen from (2.6), the IRRPPF can be zero at frequency ωP if the gains and pole frequencies of H1(s) and H2(s) are perfectly matched.
Considering the gains and pole frequencies mismatches between H1(s) and H2(s), the transfer function (2.5) can be rewritten as
) 2 1
(
) 2 1 ( )
2 1
(
) 2 1
)(
2 1 ) (
(
P P P
P P P
P P P
s
s A A j A
s
A A s A
H ω ω ω ω ω ω
ω ω ω
∆ + +
∆ + +
∆
− +
∆
−
∆
= − (2.7)
where ∆A and ∆ωP are the mismatch quantities of A and ωP, respectively. The simulated |H(jω)| and |H(-jω)| versus frequency with 20% variations are shown by the dashed lines in Fig. 2.2. It is shown that the transfer curves of H(s=jω) and H(s=-jω) are shifted to the opposite directions and the resulting IRRPPF at ω=ωP is degraded.
Using (2.7) and neglecting high-order terms, the image rejection ratio IRRPPF with
mismatch effects can be derived as
4 2
2 4 2 2 2 2 2
2 2 2
2 2 2 2 2 2 2
1
4 2
2 4 2 2 2 2 2 2
( )
{[64 ( ) 64 ( ) 64 ( )( )
16 ( )( ) ( ) 32 ( )( ) ]
/[64 ( ) 64 ( ) 64 ( )( ) ]}
PPF
P
P P P P
P
P
P P P P P
P
P
P P P P
P
IRR
A A A A
A
A A A
A
A A A A
A
P
P
ω
ω ω ωω ω ω ω ω ω ω ω
ω
ω ω ω ω ω ω ω ωω ω
ω
ω ω ωω ω ω ω ω ω ω ω
ω
≅
∆ ∆
− + − + + −
∆ ∆
+ + + + − +
∆ ∆
− − + + + +
(2.8) Fig. 2.3 depicts the exact IRRPPF(ω=ωp) with the corresponding mismatches ∆ωP/ωP
and ∆A/A, where the numbers on the curves denote the IRRPPF values in dB. The figure demonstrates that if |∆A/A|>12% or |∆ω/ωP|>5%, then the IRRPPF at ω=ωP is degraded to -30dB. Therefore, the gains and locations of the pole frequencies in H1(s) and H2(s) should be kept highly consistent to achieve the desired image rejection performance.
A broadband polyphase filter can be realized by cascading several stages of one-stage polyphase filter. The resultant image rejection ratio IRRPPFN of the N-stage polyphase filter can be derived by multiplying all IRRPPF values of the constituent one-stage polyphase filters as
, 1
( ) ( )
N
PPFN PPF n
n
IRR ω IRR ω
=
=
∏
(2.9)where IRRPPF,n is the IRRPPF of the nth-stage polyphase filter. Ideally, the image rejection ratio can be improved with a cascaded multistage structure, as indicated by (2.9). Note that the range of operating frequencies can also be expanded by assigning a different value of ωP to each one-stage polyphase filter. To provide the sufficient IRRPPF, the adequate number of stages should be determined. According to [48], the required stage can be shown in Fig. 2.4, where the ωmax and ωmin means the upper and
lower bounds of the rejection band, respectively. As seen from Fig. 2.4, at least four stages are required to achieve –50dB of IRRPPF within the band of 5MHz~25MHz.
2.3 CIRCUIT DESIGNS
2.3.1 The Circuit Design of Wideband Active Polyphase Filter
The proposed polyphase filter structure in Fig. 2.1 consists of a low-pass filter H1(s) and a high-pass filter H2(s) in each of the two LHF blocks. The CMOS realization of a LHF block is shown in Fig. 2.5(a) where the functions of H1(s) and H2(s) are combined. In Fig. 2.5(a), the NMOS device M1 converts the input voltage VI
to current i1 and then the current is mirrored to i3 and i4 by the PMOS current mirrors M2, M3, and M4. The diode-connected transistor ML and the capacitor CH then divide the mirrored current i3 into iL and iH, respectively. The currents iL and iH can be derived as
) (
)
1(
H L
H L I
L s gm C
C gm V gm
i = + (2.10)
) (
1 H L I
H s gm C
s V gm
i = + (2.11)
where gm1 and gmL are transconductances of M1 and ML, respectively. Using the mirrored currents iL and iH, the required low-pass and high-pass transfer functions H1(s) and H2(s) can be realized as
) (
) (
) 1 1 (
) 1
( 7 1
7 7
1
H L
H L L
L L OL
I OL
C gm s
C gm gm K gm
i gm K gm i
V s V
H = = = = + (2.12)
) (
) 1 1 (
) 1 (
) 1 (
) 1 ( )
(
1 8 8
3 8 5
4 8 8
2
H L H
H H
L H H OH
I OH
C gm s
s gm K gm
i gm K
i K i gm K i
gm i gm i
V s V H
− +
=
−
=
−
−
=
−
−
=
=
=
(2.13) where KL is the current ratio of M6 and ML, KH is the current ratio of M4 (M5) and M3
(ML), and gm7 (gm8) is the transconductance of M7 (M8). The capacitor CC connected between node A and VOH is used to pass the ac current iOH = i4-i5, but block the dc voltage. The rejected frequency ωP can be adjusted by changing CH since the poles of both transfer functions H1(s) and H2(s) are determined by ωP = gmL/CH.
The parasitic effects of the LHF circuit in Fig. 2.5(a) are analyzed. The parasitic capacitance CP at node A has the largest value as compared to those at other nodes, because CP consists of the parasitic capacitance of CC and the device capacitance of M4 and M5. With CP at node A, the transfer function of H2(s) can be derived as
⎥⎥
⎥⎥
⎦
⎤
⎢⎢
⎢⎢
⎣
⎡ + +
⎥⎦
⎢ ⎤
⎣
⎡
− +
=
P C
P C
P H
L H
C C
C C s gm
C gm C
gm s
s gm K gm
s
H ( ) ( )
) 1 ) (
(
8 8 1
8
2 (2.14)
As (2.14) shows, the second pole at ωP2 = gm8(CC+CP)/CCCP is generated. Since ωP2
may affect the magnitude and phase of H2(s) and thus degrade the IRR of the polyphase filter, ωP2 should be kept at least ten times larger than ωP to minimize the degradation of IRR.
Based on the structure illustrated in Fig. 2.1, a one-stage polyphase filter H(s) with a differential structure can be realized by the combination of LHF circuits. In general, the mixers used in the receiver are designed in differential circuits to cancel the LO-to-IF feedthrough [51]-[56]. Thus the proposed polyphase filter is designed in differential type to process the differential output signals from the mixers. Fig. 2.5(b)
shows the differential LHF, LHFD. The LHFD consists of two LHFs with a common current source device Mb, which is used to provide the bias current of LHF and reject the input common mode signal. Fig. 2.5(c) shows the complete circuit of one-stage polyphase filter, based on the structure in Fig. 2.1. The output node L (L ) of LHFDI is connected to the output node H (H) of LHFDQ to realize the subtraction function in Fig. 2.1, whereas the summation function in Fig. 2.1 is realized by connecting the output node H ( H) of LHFDI to the output node L (L) of LHFDQ. Finally, the output currents are converted to voltages by connecting them to diode-connected transistors M7, M7 , M8 and M8 . Fig. 2.5(c) realizes the signal flowgraph of Fig. 2.1 in differential structure.
According to (2.12) and (2.13), both the gains and the poles of the transfer functions H1(s) and H2(s) are dependant on transconductances of transistors.
Therefore, transconductances are important parameters and must be stabilized. The stability of gm is achieved by using a constant-gm bias circuit, as shown in Fig. 2.6.
In the bias circuit, MB1~MB6 are bias transistors and MB7~MB9 works to start-up. The transconductance of MB1 is
( ) ( )
1 2 1 1 2
B B B B
gm = ⎡⎣ − W L W L ⎤⎦ R (2.15)
where (W/L)B1 and (W/L)B2 are geometric ratios of MB1 and MB2, respectively. The transconductance of MB1 is determined by geometric ratios, independent of process parameters and temperature. Besides, not only is gmB1 stabilized, but all other transconductances are also stabilized since all transistor currents are derived from the same biasing network. Therefore, the transconductances of other transistors are mainly dependent on geometry.
As seen from (2.7) and (2.8), the IRRPPF(ω=ωP) is degraded if the gain and pole frequencies of H1(s) and H2(s) are not identical. Since the pole frequencies of H1(s) and H2(s) shown in (2.12) and (2.13) are identically determined by gmL and CH, the pole frequencies mismatch can be avoided. The gain mismatch between |H1(s=ωP)|
and |H2(s=ωP)| can be reduced to the balance between KL/gm7 and KH/gm8. KL and KH
are current ratios and the mismatch can be kept small. To reduce the mismatch of gm7 and gm8, the layout of M7 and M8 can be put in common centroid. Moreover, minimum channel length is not used in this design to further reduce the gain mismatch.
In the passive RC polyphase filter, the gain mismatch depends on not only the matching in RC values and transconductances of buffers in I/Q paths, but also parasitic capacitors of resisters. In comparison with the mismatch effects of current ratio and tansconductance in the proposed active polyphase filter, the IRRPPF won’t be worse than the one in passive RC polyphase filter.
A broadband multi-stage polyphase filter can be realized by cascading several stages of one-stage polyphase filters. Unlike the passive RC polyphase filter, cascading the proposed active polyphase filters can avoid the degradation of gain among stages because the input impedance in each stage is high. In each stage, CH
should be adjusted to obtain different reject frequencies. All other circuits in Fig. 2.5(c) remain unchanged, greatly reducing the complexity of the design of a multi-stage polyphase filter.
The proposed wide bandwidth polyphase filter, which targets at an image rejection ratio of -50dB within 5MHz~25MHz is realized in 0.25-um 1P5M CMOS technology with a power supply of 2.5V. According to the result shown in Fig. 2.4, four one-stage polyphase filters are cascaded in this design. Four poles are placed
equally on the logarithmic frequency axis and fine-tuned by simulations to achieve the equal ripple [48]. The equal ripple characteristic can achieve not only the highest IRRPPF4 but relax the IRRPPF4 degradation caused by mismatches between stages. The capacitors CH in the four one-stage polyphase filters are 3.5pF, 5.5pF, 10pF and 16pF, respectively. The resultant rejected frequencies are 24.5MHz, 15.5MHz, 8.5MHz and 5.4MHz, respectively.
2.3.2 The Simulation Results of Active Polyphase Filter
With the parameters shown in Table 2.1 (CH=3.5pF), the simulated transfer curve at positive and negative frequencies and the image rejection ratio IRRPPF of the one-stage CMOS polyphase filter (ωP=24.5MHz) are shown in Fig. 2.7. As seen from Fig. 2.7, the IRRPPF of –51dB at the rejected frequency and 2dB voltage gain can be achieved.
The effects of process and temperature variations in the one-stage CMOS polyphase filter that incorporates the constant-gm bias circuit are verified, HSPICE simulation shows that the transconductance variations of M1 in Fig. 2.6 can be kept within 2.3% and 2% with the four corners (FF, FS, SF, and SS) of device model parameters and variations in the temperature between 0o and 80o, respectively. Fig. 2.8 and Fig. 2.9 show the simulated transfer curve and IRRPPF with process and temperature variations. As seen from Fig. 2.8 and Fig. 2.9, the variations of rejected frequency can be kept within 8% and 5%, respectively. Accordingly, the desired IRRPPF can be achieved under process and temperature variations.
With the random variations among components, the one-stage polyphase filter (ωP=25MHz) biased with a constant-gm circuit is verified by 30-times of Monte Carlo
simulations. All device dimensions are the same as the values listed in Table 2.1. The variations of transistor parameters ∆W (channel width), ∆L (channel length) and
∆Vth(p,n) (threshold voltage) are randomly distributed according to the values provided by the corner parameters of the MOS device model, such that ∆W=±0.03um,
∆L=±0.02um, ∆Vthp= ±0.06V, and ∆Vthn=±0.05V. The relative variations of capacitance resistance are 10%. The results of the simulation show that the worst IRRPPF at 24.5MHz still exceeds -32dB and the variations of rejected frequency can be kept within 5.3%.
A wide bandwidth polyphase filter with four cascaded one-stage polyphase filters is realized. Fig. 2.10 plots the simulated transfer curves at positive and negative frequencies and the image rejection ratio IRRPPF4 of the designed four-stage polyphase filter. It is shown that the IRRPPF4 can exceed -50dB by the four-stage polyphase filter over the bandwidth 4.5MHz~27.5MHz. The voltage gain at 20MHz is 7dB. The total power consumption is 11mW at a power supply of 2.5V.
HSPICE simulations are performed to verify the effects of process and temperature variations. The results in Fig. 2.11 show that the IRRPPF4 exceeds -50dB over the range of 5MHz~26.5MHz under the four corners of the MOS device models.
As the temperature varies from 0o to 80o, Fig. 2.12 shows that an IRRPPF4 of -50dB can also be achieved within 4.75MHz to 27MHz. Thus, the performance of the proposed wide bandwidth polyphase filter can be well controlled as the process and temperature are varied.
In the multistage polyphase filter, the gain divided between stages will lead to different noise and linearity performances. Table 2.2 lists the simulated noise figure
(NF) and IIP3 characteristics of the four-stage polyphase filter where the 8dB total gain are divided between four stages in different conditions. As seen in Table 2.2, a larger gain assigned in the preceding stage results in a better noise figure and a worse IIP3. On the contrary, a larger gain assigned in the back stage leads to a better IIP3 but worse noise figure. Thus, the gain can be assigned flexible between stages for different noise and linearity requirements.
The proposed active polyphase filter can be modified for Bluetooth applications.
The Bluetooth standard specifies the operation channel bandwidth is 1MHz and group delay smaller than 6µs is required [47]. Since the channel bandwidth is narrow compared to the requirement in IEEE 802.11a, the intermediated frequency can be chosen as low as several MHz to relax the design complexity in IF stages. In the modified polyphase filter, the operational frequency is chosen from 3 to 4 MHz and two stages are needed by the relation shown in Fig. 2.4. The simulation shows if the poles of the two-stage polyphase filter are 3.1 and 3.8 MHz, 50dB of IRR and 55ns of the group delay can be achieved within the passband.
2.3.3 Layout Consideration
Layout is an important step in designing the polyphase filter. Since the gains and pole frequencies in H1(s) and H2(s) should be kept highly consistent to achieve a high IRRPPF, layout of corresponding components should be kept symmetrical carefully.
Fig. 2.13 shows the floor planning of the one-stage polyphase filter. The solid-line and dashed-line blocks represent the transistors in positive and negative paths, respectively. The transistors in I (Q) path are separated to two parts I1, I2 (Q1, Q2).
As seen from Fig. 2.13, the transistors are placed symmetry for not only differential
paths but also I/Q paths. To reduce the process variation, dummy gates and dummy capacitors are added beside the edge-transistors and edge-capacitors. Besides, a piece of ground metal is inserted between the I and Q routing metals for shielding off the mutual interference.
2.3.4 The Circuit Design of 1-V Wideband Active Polyphase Filter
With the advantage of currents operation, the proposed active polyphase filters can be modified to operate at a low supplied voltage. Fig. 2.14 shows the low-voltage version of LHF where the transistor M2 is connected in a folded structure. Therefore, the required power supply can be as low as the threshold voltage Vth2 of M2 plus the drain-source voltage VDSb2 of Mb2. Mb2 works as a current source, which provides a constant dc current to M1. Because the high impedance at the drain of Mb2, the current i1, which is generated from the input voltage signal VI by M1, flows to M2 and then mirrored to i3. The functions of other transistors are similar to those of the corresponding transistors in Fig. 2.5(a). With a supplied voltage of 1V and 0.25um 1P5M CMOS technology, the transfer curves and the IRRPPF4 of a low-voltage four-stage polyphase filter are shown in Fig. 2.15. Fig. 2.15 shows that an IRRPPF4 of -50dB can be achieved within the frequency range 4.9MHz ~ 27MHz. The simulated CMRR within this bandwidth is 40dB. The 1V polyphase filter consumes 5.5mW, which is only about 50% of the power consumption in the 2.5V version.
2.4 EXPERIMENTAL RESULTS
Fig. 2.16 shows the die micrograph of a four-stage polyphase filter, which is designed and fabricated in 0.25-um 1P5M CMOS technology. The four-stage polyphase filter consumes 11mW at a supplied voltage of 2.5V and occupies a die
area of 1162×813µm2. All of the capacitors are implemented by metal-insulator-metal (MIM) capacitors.
For measurement purposes, on-chip test buffers are placed after the polyphase filter to analyze the output signals. In the measurement set-up, a splitter converts a single-ended signal into differential signals, which are then sent to a six-stage off-chip RC polyphase filter to generate the required input quadrature signals. The off-chip RC network can provide an IRR of more than -55dB in the frequency range 4MHz~35MHz. After the gain loss of the off-chip RC network has been compensated for, the measured voltage gain of the fabricated four-stage polyphase filter at 20MHz is 6.6dB. The measured IRRPPF4 is shown in Fig. 2.17, an image rejection ratio of -48dB can be achieved in the frequency range 6.1MHz~30MHz. Fig. 2.18 shows the measured quadrature output signals when 20-MHz differential signals are applied. A two-tone test is performed to measure SFDR [57]. As shown in Fig. 2.19, when the input signals are at 19.5MHz and 20.5MHz, the differences between noise floor to fundamental and third-order intermodulation signals are 72.2dB and 21.5dB, respectively. Thus, a 65dB in-band SFDR can be achieved by the polyphase filter. Fig.
2.20 shows that the measured input third intercept point (IIP3) is 8dBm.
The simulation and measured results of the CMOS four-stage polyphase filter are listed in Table 2.3. The performance comparisons between the recently proposed polyphase filters are given in Table 2.4. In comparison to the passive RC polyphase filter [43], the proposed four-stage active polyphase filter has much lower average power dissipation per stage for the same power supply and higher passband gain while maintaining the same image rejection ratio per stage. In addition, the proposed polyphase filter can achieve a wider band than other active polyphase filter
[45][46][47].
2.5 SUMMARY
A wideband and low-power active polyphase filter has been proposed and analyzed. The wideband performance is achieved by simple CMOS single-stage filter circuit and directly cascaded multistage structure. Without inter-stage buffer, the power dissipation is kept low. The simulations have shown that by biasing with a constant-gm circuit, the variations in process and temperature are effectively reduced.
Due to the advantage of current-mode operation, the proposed active polyphase filter has been successfully modified to fit the operation of 1V power supply. The performances of the filter have been verified through measurement on the fabricated chip in 0.25-um 1P5M CMOS technology. The measured image rejection ratio of four-stage polyphase filter is higher than -48dB over the frequency range of 6.1MHz~30MHz. The power consumption is 11mW with 2.5V power supply. It has been shown from measurement results that the proposed active polyphase filter is suitable in wireless communication applications.
Table 2.1
Dimensions of Devices in Constant-Gm Bias Circuit and Polyphase Filter.
Constant-gm bias circuit
M1 (4um/1um)
M2 (4um/1um) • 4
M3 (1um/1um)
M4 (1um/2um)
M5 (8um/1um)
M6 (8um/1um)
M7 (4um/1um)
M8 (0.5um/20um)
M9 (1um/1um)
Rb 6kΩ
Active Polyphase filter
M1 (0.5um/0.5um) • 4 M2 (2.5um/0.5um) • 4 M3 (2.5um/0.5um) • 8 M4 (2.5um/0.5um) • 4 M5 (0.5um/0.5um) • 4 M6 (0.5um/0.5um) • 4 M7, M8 (2.5um/0.6um) • 4
Mb (5um/1um) • 4
ML (2.5um/0.5um) • 8
CH 4 stages: 3.5pF, 5.5pF, 10pF, 16pF
CC CH/2
Table 2.2
Simulated NF and IIP3 Characteristics of Different Gain Distributions in the Four-Stage Active Polyphase Filter.
Av (dB) Stage 1
Av (dB) Stage 2
Av (dB) Stage 3
Av (dB) Stage 4
NF (dB)
@ 20MHz IIP3 (dBm)
A 4 2 2 0 37.5 5
B 2 2 2 2 38.8 9.4
C 0 2 2 4 40.2 11.6
Table 2.3
Measured Characteristics of the Active Polyphase Filter.
Parameter Simulation Result Measured Result Fabrication process 0.25-um 1P5M CMOS technology
Power supply 2.5V
Power Dissipation 10.72mW 11mW
Bandwidth 5~25MHz 6.1~30MHz IRR -50dB -48dB
Gain @ 20MHz 7dB 6.6dB
Linearity 8.7dBm 8dBm
SFDR - 65dB CMRR 40dB 41dB
Area 1162×813µm2
Table 2.4
Comparison Between the Recently Proposed Polyphase Filter.
This Work [43] [45] [46] [47]
Type Active Passive Active RC Gm-C Gm-C
Number of stage 4 5 5 order
Butterworth
5 order Butterworth
6 order Butterworth
Power supply 2.5V 3.3V 5V 2.3V 2.7V
Center Frequency 18MHz 12.5MHz 250KHz 3MHz 2MHz
Bandwidth 23.9MHz 16.5MHz 220KHz 1MHz 1MHz
Total power
dissipation 11mW 62.7mW 90mW 7.36mW 12.69mW
Average power dissipation per stage
for 2.5V
2.75mW 9.5mW 9mW 1.6mW 3.92mW
Total IRR -48dB -60dB -64dB -53dB -45dB
Average image rejection ratio per
stage
-12dB -12dB -12.8dB -10.6dB -7.5dB
Passband gain 6.6dB -1dB 12dB 0dB 15dB
SFDR 65dB - - 52dB 45.2dB
Technology 0.25µm 0.6µm 1.2µm 0.35µm 0.35µm
Fig. 2.1 Signal flowgraph for realizing a single-stage complex filter.
Fig. 2.2 Transfer curves of |H(s)| versus frequency.
Fig. 2.3 Simulated IRRPPF values (indicated on the curves) of one-stage polyphase filter at ω=ωp with gain and pole frequency variations.
Fig. 2.4 Required stage versus achievable IRRPPFN within the rejection band.
(a)
(b)
(c)
Fig. 2.5 (a) Circuit of LHF. (b) Differential type of LHF and its equivalent functionality block LHFD. (c) Block diagram of H(s).
Fig. 2.6 Circuit of constant-gm bias.
Fig. 2.7 HSPICE simulated transfer curve and IRRPPF of the one-stage CMOS polyphase filter (ωP=24.5MHz).
Fig. 2.8 HSPICE simulated IRR variations of the one-stage CMOS polyphase filter with four corners (FF, FS, SF, and SS) of MOS device models.
Fig. 2.9 HSPICE simulated IRR variations of the one-stage CMOS polyphase filter in the temperature between 0o and 80o.
Fig. 2.10 HSPICE simulated transfer curve and IRRPPF4 of the four-stage CMOS polyphase filter.
Fig. 2.11 HSPICE simulated IRR variations of the four-stage CMOS polyphase filter with four corners (FF, FS, SF, and SS) of MOS device models.
Fig. 2.12 HSPICE simulated IRR variations of the four-stage CMOS polyphase filter in the temperature between 0o and 80o.
Fig. 2.13 Floor planning of the one-stage polyphase filter.
Fig. 2.14 Low-voltage version of LHF.
Fig. 2.15 HSPICE simulated transfer curve and IRRPPF4 of the low-voltage four-stage CMOS polyphase filter.
Fig. 2.16 Die micrograph of fabricated four-stage polyphase filter in 0.25-µm CMOS technology.
Fig. 2.17 Measured IRRPPF4 of fabricated four-stage polyphase filter in 0.25-µm CMOS technology.
Fig. 2.18 Measured quadrature output signals when 20-MHz differential signals are applied.
Fig. 2.19 Two-tone test for f1 = 19.5MHz and f2 = 20.5MHz.
Fig. 2.20 Measured IIP3 of fabricated four-stage polyphase filter in 0.25-µm CMOS
technology.
