Table 3.1 Summary of result of condition 1 and condition 2………...49 Table 3.2 Comparison of chemical REZI-38 and EKC 6800………...53 Table 3.3 Comparison of batch type spray tool chemical………56
Chapter 4 :
Table 4.1 Defect analysis for chemical dependency on crown wet particles...65 Table 4.2 Defect analysis for chemical process time dependency on crown wet particles………70 Table 4.3 Defect analysis for IPA process time dependency on crown wet
particles………71 Table 4.4 Chemical rotation speed dependency on crown capacitor particle
defects………..76 Table 4.5 Metallic reduction by Hydroxylamine……….83 Table 4.6 Final optimal condition for crown capacitor clean………..93
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Graph Captions
Chapter 3:
Graph 3.1 Analysis of defect counts for condition 1 and condition 2…………...50
Chapter 4:
Graph 4.1 Defect analysis for chemical dependency on crown capacitor particles………66 Graph 4.2 Defect analysis for chemical process time dependency on crown
capacitor particles……….72 Graph 4.3 Defect analysis for IPA process time dependency on crown capacitor particles………72 Graph 4.4 Chemical rotation speed dependency on crown capacitor particles….77
Chapter 1: Introduction
1.1 DRAM capacitor
A typical dynamic random access memory (DRAM) cell consists of an access transistor and a storage capacitor (1T/1C). There are two types of storage capacitors, stacked-capacitors and trench capacitors, of which the latter offers highest density, at the expense of process complexity [1]. In 1977, M.Koyanagi fabricated the first DRAM test chip with a stacked capacitor cell using 3 µ m NMOS technology [2].
Then, a stacked capacitor cell was employed in a 1Mbit DRAM production for the first time by Fujitsu [3]. Hitachi also employed a stacked capacitor cell in 4Mbit DRAM production [4]. Many other DRAM companies used a trench capacitor cell in
the early stage of 4Mbit DRAM production. However, the stacked capacitor cell, which eventually came to occupy a major position in 4Mbit to 4Gbit DRAM’s, has
evolved by introducing the three-dimensional capacitor structures with a fin-type electrode [5] and a cylindrical electrode . As the design rule of DRAM shrinks down below 100nm, the novel MIM capacitor processes are inevitable [6].
To achieve sufficient memory cell capacitance in a limited area, a crown wet process
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is designed to gain more effective capacitor area by using etch rate selectivity of wet etchant. (Figure 1.1) A brief fabrication process procedure for a capacitor over bitline (COB) is proposed. After the transfer gate transistor formation, W/WN bit line is defined before storage capacitor formation. Silicon nitride and thick CVD PSG / BPSG are deposited according to the required storage node height. Then, the storage node region which is packed with minimum space is defined by PSG/BPSG etching.
Subsequently, TiN film which is used for the storage node is deposited with a CVD tool. The gap of the cup-shaped capacitor is then filled by PSG. Next, CMP polishes the wafer structure until the silicon nitride end point is detected. Then, another patterning process is undergone to etch off the supporting silicon nitride. Finally, the whole wafer will be treated under a 49% HF portion, due to the high etch rate selectivity of SiN to BPSG/PSG and SiN film, all of the BPSG and PSG will be removed completely, while the SiN remains to support the cylinder. Now, a so-called crown shaped stacked capacitor with sufficient cell capacitance is formed. The feature of the crown shaped stacked capacitor structure is that both in- and out-sides of the storage node are used as cell capacitors.
However, after the crown wet capacitor formation, particulate defects which prove to be a yield killer are found all over the process wafer. The cleaning method after the
crown shaped stacked capacitor formation will now be discussed.
Figure 1.1 Fabrication procedure of crown stacked capacitor.
1.2 Wet cleaning process
In general, compared with other industrial products, the yield of VLSI is conspicuously low. Among the causes of failure in mass-produced devices, random structural defects caused by particle adhesion onto the wafer or reticle occupy an extremely large proportion, and have become the single largest cause of yield reduction [7]. Furthermore, along with the increment of memory integration levels, the failure of pattern defects caused by particles increased most markedly.
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Across the range of manufacturing techniques, maintaining wafer cleanliness has become the crucial issue for improving yield and reliability. Every wafer-processing step is a potential source of contamination, not only from particles but also from a variety of other contaminants. In order to remove these contaminants, cleaning steps appear repetitively within the semiconductor process flow, occupying 30~40% of all the process steps. As the advanced semiconductor device technology progresses from the half-micron era to the quarter-micron era and beyond, the severity of demands for cleanliness will continue to increase [7].
Cleaning process is required to achieve (i) ultraclean surface, (ii) without any adverse side effects, (iii) within a short period of time, (iv) with high reproducibility, (v) at low cost. The requirement by the industry is becoming more severe along with further integration of ULSI [8]. Cleaning technology, therefore, must be innovated to meet the ever-increasing requirements.
The high-performance and multi-performance features needed for this generation of cleaning are: controllable selectivity, multi-functionality, adaptability to high aspect ratios and finer structures, efficient cleaning for high density particles and reduction of cleaning costs and of the number of cleaning process steps. A variety of wet
cleaning processes are performed to remove metallic ions and particles. The current ULSI wet-cleaning technology is based on the so-called RCA cleaning published by Kern and Puotinen of RCA, Inc. in 1970 [9]. Table 1.1 shows a process flow of a typical current ULSI wet-cleaning based on the RCA cleaning [10]. It also shows characteristics of each cleaning solution.
These cleaning steps use ultrahigh-purity chemicals and ultra pure water in which metallic contaminant is reduced to the ppt order or less. H2O2 used in SPM (H2SO4 / H2O2), HPM (HCl / H2O2 / H2O), and APM (NH4OH / H2O2 / H2O) is a strong oxidizing agent. H2O2 oxidizes and decomposes contaminants to raise the removal efficiency, and oxidizes the top surface of Si substrate to form a passivation (SiO2) film at thickness around 1 nm. HCl, a typical strong acid, dissolved oxidized metal (oxides, hydroxides, and ions). H2SO4 decomposes organic contaminant and HF dissolves SiO2, whereas these two acids can also dissolve oxidized metals. NH4OH, the only alkali component, not only dissolves organic contaminants but also removes insoluble particle [10].
However, these chemicals cannot be applied to metal surfaces as it uses H2O2, strong acids, and strong alkali which corrode metal materials such as Al, W, Cu and Ti.
6
Although organic solvent or ultrapure water can be used for post-metallization cleaning, their cleaning performance is not sufficient. Reduction of pattern size which leads to higher aspect ratio is important in DRAM device, in addition, it becomes increasingly important to improve the cleaning performance [11].
Table 1.1 Typical cleaning solutions used in the semiconductor manufacturing process [10]. Removal of organic contaminations &
metallic ions
Removal of native oxide film and metallic ions
1.3 Objectives
This thesis will focus on the study of metal surface cleaning method for post-crown-wet- stacked capacitor in the 6F2 60 nm DRAM technology. The objective of this work is first to study how to get a defect and particles free wafer after the HF dip crown wet process (as mentioned in section 1.1, procedure 6) , in order to gain more yield for a 60 nm DRAM in 300mm wafer. In other words, this thesis focuses on unraveling the key process of particle generation, and the most efficient way to
remove them. Then, a model will be setup which takes into account the physical and chemical wet cleaning mechanism. The principles behind the model will be then discussed. The procedure to derive defects and particles with 300mm defect inspection tool of Applied Material (AMAT) Complus 3T is demonstrated.
1.4 Organization of the thesis and methods
The focal point of this work is to find the ideal way to remove crown capacitor particles after wet etch treatment. All specimen used were 300mm DRAM wafers, with capacitor structures (which also known as storage node) height of 1.7um, critical dimension (CD) 0.091 um, and an aspect ratio of 18.7. In Chapter 2, an overview of wafer contamination, including defect and particles sources analysis will be presented.
Then, the process variable of this study which will involve different kind of chemicals and tool will be introduced in Chapter 3. The investigated processing steps include:
the removal of BPSG and PSG in HF solution (Crown Capacitor Wet Etch) and the follow up cleaning and polymer residue removal process. They are common processing steps in the DRAM fabrication facility used for this study. In Chapter 4, the experimental design and results will be discussed. To analyze defect sources, measurements before and after the processing step are conducted. The observation of the change in particle and defect counts due to different experimental parameters will
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be discussed which leads to a better understanding of the impact of each parameter on particle removal. The thesis ends with a general conclusion of the research described together with suggested future study in Chapter 5.
References
1. Lutzen, J., et al., "Integration of capacitor for sub-100-nm DRAM trench technology", VLSI Technology, Digest of Technical Papers, Symposium on 2002, pp. 178-179.
2. Koyanagi, M., "The Stacked Capacitor DRAM Cell and Three-Dimensional Memory", Solid-State Circuits Newsletter, IEEE, 2008. 13(1): pp. 37-41.
3. Takemae, Y., et al., "A 1Mb DRAM with 3-dimensional stacked capacitor cells", Solid-State Circuits Conference, Digest of Technical Papers, IEEE International, 1985, pp. 250-251.
4. Kimura, K., et al., "A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier", Solid-State Circuits, IEEE , 1987, pp. 651-656.
5. Ema, T., et al., "3-dimensional stacked capacitor cell for 16 M and 64 M DRAMS", International Electron Devices Meeting, 1988, Technical Digest., 1988, pp. 592-595.
6. Changhyun, C., et al. "A 6F2 DRAM technology in 60nm era for gigabit densities",VLSI Technology, Digest of Technical Papers, Symposium on. 2005, pp.36-37.
7. Jun Sugiura, "Influence of Contaminants on Device Characteristics", Ultraclean Surface Processing of Silicon Wafers, Springer, Ed. 1998, Japan.
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8. Hitsohi, M., Ohmi, T.(Ed), "Principles of Semiconductor Device Wet Cleaning", Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, United States.
9. W. Kern and D.A. Puotinen, "Cleaning solution based on hydrogen peroxide for use in silicon semiconductor technology", 1970, RCA Rev. 31 : pp.187-206.
10. Hattori, D.T., "Ultraclean Surface Processing of Silicon Wafers.", Ultraclean Techonology for VLSI Manucfacturing: An Overview, Springer, Ed. 1995, Japan.
11. Hiroshi, M., Akinobu, T., Hitoshi M., Senri, O., Kenichi M., Ohmi, T.(Ed),
"High-Performance Wet Cleaning Technology", Scientific Wet Process Technology for Innovative LSI/FPD Manufacturing, Ed. 2006, United States.
Chapter 2: Overview of Particulate Contamination Aspects: Defect and Particle Sources Analysis
2.1 Introduction
In the semiconductor process, the word “contamination” has generally implied any items other than intentionally applied matter and morphologies which adhere inadvertently to the wafer and give rise to external disturbances. Silicon is constitutionally very sensitive to these kinds of external disturbance, and this sensitivity has been exacerbated by the development of ultrafine processes [1].
Contaminants are morphologically categorized into four groups: particles, metallic contaminants, organic contaminants, and unintended native oxide. A cleaning process is required to thoroughly remove these contaminants without inducing any adverse side effects such as excessive etching, increase of surface microroughness, and pattern damage [1].
The device characteristic degradation caused by each form of contamination is shown in Table 2.1 [2], and these connections are not independent phenomena, but rather, are interrelated in a complex way, and even hasten the development of each other. The
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structure of ultrafine devices with high aspect ratios causes a local concentration of stress within the wafer, which influences the distribution of metallic contaminants and other impurities; this seems to accelerate degradation, such as the reduction of the dielectric strength of thin insulating films and the increase of junction leakage current.
Because degradation is generated by this kind of reciprocal action between the device structure and contamination, the same contamination level can result in failures in some devices and none in others. Of the various forms of contamination, the one which causes most device failures in mass production is the particle. In fact, more than 70 to 80% of the sources of yield reduction in DRAM devices are due to particles.
The rest are due mostly to metallic contamination. Other problems appear during process development and trial operations of new equipment, and in many cases countermeasures can be found before they are implemented in mass production.
Table 2.1 Device characteristic degradation due to contamination.
Contaminant Degradation of device characteristic
Particle
Pattern defects, oxide dielectric strength failure, ion-implantation failure
Metallic Ion
Junction leakage failures, interface states increase, Vth shift, gate oxide degradation, lifetime reduction
Organics
Abnormal film growth, contact resistivity increase, crystalline defects, gate oxide degradation
Native Oxide Film
Contact resistivity increase, crystalline defects (Epi), selectivity degradation of selective CVD, gate oxide integrity degradation Surface
microroughness
Gate oxide integrity degradation, mobility degradation due to surface scattering
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Particle contamination has for the most part entailed measuring the number of particles and their diameters, but in order to determine the origin of contamination and devise an effective countermeasure for its prevention, it is also essential to analyze the particle composition and chemical states.
This chapter will give an overview of analysis for particles adhered to the wafer after crown capacitor wet process, so that we can take a fuller look at the direction of improvements.
2.2 Origins of Defect and Particles Occurrence
In order to clarify the defect source of the crown capacitor process, a step-by-step defect analysis is undergone. The defect inspection is executed after crown wet etch, high-k deposition, CVD TiN deposition, boron poly-silicon deposition, tungsten sputter, PETEOS deposition and tungsten etch respectively. This analysis used 6 wafers in 1 lot to check the defects occurrence and its origin. Defects are categorized into two simple classifications: big particle defects and sheet particle defects. A more detailed defect classification will be used in experimental design.
As shown in Figure 2.1, most of the big particles and sheet particle defects originate
from the 3S crown capacitor process. In the crown wet process step, particle generation occupied 50% of all investigated process. Hence, understanding particles generated on crown capacitor wet etch back process is very important to gain a better line yield for 68 nm DRAM.
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Figure 2.1 Defect source step-by-step inspection.
2.3 Types and Composition Analysis of Particles
In the semiconductor production line, short cycle time and high yield are demanded.
In order to ensure high yield in mass production, it is very important to control, reduce, and prevent the particles generated by each process step. Finishing the product requires days or even months, it is often too late to begin detection and analysis at the end of the process; in addition, it becomes increasingly difficult to isolate the deficiencies of a process after several steps. Thus, defects detection at an early stage, after the process step, can help us measure the number of particles and their diameters;
as well as determine the origin of contamination and analyze the particle composition of chemical states [2].
Both Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS) are applied in this analysis. SEM is used to produce the image for particle morphology; while, EDS can provide elemental analysis.
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2.3.1 Defect Types Categorization
In this investigation, the 300mm wafer is divided into two zones to clarify the defect sources: zone A, 15mm to the edge; zone B, radius of 135mm from the center (Figure 2.2). Defects are classified according to shape, size, and elemental component. The cover rate of each zone will be analyzed.
Figure 2.2 Schematic of specimen defect zone. (Zone A: 15mm to wafer edge; Zone B:
radius 135mm from wafer center).
2.3.2 Analysis of Composition
Figure 2.3 shows the distribution of defects in zone A. 65% of the particles in zone A are larger than 1μm, these include big sheet particles and big peeling particles; which are mostly titanium (Ti) or titanium nitride (TiN). Another 35% of particles covered on the wafer are smaller than 0.5μm, and they are notable as small particles. These small particles contain both Ti and TiN. The reason Ti and TiN appear on the wafer edge is speculated to be due to the pattern damage from ugly dies during lithography and etching processes. Bottom electrodes that are made of Ti can be weak and easy to collapse.
As for Figure 2.4, defects in zone B are described. Mostly defect particles distributed in the wafer center are organic-like residues. They consist of carbon, oxygen, and some of them are fluoro-like. The reaction of 49% HF and BPSG is believed to form these kinds of carbon rich, silicon rich and fluorine rich residues. These residues are believed to be chemicals bonded with the surface of Ti and form strong van der wall forces.
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Figure 2.3 Categorization and EDS analysis for defects at zone A.
Figure 2.4 Categorization and EDS analysis for defects at zone B (135 mm in radius from wafer center).
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2.4 Effects of Particulate Contaminations on DRAM Device
Device characteristic degradation due to particles include pattern defects, degradation of the insulating film’s dielectric strength, and failures due to local masking during ion implantation and etching. Of these, the biggest cause of degradation is the pattern defect. Wafer yield loss is mostly determined by short and open circuits caused by particles generated during metallization [3].
2.4.1 Defect Impact on Wafer Yield Failure
Figure 2.5 (a) and (b) compare the direct impact of defects after the crown wet etch process on the wafer failure map. As in Figure 2.5 (a) the failure of Icc2standby current is coloured in pink; the notch orientation of lot A during 49%HF wet process is shown by an arrow pointing at the bottom of the tank (Figure 2.5 a): the wafer failure map shows exactly the same distribution as the defect inspection map. On the other hand, in lot B (Figure 2.5 b) the notch orientation is 180 degrees reversed to the top and both the defects map and wafer failure map rotates. Meanwhile, as observed from both Figure 2.5 (a) and (b), the coverage of defects near the bottom of the tank is proved to be denser compared to the top and wafer center. This is mainly due to the flow field close to the wafer guide and the frictions at the touch point between wafer guide and wafers.
Figure 2.6 is the analysis in wafer failure test. The SEM cross-section indicates that the particle defects appear before High-K dielectric deposition but after bottom TiN electrode formation. Thus, it is proofs that these particle defects comes from crown wet capacitor etch process from wet bench.
(a)
(b)
Figure 2.5 (a) Failure map versus in-line defect map of lot A; wafer notch pointed to bottom of wet bath tank during crown wet etch back process. (b) Failure map versus in-line defect map of lot B; wafer notch pointed to top of wet bath tank during crown wet etch back process.
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(a) (b)
Figure 2.6 (a) Top view of particle defect induced capacitor short (b) Cross section of particle defects appear before high-K dielectric deposition and after bottom TiN electrode formation.
2.4.2 Summary of Yield Loss for Each Defect Categorization
All defects including pattern collapse, particles and residues after the crown wet etch process are taken into account the yield loss. 250 wafers together with defects and wafer yield data are compared and analyzed. The average yield loss is predicted. Table 2.2 summarizes the correlation of each defect type after crown wet etch to the yield loss. However, pattern collapse and penetration which caused 1 percent of yield loss will not be focused on this study. This study will focus generally on the particle removal ability: how to remove big sheet particles, residues, peeling particles and wafer edge cluster, small particles, that totally impact 2.2 percent of wafer yield loss will be evaluated.
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Table 2.2 Summary of yield loss for crown wet etch defects.
2.5 Particle Adhesion in a Liquid Bath
To understand the particle detachment from the wafer surface, it is essential to understand the particle adhesion on the wafer. This section will briefly introduce three
To understand the particle detachment from the wafer surface, it is essential to understand the particle adhesion on the wafer. This section will briefly introduce three