未來展望

第四章結論與未來展望

4.2 未來展望

近年來，隨著鰭式場效電晶體(FinFET)的發明，其特性相對傳統 CMOS 來的好，已有漸漸取代的趨勢，鰭式場效電晶體又有分成雙閘跟三閘，隨然三閘有較佳控制能力，但製程上以雙閘較為容易，因閘極類似立體架構，可大幅降低漏電流問題，隨著半導體產業持續微縮，這可是相當受用的。材料方面，目前以石墨烯(Graphene)、鍺(Ge)、III-V 半導體來改善通道內載子移動率。雖然有鰭式場效電晶體這種新結構產生，但元件微縮不是沒有盡頭，當通道小於 10nm 則造成量子穿隧效應增加，這也是日後需克服的問題

圖 2 - 1 實驗室整體量測環境

圖 2 - 2 4156B 半導體參數分析儀

圖 2 - 3 八吋探針座(DC Probe Station)

圖 2 - 4 機台開關轉換裝置 E5250A

圖 2 - 5 量測軟體 ICS

圖 2 - 6 繪圖軟體 OriginPro 6.0

圖 2 - 7 Double Gate FinFET 結構圖

0.1 1

-1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7

0.05 0.2

PMOS

V th (V )

Gate Length( µm)

Filled ：W=10

Vacant ：W=2

圖 2 - 8 pFET 之不同閘極通道長度與臨界電壓(Vth)關係圖

0.1 1 55

60 65 70

0.05 Filled PMOS ：W=1

Vacant ：W=2

0.2 S S (m V /d e c )

Gate Length(µm)

圖 2 - 9 pFET 之不同閘極通道長度與次臨界擺福(SS)關係圖

-1.5 -1.0 -0.5 0.0

10

^-14

10

^-12

10

^-10

10

^-8

10

^-6

10

^-4

10

^-2

pFET W=10nm H=30nm

L=0.05µm L=0.1µm L=0.2µm L=1µm

Dr a in Cu rr e n t( A)

Gate Voltage(Volt)

圖 2 - 10 pFET 之不同閘極通道長度 ID-VG圖

-1.5 -1.0 -0.5 0.0 0.0

4.0x10

^-5

8.0x10

^-5

1.2x10

^-4

1.6x10

^-4

pFET W=10nm H=30nm

L=0.05 µm L=0.1 µm L=0.2 µm L=1µm

G m (A /V )

Gate Voltage(V)

圖 2 - 11 pFET 之不同閘極通道長度轉導對電壓關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0 2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

1.0x10

^-3

pFET W=10nm H=30nm

L=0.05 µm L=0.1 µm L=0.2 µm L=1µm

Dr a in Cu rr e n t( A)

Drain Voltage(Volt)

圖 2 - 12 pFET 之不同閘極通道長度 ID-VD圖

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

-1.5 -1.0 -0.5 0.0 0.0

4.0x10

^-5

8.0x10

^-5

1.2x10

^-4

1.6x10

^-4

pFET W=10nm L=50nm

G m (A /V )

Gate Voltage(V)

W=10nm W=25nm

圖 2 - 15 pFET 之不同鰭寬度轉導對電壓關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0 2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

1.0x10

^-3

1.2x10

^-3

pFET W=10nm L=50nm

W=10nm W=25nm

Dr a in Cu rr e n t( A)

Drain Voltage(V)

圖 2 - 16 pFET 之不同鰭寬度 ID-VD圖

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 10

^-13

10

^-11

10

^-9

10

^-7

10

^-5

10

^-3

10

^-1

10 W=10nm W=25nm pFET W=10nm L=50nm

G at e C u rr en t( A )

Gate Voltage(V)

圖 2 - 17 pFET 之不同鰭寬度 IG-VG圖

圖 3 - 1 熱載子效應量測流程圖開始

進行電性壓迫(stress)之前，在室溫(25°C)的情況下量測I_D

-V

_G、

I

-V

_D及I_G

-V

設定電性壓迫的電壓及時間

ICS自動量測流程

每段電性壓迫時間結束後量測I_D

-V

_G、I_D

-V

_D 及I_G

-V

分段壓迫時間是否完成

完成電性壓迫(stress)流程後，量測I_D

-V

_G、I_D

-V

_D及I_G

-V

量測完畢

否

是

圖 3 - 2 負偏壓不穩定性量測流程圖開始

進行電性壓迫(stress)之前，在室溫(25°C)的情況下量測I_D

-V

_G、

I

-V

_D及I_G

-V

設定電性壓迫的電壓及時間

ICS自動量測流程

每段電性壓迫時間結束後量測I_D

-V

_G、I_D

-V

_D 及I_G

-V

分段壓迫時間是否完成

完成電性壓迫(stress)流程後，量測I_D

-V

_G、I_D

-V

_D及I_G

-V

量測完畢

否

是

-1.5 -1.0 -0.5 pFET L=90nm W=10nm H=30nm

HCI V

=V

= -2.5V pFET L=90nm W=10nm H=30nm

HCI V

-1.5 -1.0 -0.5 pFET L=90nm W=10nm H=30nm

HCI V

pFET L=90nm W=10nm H=30nm

HCI V

=V

= -2.8V

1 10 100

pFET L=90nm W=10nm H=30nm

HCI for 100min

pFET L=90nm W=10nm H=30nm

n=0.159

0 20 40 60 80 100

100 L=90nm W=10nm H=30nm

S ubt hr e s hol d S w ing

Time(min)

HCI for 100 min V

=-2.5V L=90nm W=10nm H=30nm

G m (A /V )

Gate Voltage(V)

圖 3 - 10 pFET 在閘極與汲極加上-2.5V 的 Stress 電壓 100 分鐘前後 Gm 變化圖

-1.5 -1.0 -0.5 0.0 L=90nm W=10nm H=30nm

G m (A /V ) L=90nm W=10nm H=30nm

G m (A /V )

Gate Voltage(V)

圖 3 - 12 pFET 在閘極與汲極加上-2.7V 的 Stress 電壓 100 分鐘前後 Gm 變化圖

-1.5 -1.0 -0.5 0.0 L=90nm W=10nm H=30nm

G m (A /V )

8.0x10

^-4

pFET L=90nm W=10nm H=30nm

HCI V

=V

= -2.5V

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.0

2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

pFET L=90nm W=10nm H=30nm

HCI V

=V

= -2.6V ST= Fresh

ST= 1 min_∆=2.88%

ST= 10 min_∆=5.24%

ST=100min_∆=7.47%

Dr a in Cu rr e n t( A)

Drain Voltage(V)

圖 3 - 15 pFET 在閘極與汲極加上-2.6V 的 Stress 電壓 100 分鐘前後 ID-VD關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0 2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

pFET L=90nm W=10nm H=30nm

HCI V

=V

= -2.7V ST= Fresh

ST= 1 min_∆=5.72%

ST= 10 min_∆=7.98%

ST=100min_∆=10.37%

Dr a in Cu rr e n t( A)

Drain Voltage(V)

圖 3 - 16 pFET 在閘極與汲極加上-2.7V 的 Stress 電壓 100 分鐘前後 ID-VD關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.0

2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

pFET L=90nm W=10nm H=30nm

HCI V

=V

= -2.8V ST= Fresh

ST= 1 min_∆=4.53%

ST= 10 min_∆=7.07%

ST=100min_∆=15.2%

Dr a in Cu rr e n t( A)

pFET HCI for 100 min

V

=-2.8V

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

pFET L=90nm W=10nm H=30nm HCI V

= -2.5V

pFET L=90nm W=10nm H=30nm

HCI V

= -2.6V

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

pFET L=90nm W=10nm H=30nm

HCI V

= -2.8V

-1.5 -1.0 -0.5 0.0

Fresh Device HCI @ V

=1/2V

1.2x10

^-4

Fresh Device

HCI @ V

=1/2V

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

pFET After 100min @V

= -2.5V

Fresh Device HCI @ V

=1/2V

Fresh Device

HCI @ V

=1/2V

1 10 100 1

10 100

pFET HCI at 25

⁰

C Stress for 100 min

0.6V_D

1.2 Hot Carrier Injection

0.9V

Ti m e P ow e r E x pone nt n

Gate Voltage

0.09

圖 3 - 28 pFET 在不同 Stress 電壓下 100 分鐘前後 n 值比較圖

-1.5 -1.0 -0.5 0.0 0.5

pFET L=90nm W=10nm H=30nm

Dr a in Cu rr e n t( A)

pFET L=90nm W=10nm H=30nm

Dr a in Cu rr e n t( A)

-1.5 -1.0 -0.5 0.0 0.5

pFET L=90nm W=10nm H=30nm

Dr a in Cu rr e n t( A)

-0.92 pFET L=90nm W=10nm H=30nm

∆ V th

1 10 100 1000 10 n=0.18

n=0.18 n=0.19

pFET L=90nm W=10nm H=30nm

Thr e s hol d V ol ta ge (% )

Time(s)

NBTI for 1000s V

=-2.8V V

=-2.9V V

=-3.0V

圖 3 - 33 pFET 在不同的 Stress 電壓下 1000 秒前後臨界電壓 Vth變化量對 Stress 時間變化圖

1 10 100 1000

64 68 72 76

L=90nm W=10nm H=30nm

S ubt hr e s hol d S w ing

Time(min)

NBTI for 100 min V

=-2.8V V

=-2.9V V

=-3.0V

圖 3 - 34 pFET 在不同的 Stress 電壓下 1000 秒前後臨界斜率 SS 對 Stress 時間變化圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0 2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

L=90nm W=10nm H=30nm

Dr a in Cu rr e n t( A)

Drain Voltage(V)

NBTI V

= -2.8V ST= Fresh

ST= 100 s_ ∆= 5.14%

ST= 1000 s_ ∆= 8.99%

圖 3 - 35 pFET 在閘極加上-2.8V 的 Stress 電壓 1000 秒前後 ID-VD關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0 2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

L=90nm W=10nm H=30nm

Dr a in Cu rr e n t( A)

Drain Voltage(V)

NBTI V

= -2.9V ST= Fresh

ST= 100 s_ ∆= 6.68%

ST= 1000 s_ ∆=10.71%

圖 3 - 36 pFET 在閘極加上-2.9V 的 Stress 電壓 1000 秒前後 ID-VD關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

L=90nm W=10nm H=30nm

Dr a in Cu rr e n t( A) pFET L=90nm W=10nm H=30nm _V

=-3.0V

∆ I D (%)

Time(min)

圖 3 - 38 pFET 在不同的 stress 電壓 1000 秒前後 ID-VD衰退圖

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

pFET L=90nm W=10nm H=30nm

G at e C u rr en t( A )

pFET L=90nm W=10nm H=30nm

G at e C u rr en t( A )

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

pFET L=90nm W=10nm H=30nm

G at e C u rr en t( A )

pFET L=90nm W=10nm H=30nm

G m (A /V )

Gate Voltage(V)

圖 3 - 42 pFET 在閘極加上-2.8V 的 Stress 電壓 1000 秒前後 Gm 變化圖

-1.5 -1.0 -0.5 0.0

pFET L=90nm W=10nm H=30nm

G m (A /V )

pFET L=90nm W=10nm H=30nm

G m (A /V )

Gate Voltage(V)

圖 3 - 44 pFET 在閘極加上-3.0V 的 Stress 電壓 1000 秒前後 Gm 變化圖

-1.5 -1.0 -0.5 0.0

10

^-4

pFET for L=90nm

Dr a in Cu rr e n t( A)

Gate Voltage(V)

NBTI @ V

=-2.8V

W=10nm_Fresh W=10nm_ST=1000s

pFET for L=90nm

Dr a in Cu rr e n t( A)

Gate Voltage(V)

NBTI @ V

=-2.9V

W=10nm_Fresh

W=10nm_ST=1000s

-1.5 -1.0 -0.5 0.0 10

^-14

10

^-12

10

^-10

10

^-8

10

^-6

10

^-4

NBTI @ V_G

=-3.0V

W=10nm_Fresh W=10nm_ST=1000s W=25nm_Fresh W=25nm_ST=1000s

pFET for L=90nm

Dr a in Cu rr e n t( A)

Gate Voltage(V)

圖 3 - 47 pFET 在不同鰭寬度下加上-3V 的 Stress 電壓 1000 秒前後 ID-VG關係圖

1 10 100 1000

10 pFET NBTI for L=90nm ST=1000s

@V

= -2.8V

W=10nm_n=0.19 W=25nm_n=0.18

∆ V th (%)

Time(s)

圖 3 - 48 pFET 在不同鰭寬度下加上-2.8V 的 Stress 電壓 1000 秒前後臨界電壓 Vth

變化量對 Stress 時間變化圖

1 10 100 1000 10

W=10nm_n=0.18 W=25nm_n=0.16 pFET NBTI for L=90nm ST=1000s

@V

= -2.9V

∆ V th (%)

Time(s)

圖 3 - 49 pFET 在不同鰭寬度下加上-2.9V 的 Stress 電壓 1000 秒前後臨界電壓 Vth

變化量對 Stress 時間變化圖

1 10 100 1000

10 pFET NBTI for L=90nm ST=1000s

@V

= -3.0V

W=10nm_n=0.18 W=25nm_n=0.15

∆ V th (%)

Time(s)

圖 3 - 50 pFET 在不同鰭寬度下加上-2.9V 的 Stress 電壓 1000 秒前後臨界電壓 Vth

變化量對 Stress 時間變化圖

-2.80 -2.85 -2.90 -2.95 -3.00 16

18 20 22 24 26 28 30

32 pFET for L=90nm

NBTI for 1000s W=10nm W=25nm

∆ V th (%)

Stress Voltage(V)

圖 3 - 51 pFET 在不同鰭寬度、不同 Stress 電壓下臨界電壓 Vth變化圖

-2.80 -2.85 -2.90 -2.95 -3.00

0.15 0.16 0.17 0.18

0.19 pFET for L=90nm

NBTI for 1000s W=10nm W=25nm

Ti m e P ow e r E x pone nt n

Strsss Voltage(V)

圖 3 - 52 pFET 在不同鰭寬度下 1000 秒前後 n 值對 VG關係圖

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

W=10nm_Fresh W=10nm_ST=1000s

W=10nm_Fresh

W=10nm_ST=1000s

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.0

2.0x10

^-4

4.0x10

^-4

6.0x10

^-4

8.0x10

^-4

1.0x10

^-3

pFET NBTI for L=90nm @V

= -3.0V

Dr a in Cu rr e n t( A)

Drain Voltage(Volt)

W=10nm_Fresh W=10nm_ST=1000s W=25nm_Fresh W=25nm_ST=1000s

圖 3 - 55 pFET 在不同鰭寬度下加上-3.0V 的 Stress 電壓 1000 秒前後 ID-VD關係圖

-2.80 -2.85 -2.90 -2.95 -3.00

-12 -10 -8 -6

pFET for L=90nm

NBTI for 1000s W=10nm W=25nm

I D de ge nr a ti on( % )

Stress Voltage(V)

圖 3 - 56 pFET 在不同鰭寬度、不同 Stress 電壓下汲極衰退關係圖

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

W=10nm_Fresh W=10nm_ST=1000s

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 10

^-15

10

^-13

10

^-11

10

^-9

10

^-7

10

^-5

10

^-3

10

^-1

pFET NBTI for L=90nm @V

= -3.0V

W=10nm_Fresh W=10nm_ST=1000s W=25nm_Fresh W=25nm_ST=1000s

G at e C u rr en t( A )

Gate Voltage(Volt)

圖 3 - 59 pFET 在不同鰭寬度下加上-3.0V 的 Stress 電壓 1000 秒前後 IG-VG關係圖

-1.0 -0.8 -0.6 -0.4

0.0 1.0x10

^-4

pFET NBTI for L=90nm @V

= -2.8V

G m (A /V )

Drain Voltage(Volt)

W=10nm_Fresh W=10nm_ST=1000s W=25nm_Fresh W=25nm_ST=1000s

圖 3 - 60 pFET 在不同鰭寬度下加上-2.8V 的 Stress 電壓 1000 秒前後 Gm 變化圖

-1.0 -0.8 -0.6 -0.4 0.0

1.0x10

^-4

pFET NBTI for L=90nm @V

= -2.9V

G m (A /V )

Drain Voltage(Volt)

W=10nm_Fresh W=10nm_ST=1000s W=25nm_Fresh W=25nm_ST=1000s

圖 3 - 61 pFET 在不同鰭寬度下加上-2.9V 的 Stress 電壓 1000 秒前後 Gm 變化圖

-1.0 -0.8 -0.6 -0.4

0.0 1.0x10

^-4

pFET NBTI for L=90nm @V

= -3V

G m (A /V )

Drain Voltage(Volt)

W=10nm_Fresh W=10nm_ST=1000s W=25nm_Fresh W=25nm_ST=1000s

圖 3 - 62 pFET 在不同鰭寬度下加上-3.0V 的 Stress 電壓 1000 秒前後 Gm 變化圖

-2.80 -2.85 -2.90 -2.95 -3.00 -24

-22 -20 -18

-16 pFET for L=90nm

NBTI for 1000s W=10nm W=25nm

∆ G m (%)

Stress Voltage(V)

圖 3 - 63 pFET 在不同鰭寬度、不同 Stress 電壓下 Gm 關係圖

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2011.

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Study on Hot-Carrier Stress and Negative-Bias Stress Induced Degradation on P-Channel FinFET Devices

1 Jia-Jian Hong, ² Jie-Chen Wong, ²Ying-Ya Chen,²Tsu-Ting Cheng, ²Tzu-Sung Yen, ²Yi-Lin Yang and ¹Wen-Kuan Yeh,

1DEPARTMENT OF ELECTRICAL ENGINEERING, NATIONAL UNIVERSITY OF KAOHSIUNG

2DEPARTMENT OF ELECTRONIC ENGINEERING, NATIONAL KAOHSIUNG NORMAL UNIVERSITY

Abstract — In this paper, the hot carrier injection (HCI) and the negative bias temperature instability (NBTI) were investigated and compared as representative reliability issues for p-channel FinFET devices. The power law time exponent threshold voltage (VTH) shift was largest at VG=0.6VD for HCI stress. On the other hand, the power law time exponent is consistent and independent of gate voltage for NBTI stress.

INTRODUCTION

The dual-gate n-channel FinFET devices with high-k gate dielectric, as shown in Fig. 1, were fabricated on bulk Si under 28nm technology node. The FinFET has considered as one of the most promising options for future devices to replace planner MOSFETs. Due to the stronger

electrostatic control of the channel, short channel effect (SCE) could be suppressed effectively [1]. Hot carriers refer to electrons or holes in the substrate of a MOS device that have energies significantly above average. Hot carriers may be present due to a variety of circumstances, the MOSFETs, they may compromise operation of the device by generating charged defects in the oxide layer, and by degrading the oxide and the Si-SiO2 interface.

Negative Bias Temperature Instability (NBTI) is

considered the topmost reliability issue for scaled CMOS technologies [2]. Hot-Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) are important reliability concerns for pMOSFET.

However, fundamental understanding in FinFET reliability is still larking [3]. The most common method for the prediction of hot carrier lifetime is stressing the devices at high drain voltages while the gate voltage is

corresponding to the maximum substrate current (ISUB), and measuring the degradation of device with time [4].

For the conventional MOSFETs, it is reported the most serious degradation occurs at VG=VD/2. However, the differences in reliability between FinFET and conventional MOSFET are not quantified, and the characteristics of HCI and NBTI induced FinFET degradation is still unclear.

In this work, the examination of the conditions of HCI NBTI has been carried out in detail on FinFET devices.

Difference in threshold voltage (VTH) degradations could be observed by modulating gate voltages. The degradation phenomena were presented in this paper.

EXPERIMENTAL

The structure of the p-channel FinFET device was fabricated on bulk Si under 22nm

fabrication technology as shown in Fig. 1. The dimensions of the devices are 90nm, 10nm and 30nm for gate-length, fin-width and height, respectively.

The current-voltage (I-V) curves, were measured with an HP-4156B. After the basic electric measurements, the hot carrier injection was evaluated at room temperature. As the HCI was carried out, the gate voltage was set from 0.1 VD

to VD while VD=-2.5V. On the other hand, the gate voltage was set from -2.8V to -3V while NBTI measurement was applied. The I-V curves were then measured at intervals of a certain stress time.

RESULTS AND DISCUSSIONS

Figure 2(a) and 2(b) show the fresh and stressed ID-VG and ID-VD curves of the fresh p-channel FinFET devices and the devices after 100 minutes HCI stress with the stress conditions of VG=0.5VD and VG=VD. It could be observed that the stress condition of VG=VD shows the more serious degradation than another.

The threshold voltage shift against stress time is presented by power law as

ΔVth=Atⁿ (1)

was shown in Fig. 3, where n is power law exponent of VTH shift. The results found by the variation of n with different stress conditions were plotted as shown in fig. 4.

The maximum value of n is 1.10 and is observed at VG=0.6VD on pFinFET device structure.

From the prior research [5-6], it is known that different n indicates different type of damages. If n has value around 0.5, the damage is associated with interface states. On the other hand, if n is around 0.2-0.3, oxide traps are response for device degradation. In this research, the maximum value of n, which was approximately 1.1, could be observed at VG=0.6VD. On the other hand, with the continuously increasing of VG, the value of n is around 0.26 at VG=VD. It is interested that although the stress

-1.5 -1.0 -0.5 0.0

Fresh Device HCI @ V_G=1/2V_D

Fresh Device HCI @ V_G=1/2V_D HCI @ V_G=V_D condition of VG=VD shows the largest VTH shift than

others, it doesn’t show the maximum n. It is suggested that electron injection from gate electrode dominates the VTH

shift thus reduces the n value.

In order to make sure the suggestion, NBTI with various gate voltages were applied. Figure 5 shows the ID-VG

curves of device before and after -2.8V NBTI stress. A slight subthreshold swing variation could be observed.

The threshold voltage shift against stress time with various stress conditions were shown in Fig. 6. It could be

observed that the values of n are almost the same with various stress conditions. It is similar with the value of n under HCI with stress condition of VG=VD. The result indicates that VTH shift at VG=VD is caused by electron injection from gate electrode.

CONCLUSION

In this paper, we demonstrate in hot carrier induced p-channel FinFET degradation was studied at various VG

conditions. It is found that the most serious VTH

degradation happens at VG=0.6VD. On the other hand, the value of n reduced at VG=VD. It is because that hot carrier injection dominates the VTH shift at VG=0.6VD while electron injection is the main cause of VTH shift at VG=0.6VD.

Fig.1.Schematic view of the structure of FinFET device.

REFERENCES

Mingu Kang, “FinFET SRAM Optimization With Fin Thickness and Surface Orientation,” IEEE Trans. Electron Dev., vol. 57, no. 11, pp. 2785-2793, November 2010.

M. Cho et al., “Positive and Negative Bias Temperature Instability on sub-nanometer EOT high-k MOSFETs”, in Proc. IRPS, pp. 1095-1098, 2010

M. Wang, “Superior PBTI Reliability for SOI FinFET Technologies and Its Physical Understanding,” IEEE Electron Dev. Lett., vol. 34, no. 1, pp. 837-839, July 2013 B. S. Doyle, “Examination of the Time Power Law Dependencies in Hot Carrier Stressing of n-MOS Transistors,” IEEE Electron Device Lett., Vol. 18, no. 2, pp. 51-53, 1997

B. S. Doyle, “The Generation and Characterization of Electron and Hole Traps Created by Hole Injection During

Low Gate Voltage Hot-Carrier Stressing of n-MOS Transistors,” IEEE Trans. Electron Devices, vol. 37, no. 8, pp.1869 -1876, 1990

E. Takeda, “An Empirical Model for Device Degradation Due to Hot-Carrier Injection,” IEEE Electron Device Lett., vol. 4, no. 4, pp.111-113, 1983

1.2 Hot Carrier Injection

0.9V_D

Ti m e P ow e r E x pone nt n

Gate Voltage

0.09

(a)

(b)Fig.2 (a) The ID-VG curves and (b) ID-VD curves of pFinFET devices before and after HCI stress for 100 min.

0.0

1.2 Hot Carrier Injection

0.9V_D

T im e P o w e r E x p o n e n t n

Gate Voltage(Volt)

Fig.3 The HCI threshold voltage shift against stress time for 100 min.

Fig. 4 The extracted power law exponents against stress conditions.

Fig.5 The ID-VG curves of pFinFET devices before and after NBTI stress for 1000 sec

Fig.6 The NBTI threshold voltage shift against stress time for 1000 sec. NBTI @ pFinFET For 1000 sec

Dr a in Cu rr e n t( A)

Gate Voltage(Volt)

Fresh Device Stress Time=100s Stress Time=1000s

1 10 100 1000 10000

10¹

pFET NBTI at 25⁰C Stress for 1000 sec

n=0.178

在文檔中不同尺寸之P型先進鰭式場效電晶體可靠度之研究 (頁 37-88)

第四章 結論與未來展望

4.2 未來展望

0.1 1

-1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7

0.05 0.2

PMOS

V th (V )

Gate Length( µm)

Filled ：W=10

Vacant ：W=2

0.1 1 55

60 65 70

0.05

Filled PMOS ：W=1

Vacant ：W=2

0.2

S S (m V /d e c )

Gate Length(µm)

-1.5 -1.0 -0.5 0.0

10

10

10

10

10

10

10

pFET W=10nm H=30nm

L=0.05µm L=0.1µm L=0.2µm L=1µm

Dr a in Cu rr e n t( A)

Gate Voltage(Volt)

-1.5 -1.0 -0.5 0.0 0.0

4.0x10

8.0x10

1.2x10

1.6x10

pFET W=10nm H=30nm

L=0.05 µm L=0.1 µm L=0.2 µm L=1µm

G m (A /V )

Gate Voltage(V)

0.0 2.0x10

4.0x10

6.0x10

8.0x10

1.0x10

pFET W=10nm H=30nm

L=0.05 µm L=0.1 µm L=0.2 µm L=1µm

Dr a in Cu rr e n t( A)

Drain Voltage(Volt)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

-1.5 -1.0 -0.5 0.0 0.0

4.0x10

8.0x10

1.2x10

1.6x10

pFET W=10nm L=50nm

G m (A /V )

Gate Voltage(V)

W=10nm W=25nm

-1.0 -0.8 -0.6 -0.4 -0.2 0.0

0.0 2.0x10

4.0x10

6.0x10

8.0x10

1.0x10

1.2x10

pFET W=10nm L=50nm

W=10nm W=25nm

Dr a in Cu rr e n t( A)

Drain Voltage(V)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 10

10

10

10

10

10

10

10

W=10nm W=25nm pFET W=10nm L=50nm

G at e C u rr en t( A )

第四章結論與未來展望