第七章 結論與建議
第二節 未來研究建議
本研究無論是在產能規劃模式或是現場管控法則的發展上，都是以等候模 型為基礎。然而，等候模型基本上只適用於長期穩態的系統環境。雖然本研究 已針對傳統等候模型完成某些必要的模式修正，使其能更貼近生產系統中的動 態環境。然而，生產系統是一具有高度複雜性之環境，此環境之下有著許多的 動態行為，例如，產品的加工優先順序可能在等候過程中因管理者需求而動態 調整。如何讓決策模式更能顧及動態環境，特別是現場管控法則的建立上，是 未來相關研究一個可以努力的方向。
再者，本研究所提出之產能規劃模式雖然允許管理者自行設定其希望之良 率目標值，然而，卻尚未提出一套該如何制訂目標值的決策過程。後續相關研 究可以試著把成本因素納入產能決策之中，如此才能找出最具成本效益之系統 良率目標。
參考文獻
林忠文(2004)。晶圓製造廠連續型時間限制問題之產能決策模式。未出版之碩士 論文，私立中華大學科技管理研究所，新竹市。
Bala R., & Gunvant, P. (1998). Modelling Furnace Operations Using Simulation and Heuristics. Paper presented at the 1998 Winter Simulation Conference, DC, USA.
Benavides, D.L., Duley, J.R., & Johnson, B.E. (1999). As good as it gets: Optimal fab design and deployment. IEEE Transactions on Semiconductor Manufacturing, 12(3), 281–287.
Chen, H., Harrison, J. M., Mandelbaum, A., Ackere, V., & Wein, L. M. (1998).
Empirical evaluation of a queueing network model for semiconductor wafer fabrication. Operations Research, 36(2), 202-215.
Chou, W., & Everton, J. (1996). Capacity planning for development wafer fab expansion. Paper presented at the Advanced Semiconductor Manufacturing Conference and Workshop, Cambridge, MA.
Christie, R. M. E., & Wu, S. D. (2002). Semiconductor capacity planning: stochastic modeling and computational studies. IIE Transactions, 34(2), 131-143.
Chung, S. H., & Huang, H. W. (1999). The block-based cycle time estimation algorithm for wafer fabrication factories. International Journal of Industrial Engineering, 6(4), 307-316.
Cunningham, J. A. (1990). The use and evaluation of yield models in integrated circuit manufacturing. IEEE Transactions on Semiconductor Manufacturing, 3(2), 60-71.
Fowler, J. W., Brown, S., Gold, H., & Schoemig, A. (1997). Measurable improvements in cycle-time-constrained capacity. Paper presented at the 6th IEEE/UCS/SEMI International Symposium on Semiconductor Manufacturing, San Francisco, CA.
Fowler, J. W., Phojanamongkolkij, N., Cochran, J. K., & Montgomery, D. C. (2002).
Optimal batching in a wafer fabrication facility using a multiproduct G/G/c model with batch processing. International Journal of Production Research, 40(2), 275-292.
Glassey, C. R., & Weng, W. W. (1991). Dynamic batching heuristic for simultaneous processing. IEEE Transactions on Semiconductor Manufacturing, 4(2), 77-82.
Goldratt, E. M. (1990). The Haystack Syndrome. Great Barrington, MA: North River Press.
Goldratt, E. M. & Cox, J. (1992). The Goal. 2nd Edition, Great Barrington, MA:
North River Press.
Hood, S.J., Bermon, S., & Barahona, F. (2003). Capacity planning under demand uncertainty for semiconductor manufacturing. IEEE Transaction on Semiconductor Manufacturing, 16(2), 273-280.
Leachman, R. C., & Carmon, T. (1992). On capacity modeling for production planning with alternative machine types. IIE Transactions, 24(4), 62-72.
Lee, S. H., & Jung, M. Y. (2003). Timing constraints’ optimization of reserved tasks in the distributed shop-floor scheduling. International Journal of Production Research, 41(2), 397-410.
Louw, L., & Page, D.C. (2004). Queuing network analysis approach for estimating the size of the time buffers in Theory of Constraints-controlled production systems. International Journal of Production Research, 42(6), 1207-1226.
Neuts, J. D. C. (1967). A general class of bulk queues with Poisson input. Annals of Mathematical Statistics, 38(3), 759-770.
Pan W. S. S., & Iskandar W. W. (1997). A survey of scheduling rules. Operational Research, 25(1), 45-61.
Robinson, J. K. (1998). Capacity planning in a semiconductor wafer fabrication facility with time constraints between process steps. Unpublished doctoral dissertation, University of Massachusetts Amherst.
Robinson, J. K., & Giglio, R. (1999). Capacity planning for semiconductor wafer fabrication with time constraints between operations. Paper presented at the 1999 Winter Simulation Conference, Phoenix, AZ.
Rulkens, H. J. A., van Campen, E. J. J., van Herk, J., & Rooda, J. E. (1998). Batch size optimization of a furnace and pre-clean area by using dynamic simulations.
Paper presented at the 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Boston, MA.
Russ, M. D., & John, W. F. 2003. A new scheduling approach using combined dispatching criteria in wafer fabs. IEEE Transactions On Semiconductor Manufacturing, 16(3), 501-510.
Schoemig, A. K. (1999). On the corrupting influence of variability in semiconductor manufacturing. Paper presented at the 1999 Winter Simulation Conference, Phoenix, AZ.
Scholl, W., & Domaschke, J. (2000). Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations. IEEE Transactions on Semiconductor Manufacturing, 13(3), 61-63.
Srnivasan, K., Sandell, R., & Brown, S. (1995). Correlation between Yield and Waiting Time: A Quantitative Study. Paper presented at 1995 IEEE/CPMT International Electronics Manufacturing Technology Symposium, Texas, USA.
Tu, Y. M., Chao, Y. H., Chang, S. H., & You, H. C. (2005). Model to determine the backup capacity of a wafer foundry. International Journal of Production Research, 43(2), 339-359.
Tu, Y. M., & Chen, C. L. (2006a). The influence of arrival smoothing between batch and serial processes on system performance. Paper presented at the 7th Asia Pacific Industrial Engineering and Management Systems Conference 2006, Bangkok, Thailand.
Tu, Y. M., & Chen, H. N. (2006b). Waiting time approximation with resource failure.
Paper presented at the 2006 International Conference of Pacific RIM Management, Honolulu, USA.
Tu, Y. M., & Chen, H. N. (2009). Tool portfolio planning in the Back-End process of wafer fabrication with sequential time constraints. Journal of the Chinese Institute of Industrial Engineers, 26(1), 60-69.
Tu, Y. M., & Liou, C. S. (2006). Capacity determination model with time constraints and batch processing in semiconductor wafer fabrication. Journal of the Chinese Institute of Industrial Engineers, 23(3), 192-199.
Tu, Y. M., & Li, R. K. (1998). Constraint time buffer determination model.
International Journal of Production Research, 36(4), 1091-1103.
Vollmann, T. E., Berry, W. L., & Whybark, D. C. (1997). Manufacturing Planning and Control Systems. Irwin: McGraw-Hill.
Whitt, W. (1983). The queueing network analyzer. The Bell System Technical Journal, 62(9), 2779-2815.
Whitt, W. (1993). Approximations for the GI/G/m Queue. Production and Operations Management, 2(2), 114-161.
Weng, W. W., & Leachman, R. C. (1993). An improvement methodology for real-time production decision at batch-process workstations. IEEE Transactions on Semiconductor Manufacturing, 6(3), 219-225.
Wiley J. (1982). Sequencing and Scheduling: an Introduction to the Mathematics of the Job-shop. NY: Sons Inc.
Wolfgang, S., & Joerg, D. (2000). Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations. IEEE Transactions on Semiconductor Manufacturing, 13(3), 273-277.
capacity planning techniques within standard software packages. Production Planning & Control, 7(2), 117-128.
Wu, S. D., Erkoc, M., & Karabuk, S. (2005). Managing capacity in the high-tech industry: A review of literature. The Engineering Economist, 50(2), 125-158.
附錄 A
數學式部分
1. 式(15)中之α與β：
∑=
− − + −
+ +
−
= n
i
s ij s
i i ij ij j
j p q m ci q cj
1
2' 2 2
5 .
0 (max{ ,0.2} 1] (1 ) ) 1
[ (
1 ω ω ρ
α (A1)
)]
1 ( ) 1
[( i2 ij
ij ij
jp q − + −q
=ω ρ
β (A2)
1
2( 1)]
) 1 ( 4 1
[ + − − −
= j j
j ρ ν
ω (A3)
1 0
2] [ −
∑
== n
i ij
j p
ν (A4)
j ij ij
p =λ λ (A5)
2. 式(16)中之φ(λj,Caj2,τ'j,Csj2',mj)：
) , , , ,
(λj Caj2 τ'j Csj2' mj
φ =
2 2 2
2 2 2
2 2 1
2 2 2
2 2 2
2 2 2
2 2 2 1
2 2 2
, ) , 2 , ( 3 ) (4 ) , ( 3 ) 4
) ( (4
), , 2 , ( 2 ) 2 ( 3 ) , ( 2 ) 2
) ((
sj aj j j sj aj sj aj
sj j j sj aj
sj aj
sj aj j j sj aj sj aj
aj sj j j sj aj
aj sj
c c c m
c c c m c c c
c c
c c c m
c c c
c m c
c c
c c
+ ≥ + −
−
−
+ <
+ + + +
=
− φ ρ ψ ρρ ψ
ρ
φ (A6)
) , ,
( 2 ρ
ψ c m ( 1, ) 0 1 1
2 ) 2
1 2 ( 2 4
≥
≤
≤
=
− c cmρ c
φ (A7)
2 }
) , ( ) , , ( 1
min{ 1 3
4
ρ φ ρ
φ = φ m + m
(A8)
) 3 / ) 1 ( 2 exp(
) , ( ) ,
( 2
3 ρ φ ρ ρ ρ
φ = m = m − − (A9)
) , ( 4 1 ) ,
2( ρ γ ρ
φ m = − m (A10)
) , ( 1 ) ,
1( ρ γ ρ
φ m = + m (A11)
16 }
) 2 5 4 )(
1 )(
1 ,( 24 . 0 min{
) ,
( ρ
ρ ρ
γ m
m
m = − m− + − (A12)
) 1 (
) ) (
/ /
( ρ
τ
−
= ≥
j j j
j m
m N m P
M M
EW (A13)
ρ ξ
ρ ]
) 1 (
! ) [(
)
( ≥ = −
j m j j
j m
m m N P
j
(A14)
1 1
0
! ] ) ( ) 1 (
! )
[ ( −
−
∑
=− +
= j
j m
h
h j j j
j m j j
h m m
m ρ
ρ ξ ρ
(A15)
附錄 B
晶圓廠後段製程之產品製程表
產品 A
加工步驟 站別 加工時間 (hr)
TC
(hr) 加工步驟 站別 加工時間 (hr)
TC (hr) 1 Suppter 0.51 25 Suppter 0.48
2 Descum 0.53 5 26 Descum 0.50 5 3 Scrubber 0.67 5 27 Scrubber 0.73 5 4 Photo 0.70 28 Photo 0.90
5 Baking 0.78 5 29 Baking 0.52 5 6 Etching 0.70 5 30 Etching 0.90 5 7 PR strip 0.82 5 31 PR strip 0.82 5 8 CD mes. 0.63 32 CD meas. 0.70
9 Suppter 0.45 33 Suppter 0.50
10 Descum 0.50 5 34 Descum 0.48 5 11 Scrubber 0.68 5 35 Scrubber 0.41 5 12 Photo 0.82 36 Photo 0.92
13 Baking 0.90 5 37 Baking 0.57 5 14 Etching 0.82 5 38 Etching 0.92 5 15 PR strip 0.82 5 39 PR strip 0.82 5 16 CD meas. 0.65 0 40 CD meas. 0.41
17 Suppter 0.50
18 Descum 0.47 5 19 Scrubber 0.68 5 20 Photo 0.85
21 Baking 0.90 5 22 Etching 0.85 5 23 PR strip 0.82 5 24 CD meas. 0.68
產品 B
Step 站別 加工時間 (hr)
TC (hr)
Step 站別 加工時間 (hr)
TC (hr) 1 Suppter 0.52 25 Suppter 0.53
2 Descum 0.53 6 26 Descum 0.55 6 3 Scrubber 0.68 6 27 Scrubber 0.67 6 4 Photo 0.87 28 Photo 0.88
5 Baking 0.47 6 29 Baking 0.50 6 6 Etching 0.88 6 30 Etching 0.95 6 7 PR strip 0.75 6 31 PR strip 0.75 6 8 CD meas. 0.70 32 CD meas. 0.72
9 Suppter 0.53 33 Suppter 0.50
10 Descum 0.50 6 34 Descum 0.57 6 11 Scrubber 0.68 6 35 Scrubber 0.71 6 12 Photo 0.92 36 Photo 0.92
13 Baking 0.52 6 37 Baking 0.61 6 14 Etching 0.92 6 38 Etching 0.92 6 15 PR strip 0.75 6 39 PR strip 0.75 6 16 CD meas. 0.68 40 CD meas. 0.72
17 Suppter 0.55 41 Suppter 0.54
18 Descum 0.55 6 42 Descum 0.52 6 19 Scrubber 0.65 6 43 Scrubber 0.67 6 20 Photo 0.95 44 Photo 0.92
21 Baking 0.50 6 45 Baking 0.47 6 22 Etching 0.90 6 46 Etching 0.87 6 23 PR strip 0.75 6 47 PR strip 0.75 6 24 CD meas. 0.68 48 CD meas. 0.70