本論文提出了一個數位輔助式閘式壓控震盪器的突發式時脈與 資料回復電路 (A Digitally Assisted Gated VCO Based Burst-Mode CDR)，
由頻率檢知器電路(Frequency Locked Detector)、十六位元上、下計數 器(U/D Counter)、寬範圍多模數除頻器(Modulus Divider)、電流式數位 類 比 轉 換 器 (Current Steering DAC) 、 和 差 調 變 器 (Delta-Sigma
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