本論文主要設計與實作出低功耗鎖相迴路電路與低功耗電壓控制振盪器，藉 由國家晶片中心所提供的 TSMC CMOS 0.18-µm 與 90-nm 製程設計驗證。
在第三章實現低電壓低功耗的 K-band 變壓器回授之電壓控制振盪器，其供應 電壓僅需要 1.1 V，消耗功率約為 1 mW。調變範圍為 19.4 GHz 至 19.99 GHz。相 位雜訊為-95.37 dBc/Hz @ 1 MHz。
在第四章實現了低功耗鎖相迴路電路，利用第三章的設計原理，進而設計低 電壓變壓器回授之電壓控制振盪器與低功耗除頻器來達到節省消耗功率之效果。
在整個低功耗鎖相迴路的量測結果顯示，最低總消耗功率為 9.23 mW，鎖定範圍 為 5.408 至 5.568 GHz，鎖定後的相位雜訊為-116.64 dBc/Hz @ 10 MHz。
最後，由實作結果發現頻率皆有往下頻漂之現象，具有固定的趨勢，初步評 估是電磁模擬環境評估不準確，在未來的工作，可藉由此次經驗來修正，達到一 個準確的實驗方式，進一步設計出更好的電路。
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參 考 文 獻
[1] Floyd M. Gardner, Phaselock Techniques, 2-th Ed., New York : Wiley & Sons, 1979.
[2] Roland E. Best, Phase-Locked Loops, 2-th Ed., New York : McGraw-Hill, 1993.
[3] Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuit : theory
and design, New York: IEEE press, 1996.
[4] Mozhgan Mansuri, Dean Liu, and Chih-Kong Ken Yang, “Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops,” IEEE J. Solid-State
Circuits, vol. 37, no. 10, pp. 1331-1334, Oct. 2002.
[5] Woogeun Rhee, “Design of high performance CMOS charge pump in phase locked loop,”
in Proc. IEEE Int. Symp. Circuits and Systems, 1999, pp. 545-548.
[6] Geoger Wegmann, Eric A. Vittoz, and Fouad Rahali, “Charge injection in analog MOS switches,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1091-1097, Dec. 1987.
[7] Behzad Razavi, Design of Analog Integrated Circuits, McGraw-Hill Companies, 1st, Boston: McGraw-Hill, 2001.
[8] Bing J. Sheu and Chenming Hu, “Switch-induced error voltage on a switched capacitor,”
IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 519-525, Aug. 1984.
[9] Mark Van Paemel, “Analysis of a charge-pump PLL: A new model,” IEEE Trans.
Commun., vol. 42, no.7, pp. 2490-2498, July 1994.
[10] Floyd M. Gardner, “Charge-pump phase-lock loops,“ IEEE Trans. Commun., vol. 28, no.
11, pp. 1849-1858, Nov. 1980.
[11] William O. Keese, “An analysis and performance evaluation of a passive filter design techniques for charge pump PLL’s,” National Semiconductor application note 1001, July 2001.
[12] 劉深淵,楊清淵, 鎖相迴路, 滄海書局, 2006.
118
[13] William O. Keese, “An analysis and performance evaluation of a passive filter design techniques for charge pump PLL’s,” National Semiconductor application note 1001, May 1996.
[14] 于宗仁, “應用在 HDTV/ITV 寬頻帶射頻調諧器及 900-MHz/2.4-GHz 無線通訊之 頻率合成器的設計,” 國立成功大學電機工程研究所碩士論文, 民國八十六年。
[15] Ali Hajimiri, and Thomas H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[16] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol.
54, pp. 329-330, Feb. 1966.
[17] H. G. Booker, Energy in Electromagnetism, London, New York: Peter Peregrinus, 1982.
[18] C. Patrick Yue, and S. Simon Wang, “On-chip spiral inductors with patterned ground shields for Si-based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, no.5, pp. 743-752, May 1998.
[19] Alireza Zolfaghari, Andrew Chan, and Behzad Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp.
620-628, Apr. 2001.
[20] Jan Craninckx, and Michiel S. J. Steyaert, “A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol.32, no. 5, pp.
736-744, May 1997.
[21] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE
Trans. Parts, Hybrids, Packag., vol. 10, no.2, pp. 101-109, June 1974.
[22] Chia-Hsin Wu, “CMOS miniature 3D inductors and low noise amplifier,” M.S. thesis, National Taiwan University, June 2001.
[23] Chia-Hsin Wu, Chun-Yi Kuo, and Shen-Iuan Liu, “Selective metal parallel shunting inductor and its VCO application,” in Symp. VLSI Circuits Dig. Technical Papers, June
119
2003, pp. 37-40.
[24] KaChun Kwok, and Howard C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, March 2005.
[25] Pietro Andreani and Sven Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE
J. of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
[26] Theerachet Soorapanth, C. Patrick Yue, Derek K. Shaeffer, Thomas H. Lee, S. Simon Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs” in Symp.
VLSI Circuits Dig. Technical Papers, June 1998, pp. 32-33.
[27] A. R. Kral, “A 2.4GHz frequency synthesizer in 0.6-μm CMOS,” M.S. thesis, University of California Los Angeles, March 1998.
[28] J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design, London, U.K.: Kluwer, 1998.
[29] Marc Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE J. of Solid-State Circuits, vol. 36, no. 7, pp. 1018-1024, July 2001.
[30] Chi-Kai Hsieh, Kun-Yao Kao, and Kun-You Lin, “An ultra-low-power CMOS complementary VCO using three-coil transformer feedback,” in 2009 IEEE Radio
Frequency Integrated Circuits (RFIC) Symp., June 2009, pp. 7-9.
[31] KaChun Kwok, and Howard C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, pp.
652-660, Mar 2005.
[32] B. Jung, and R. Harjani, “A 20GHz VCO with 5GHz tuning range in 0.25-μm SiGe BiCMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp.
178-179.
120
[33] Hsieh-Hung Hsieh, and Liang-Hung Lu, “A low-phase-noise K-band CMOS VCO,”
IEEE Microwave Wireless Compon. Lett., vol. 16, no. 10, pp. 552-554, Oct. 2006.
[34] Jaemo Yang, Choul-Young Kim, Dong-Wook Kim, and Songcheol Hong, “Design of a 24-GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuits Syst.
II, Exp. Briefs, vol. 57, no. 3, pp. 173-177, Mar. 2010.
[35] To-Po Wang, “A K-band low-power colpitts VCO with voltage-to-current positive-feedback network in 0.18-μm CMOS,” IEEE Microwave Wireless Compon.
Lett., vol. 21, no. 4, pp. 218-220, Apr. 2011.
[36] Szu-Ling Liu, Xin-Cheng Tian, Yue Hao, and Albert Chin, “A bias-varied low-power K-band VCO in 90 nm CMOS technology,” IEEE Microwave Wireless Compon. Lett., vol. 22, no. 6, pp. 321-323, June. 2012.
[37] Ian A. Young, Jeffrey K. Greason, and Keng L. Wong, “A PLL clock generator with 5 to 110 MHz of lock rang for microprocessors,” IEEE J. of Solid-State Circuits, vol. 27, pp.
1599-1607, Nov. 1992.
[38] Dejan Mijuskovic, Martin Bayer, Thecla Chomicz, Nitin Garg, Frederick James, Philip McEntarfer, and Jeff Porter, “Cell-based fully integrated CMOS frequency synthesizers,”
IEEE J. of Solid-State Circuits, vol. 27, pp. 271-279, Mar. 1994.
[39] Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer, and Steve Wyatt, “Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and 50ps jitter,” IEEE J.
of Solid-State Circuits, vol. 30, pp. 1723-1732, Nov. 1996.
[40] J.-R. Yuan, and C. Svensson, “Fast CMOS nonbinary divider and counter,” Electronics
Letters, vol. 29, pp. 1222-1223, June 1993.
[41] Jiren Yuan, and Christer Svensson, “High speed CMOS circuit technique,” IEEE J. of
Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
[42] Rola A. Baki, and , Mourad N. El-Gamal, “A new CMOS charge pump for low-voltage
121
(1V) high-speed PLL applications,” in Proceedings of International Symposium on
Circuits and Systems ISCAS’03., vol. 1, pp. 25-28, May 2003.
[43] Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, and Wei Meng Lim, “Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp.72-82, Jan. 2010.
[44] Dong-Jun Yang, and Kenneth K. O, “A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 2, pp 461-468, Feb. 2004.
[45] Ming-Wei Li, Po-Chi Wang, Tzuen-Hsi Huang, and Huey-Ru Chuang, “Low-voltage, wide-locking-range, millimeter-wave divide-by-5 injection-locked frequency dividers,”
IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 679-685, Mar. 2012.
[46] Jae-Hong Chang, Yong-Sik Youn, Mun-Yang Park, and Choong-Ki Kim, “A new 6GHz fully integrated low power low phase noise CMOS LC quadrature VCO,” in 2003 IEEE
Radio Frequency Integrated Circuits (RFIC) Symp., June 2003, pp. 295-298.
[47] Giuseppe De Astis, David Cordeau, Jean-Marie Paillot, and Lucian Dascalescu, “A 5-GHz fully integrated full PMOS low-phase-noise LC VCO,” IEEE J. of Solid-State
Circuits, vol. 40, no. 10, pp. 2087-2091, Oct. 2005.
[48] Dan Shi, Jack East, and Michael P. Flynn, “A compact 5GHz standing-wave resonator-based VCO in 0.13-μm CMOS,” in 2007 IEEE Radio Frequency Integrated
Circuits (RFIC) Symp., June 2007, pp. 591-594.
[49] Kuan-Chung Lu, Fu-Kang Wang, and Tzyy-Sheng Horng, “Ultralow phase noise and wideband CMOS VCO using symmetrical body-bias PMOS varactors,” IEEE
Microwave Wireless Compon. Lett., vol. 23, no. 2, pp. 90-92, Feb. 2013.
[50] Ping Lu, Danfeng Chen, Fan Ye, and Junyan Ren, “A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator,” in 2009 IEEE SOCC Symp.,
122
Sep. 2009, pp. 39-42.
[51] Wei-Hao Chiu, Tai-Shun Chan, and Tsung-Hsien Lin, “A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS,” in Proc. IEEE A-SSCC, Nov. 2007, pp.
456-459.
[52] Chih-Ming Hung, and Kenneth K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. of Solid-State Circuits, vol. 37, no. 4, pp. 521-525, Apr.
2002.
[53] S. Pllerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. of Solid-State Circuits, vol.
39, no. 2, pp. 378-383F, Feb. 2004.
[54] Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu, “A sub-1mW 5.5-GHz PLL with digitally-calibrated ILFD and linearized varactor for low supply voltage operation,” in 2014 IEEE Radio Frequency Integrated
Circuits (RFIC) Symp., June 2014.
[55] Ulrich L. Rohde, Digital PLL Frequency Synthesizers: Theory and Design, Englewood Cliffs, NJ: Prentice-Hall, 1983.
[56] Behzad Razavi, RF Microelectronics, 2-th Ed., NJ : Prentice Hall, 2011.
[57] 施宏達, “應用於 X 頻段之鎖相迴路與頻率合成器之設計與實現,” 國立臺灣師範大 學應用電子科技學系研究所碩士論文, 民國一百零一年。
[58] 黃敏, “具變壓器回授電流重複使用之 Q-band 低雜訊放大器與低功耗ΔΣ分數型頻 率合成器之設計與分析,” 國立臺灣大學電信工程學研究所碩士論文, 民國一百零 一年。
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作 者 簡 歷
作者周健帄，出生於台北市。民國九十九年七月進入國立臺灣師範大學電子 應用科技學系就讀研究所，並加入射頻積體電路實驗室接受蔡政翰教授指導，研 究方向為高速混合信號積體電路與鎖相迴路設計，於民國一百零二年八月完成碩 士學位。
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學 術 成 就
[1] Jeng-Han Tsai, Jian-Ping Chou, “A K-band low-power CMOS transformer-feedback VCO,” in Proc. IEEE Radio and Wireless Symposium (RWS