本論文主要是設計可操作在 X 頻段的鎖相迴路與頻率合成器，藉由國家晶片 中心所提供的 TSMC CMOS 0.18-µm 製程設計驗證。
在第三章設計出了一個低電壓電壓器回授之壓控振盪器，所需要的供應電壓 源僅需 0.65V，消耗功率約為在 11mW 以下。調變範圍為 11.24 GHz 至 12.08 GHz。
相位雜訊為-84.5 dBc/Hz@1 MHz。在第四章介紹了一些常用於高頻的除頻器架構，
並且設計了一個 2bits 即四模態的高頻除頻器。此次設計的除頻器操作頻率可從 7 至 12 GHz，可涵蓋整個 X 頻段。功率消耗約為 19.5 mW。在第五章實現了一個 操作在 X 頻段的鎖相迴路，利用電流再利用技術達到節省功率之效果。在量測結 果顯示整個鎖相迴路總功率消耗為 38.042 mW，鎖定範圍為 10.368 至 11 GHz，
鎖定後的相位雜訊為-94 dBc/Hz @ 100 kHz。在第六章實現了一個頻率合成器主 要是將第三章、第四章與第五章的電路作一個整合，並且設計在低電壓下。此次 頻率合成器具有 2 bits 控制線可以調整頻率，總共可以切換三個頻道。所需的功 率消耗約為 36.76 mW。相位雜訊在 In-band 為-75 dBc/Hz @ 100 kHz，在 out-band 為-120 @ 10 MHz。
最後，在圖 7-1 比較了訊號產生器與鎖相迴路以及頻率合成器的相位雜訊差 異，頻率合成器的部分，是參考圖 6-15 再自行作圖。我們觀察鎖相迴路的相位雜 訊 曲 線 ， 在 可 以 觀 察 到 在 靠 近 迴 路 頻 寬 的 地 方 ， 兩 者 相 位 呈 現 了 約 20log(32)=30.1dB 的差值，可以說明鎖相迴路本身貢獻的相位雜訊可以忽略。在 幾次的實驗結果發現頻率皆有往下頻漂之現象，且有固定的趨勢，初步評估是電 磁模擬環境評估不準確，在未來的工作，可藉由此次經驗來修正，達到一個準確 的實驗方式，進一步設計出更好的電路。
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34 dB 73.1 dB
Proposed PLL in ch5 Proposed synthesizer in ch6
圖 7-1 鎖相迴路與訊號產生器的相位雜訊
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作 者 簡 歷
作者施宏達，出生於新北市。民國九十八年七月進入國立臺灣師範大學電子 應用科技學系就讀研究所，並加入射頻積體電路實驗室接受蔡政翰教授指導，研 究方向為高速混合信號積體電路與鎖相迴路設計，於民國一百零一年八月完成碩 士學位。
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