討論

本實驗利用不同材料的奈米粒子，包括金奈米粒子、金-硫化鎘殼核奈米粒子來當 做記憶體的懸浮閘極。操作在不同的寫入電壓時，對於記憶窗會有不同的變化，是因為 電子受到控制氧化層的吸引，穿隧過穿隧氧化層到達奈米粒子所形成的懸浮閘極後，則 被奈米粒子捕捉住，然後電子便會儲存在奈米粒子和奈米粒子與二氧化矽的接面處。另 外，金在奈米的尺度下會有能階的產生，加上金有很深的功函數，可以捕捉較多的電子，

如圖4-22 所示。而金-硫化鎘殼核奈米粒子之所以會產生較大的記憶窗，主要的原因是 奈米粒子之間會有更多的接面[32]，所以相對的記憶窗就會更大。

在記憶時間方面，室溫和升溫條件下，金-硫化鎘殼核奈米粒子的記憶體皆有很好 的儲存能力，推測是電子被捕捉而儲存在金和硫化鎘的接面，如圖 4-23 所示，而被儲 存的電子要自行離開懸浮閘極，可能有很多的機制，不過跟所經過的厚度有關[33]。因 此金-硫化鎘殼核奈米粒子，對於被捕抓的電子來說，多了一個位能障和硫化鎘所產生 的厚度，將會增加電子離開懸浮閘極層的難度，進而增加記憶時間[34]。

圖4-22、金奈米粒子能帶圖。 

圖4-23、金-硫化鎘殼核奈米粒子能帶圖。 

Tunnel oxide Si

4.1 eV

5.1 eV

4.5 eV 0.9 eV

4.2 eV

Control oxide

Au

Vacuum level

Au

CdS CdS

Au

Al

結論與未來展望

(Summary and Future Work)

5.1 結論

我們可以利用半導體製程技術和自組裝(SAM)奈米粒子的方法，成功的做出奈米粒 子 當 作 懸 浮 閘 極 的 電 容 式 記 憶 體 。 當 懸 浮 閘 極 的 材 料 是 金-硫化鎘殼核奈米粒子 (Au@CdS NPs)，相較於單獨只有金奈米粒子(Au NPs)的記憶體，可以提高記憶窗的變化 (ΔVFB)和增加記憶時間(Retention time)。表 5-1 為對本研究的兩種不同奈米粒子懸浮閘極 所做的總整理表格。

表 5-1、本實驗的奈米粒子記憶體元件總整理。

Au 16 nm

Au@CdS 23 nm Density (No./cm²) 8.21x10¹⁰ 1.25x10¹⁰

Stored charges 6 e^-/No. 67 e^-/No.

Write Vg= 35 V 3 sec Vg= 35 V 3 sec Erase Vg= -35 V 1 sec Vg= -35 V 1 sec

ΔVFB 1 V 2 V

Retention

charge remain 36 % 83 %

最後，我們將本實驗的元件特性與文獻回顧的三篇論文[14][15][16]做比較，在各個 方面雖然不是最好，但是也都有理想的表現，如表5-2。

表 5-2、本實驗元件與文獻回顧之比較。

Floating gate

15 nm charge remain

84 % 75 % 15 % 36 % 83 %

因本實驗所使用的奈米粒子粒徑比一般文獻要大許多，所以會使得奈米粒子的沉積 密度不高，且因粒徑過大在沉積控制氧化層時所需要的物理厚度就相對的變厚許多，故 最後需要操作在十分大的操作電壓下才可運作，在如此大的操作電壓下對元件特性一定 會有很大的負面影響。所以我們若能將金奈米粒子粒徑縮小，進而也可使金-硫化鎘殼 核奈米粒子整體粒徑縮小，如圖5-1 所示，此金-硫化鎘殼核奈米粒子大小大約為 9 nm 與原本的23 nm 相較之下小了許多；若能以此小粒徑的奈米粒子為懸浮閘極來製作電容 記憶體想必可以獲得更好的記憶體特性[35]，而未來我們也可將此奈米粒子沉積於奈米 線上，並且製作成奈米線的懸浮閘極場效應記憶體，藉由閘極電壓的操控，期望能夠看 到更佳的非揮發性記憶體特性。

  圖5-1、粒徑 9 nm 的金-硫化鎘殼核奈米粒子圖。 

參考文獻(References)

[1] R. Bez, E. Camerlengh, A. Modelli, A. Visconti, "Introduction to flash memory," Proc.

IEEE, vol. 91, pp. 489–502, April. 2003.

[2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells—An overview," Proc.

IEEE, vol. 85, pp. 1248–1271, Aug. 1997.

[3] D. Kahng and S. M. Sze, "A floating gate and its application to memory devices," Bell Syst. Tech, J., vol. 46, pp. 629, Sep. 1967.

[4] M. White, D. Adams and J. Bu, "On the go with SONOS," in Proc. IEEE Circuits Designs Conf., 2000, pp. 22–31.

[5] S. Tiwari, F. Rana, H. Hanfi, A. Hartstein, E. F. Crabbe, and K. Chan, "A silicon nanocrystals based memory," Appl. Phys. Lett., vol. 68, pp. 1377–1379, 1996.

[6] F. R. Libsch and M. H. White, "Charge transport and storage of low programming voltage SONOS/MONOS memory devices," Solid State Electron., vol. 33, pp. 105–126, 1990.

[7] M. Kanoun, A. Souifi, T. Baron, and F. Mazen, "Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications,"

Appl. Phys. Lett., vol. 84, pp. 5079–5081, 2004.

[8] C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, "Self-assembly of metal nanocrystal on ultrathin oxide for nonvolatile memory applications," J. Electron. Mater., vol. 34, no. 1, pp. 1–11, Jan. 2005.

[9] S. K. Samanta, W. J. Yoo, G. Samudra, E. S. Tok, L. K. Bera, and N. Balasubramanian,

"Tungsten nanocrystals embedded in high-k materials for memory application," Appl.

Phys. Lett., vol. 87, pp. 113110-3, 2005.

[10] W. R. Chen, T. C. Chang, J. L. Yeh, S. M. Sze, and C. Y. Chang, "Reliability characteristics of NiSi nanocrystals embedded in oxide and nitride layers for nonvolatile memory application," Appl. Phys. Lett., vol. 92, pp. 152114-3, 2008.

nanocrystals embedded in HfO2 gate oxide for nonvolatile nanocrystal flash devices,"

Appl. Phys. Lett., vol. 92, pp. 013512-3, 2008.

[12] B. Liedberg et al., "Self Assembled Monolayers of Alkanethiols on Gold," Laboratory of Applied Physics, Linkoping University.

[13] Z. Liu, C. hungho Lee, V. Narayanan, G. Pei, and E. C. Kan, "Metal Nanocrystal Memories—Part I: Device Design and Fabrication," IEEE Trans. Electron Devices, vol.

49, pp. 1606-1613, Sep. 2002.

[14] C. L Yuan, P. S. Lee, "Enhanced charge storage capability of Ge/GeO2 core/shell nanostructure," Nanotechnology, vol. 19, pp. 355206, 2008.

[15] L. Hai, W. Winkenwerder, L. Yueran, D. Ferrer, D. Shahrjerdi, S. K. Stanley, J. G.

Ekerdt, and S. K. Banerjee, "Core-Shell Germanium-Silicon Nanocrystal Floating Gate for Nonvolatile Memory Applications," IEEE Trans. Electron Devices, vol. 55, pp.

3610-3614, Dec. 2008.

[16] C. C. Wang, J. Y. Tseng, T. B. Wu, L. J. Wu, C. S. Liang, and J. M. Wu, "Charging characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structures,"

J. Appl. Phys., vol. 99, pp. 026102-3, 2006.

[17] S. M. Sze, Semiconductor Devices, Physics and Technology, 2nd, 2002.

[18] R. F. Pierret, Semiconductor Device Fundamentals, 1996.

[19] W. T. Chen, T. T. Yang, and Y. J. Hsu, "Au-CdS Core－Shell Nanocrystals with Controllable Shell Thickness and Photoinduced Charge Separation Property," Chem.

Mater., vol. 20, pp. 7204-7206, 2008.

[20] J. T. Sheu, C. C. Chen, P. C. Huang, Y. K. Lee and M. L. Hsu, "Selective deposition of gold nanoparticles on SiO2/Si nanowires for molecule detection," Jpn. J. Appl. Phys, vol.

44, pp. 2864-2867, 2005.

[21] T. Nakanishi, B. Ohtani, and K. Uosaki, "Fabrication and Characterization of

CdS-Nanoparticle Mono- and Multilayers on a Self-Assembled Monolayer of Alkanedithiols on Gold," J. Phys. Chem. B, vol. 102, pp. 1571-1577, 1998.

[22] W. K. Shih, E. X. Wang, S. Jallepalli, F. Leon, C. M. Maziar, and A. F. Tasch,

"Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide," Solid State Electron., vol. 42, pp. 997-1006, 1998.

[23] R. K. Chanana, K. McDonald, M. Di Ventra, S. T. Pantelides, L. C. Feldman, G. Y.

Chung, C. C. Tin, J. R. Williams, and R. A. Weller, "Fowler–Nordheim hole tunneling in p-SiC/SiO2 structures, " Appl. Phys. Lett., vol. 77, pp. 2560–2562, 2000.

[24] M. Lenzlinger and E. H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown SiO2," J. Appl. Phys., vol. 40, pp. 278-283, 1969.

[25] P. Olivo, J. Sune, and B. Ricco, "Determination of the Si-SiO2 barrier height from the Fowler-Nordheim plot," IEEE Electron Device Lett., vol. 12, pp. 620-622, Feb. 1991.

[26] J. Sanghun, H. Jeong Hee, L. Junghoon, C. Sangmoo, H. Hyunsang, and K. Chungwoo,

"Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode," IEEE Electron Device Lett., vol. 27, pp.

486-488, June. 2006.

[27] P. Ericsson, S. Bengtsson, and J. Skarp, "Properties of AlO films deposited on silicon by atomic layer epitaxy," Microelectron. Eng., vol. 36, pp. 91–94, 1997.

[28] J. Buckley, B. De Salvo, D. Deleruyelle, M. Gely, G. Nicotra, S. Lombardo, J. F.

Damlencourt, P. Hollinger, F. Martin, and S. Deleonibus, "Reduction of fixed charges in atomic layer deposited Al2O3 dielectrics," Microelectronic Eng., vol. 80, pp. 210-213, 2005.

[29] M. Houssa, M. Tuominen, M. Naili, V. Afanas’ev, A. Stesmans, S. Haukka, and M. M.

Heyns, "Trap-assisted tunneling in high permittivity gate dielectric stacks, " J. Appl.

Phys., vol. 87, pp. 8615–8620, 2000.

dielectric for high-temperature applications," Solid State Electron., vol. 49, pp. 716-720, 2005.

[31] M. Specht, M. Stadele, S. Jakschik, and U. Schroder, "Transport mechanisms in atomic-layer-deposited Al2O3 dielectrics," Appl. Phys. Lett., vol. 84, pp. 3076-3078, 2004.

[32] R. M. Ma, L. Dai, and G. G. Qin, "High-performance nano-Schottky diodes and nano-MESFETs made on single CdS nanobelts," Nano Letters, vol. 7, no. 4, pp.

868–873, Apr. 2007.

[33] D. Tsoukalas, P. Dimitrakis, S. Kolliopoulou, and P. Normand, "Recent advances in nanoparticle memories," Mater. Sci. Eng. B, vol. 124-125, pp. 93-101, 2005.

[34] J. Lu, Z. Zuo, Y. Chen, Y. Shi, L. Pu, and Y. Zheng, "Charge storage characteristics in metal-oxide-semiconductor memory structure based on gradual Ge1-xSix/Si heteronanocrystals," Appl. Phys. Lett., vol. 92, pp. 013105-3, 2008.

[35] S. Min and K. Tsu-Jae, "Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance," IEEE Trans. Electron Devices, vol. 50, pp.

1934-1940, Sep, 2003.

[36] S. Maikap, P. J. Tzeng, T. Y. Wang, C. H. Lin, L. S. Lee, J. R. Yang, and M. J. Tsai,

"Memory Characteristics of Atomic-Layer-Deposited High-κ HfAlO Nanocrystal Capacitors," Electrochem. Solid State Lett., vol. 11, pp. K50-K52, 2008.

[37] S. Takagi and A. Toriumi, "New experimental findings on hot carrier transport under velocity saturation regime in Si MOSFET’s," in ZEDM Tech. Dig., 1992, pp. 711-714.