在不同屏蔽比例下，當 VCORE=1V、VI/O=0.56V 量測結果如下:
圖 5.14 VCORE=1V、VI/O=0.56V 不同屏蔽下之眼圖
Shielding% 200Mbps 400Mbps 500Mbps 600Mbps
0% 127.3ps 136.4ps 116.4ps 174ps 0.025UI 0.055UI 0.058UI 0.104UI 50% 109.1ps 181.8ps 130.9ps 192ps
0.022UI 0.072UI 0.065UI 0.115UI 85% 109.1ps 145.5ps 152ps 204ps
0.022UI 0.058UI 0.076UI 0.122UI
100% 127.3ps 145.5ps 269.1ps 180ps
0.025UI 0.058UI 0.135UI 0.108UI 表 5.5 VCORE=1V、VI/O=0.56V 不同屏蔽下之信號抖動
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在不同屏蔽比例下，當 VCORE=1V、VI/O=1V 量測結果如下:
圖 5.15 VCORE=1V、VI/O=1V 不同屏蔽下 0.8G-1.4G 之眼圖
Shielding% 800Mbps 1Gbps 1.2Gbps 1.4Gbps
0% 119.4ps 142.2ps 116.9ps 263.8ps 0.096UI 0.142UI 0.14UI 0.369UI 50% 213.9ps 206.7ps 222.7ps 271.7ps 0.171UI 0.207UI 0.267UI 0.38UI 85% 205.6ps 211.1ps 287.6ps 247.2ps
0.164UI 0.211UI 0.345UI 0.346UI
100% 186.1ps 162.2ps 228.2ps 262.2ps
0.149UI 0.162UI 0.274UI 0.367UI 表 5.6 VCORE=1V、VI/O=1V 不同屏蔽下 0.8G-1.4G 之信號抖動
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圖 5.16 VCORE=1V、VI/O=1V 不同屏蔽下 1.6G-2.2G 之眼圖
Shielding% 1.6Gbps 1.8Gbps 2Gbps 2.2Gbps
0% 202.8ps 254.1ps 270ps 327.6ps 0.324UI 0.457UI 0.54UI 0.721UI 50% 233.3ps 194.9ps 180ps 210.3ps 0.373UI 0.351UI 0.36UI 0.463UI 85% 197.2ps 175.1ps 145.6ps 175.9ps 0.316UI 0.315UI 0.291UI 0.387UI
100% 179.2ps 234.3ps 155.6ps 206.3ps
0.287UI 0.422UI 0.311UI 0.454UI 表 5.7 VCORE=1V、VI/O=1V 不同屏蔽下 1.6G-2.2G 之信號抖動
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我們可以發現當 VCORE操作在 1V 時，匯流排得以傳輸超過 2Gbps 之信號，在 VI/O 為 0.56V 並以較低之資料速率運作時，可以從圖 5.14 看見非常清晰的眼圖，輸出信號 幾乎不受到 ISI 效應與耦合效應之影響。而當我們欲將速度提升至匯流排臨界時，為了 讓偽隨機信號產生器也能在高速下正常運作需將 VI/O提升至 1V，然而因此在輸出端造 成過大的電流而產生嚴重的過衝現象(overshoot)與振鈴(Ringing)，因為在製作印刷電路 板時沒有考量到此問題因而沒有將輸入與輸出埠之電壓分開，若將兩埠分開則可讓輸入 埠接上高電壓以利偽隨機信號產生器運作在高速環境，而輸出埠則可以較低電壓驅動以 避免過大的電流造成過衝與振鈴。我們在各個屏蔽比例下皆可以發現上述現象，而隨著 資料速率的提升可以發現耦合突波影響信號轉態邊緣造成信號抖動之效應隨之加劇，在 接近臨界速度時，85%屏蔽有最佳之抖動抑制如同我們之前所預期，而當資料速率到達 2.4Gbps 時，也僅有 85%屏蔽得以傳送正確資料。
圖 5.17 臨界資料速率下不同屏蔽比例之信號抖動
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Postsim measurement
Bus Only With
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Simulation Measurement
Technology 180nm 90nm 55nm 90nm 90nm
Topology INV Repeater Cap Coupling BT Repeater BT Repeater BT Repeater
Shielding Fully Shielding
Single Channel
Fully Shielding
Partial
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第六章 結論
隨著製程的演進，晶片內匯流排不論是在速度、功耗與面積上都逐漸成為晶片設計 上的瓶頸，本論文之目標為使用最小線間距以降低匯流排之面積，使用拔靴帶式電路作 為中繼器以降低操作電壓達到低功耗又能維持操作速度。使用最小線間距雖能大幅降低 匯流排所占之面積，然而會受到嚴重的耦合效應影響產生大量信號抖動，若使用完全屏 蔽線將信號線彼此隔絕又有嚴重的負載問題，因而我們使用轉態邊緣交錯機制讓耦合所 造成的抖動與其他信號抖動源如 ISI 分開來，再以部分屏蔽加以保護。根據我們文中之 分析，在 90nm 製程中使用最小線距並操作在 0.5V、1Gbps 的狀態下，在 85%屏蔽有最 佳之信號抖動抑制。於論文中我們將各個效應模組化，因此在不同的環境下只要將製程 參數與操作條件帶入我們的模型中即能推算出最佳之屏蔽比例，達到信號抖動與功耗之 平衡點。
在不考慮其他雜訊源的情形下只看耦合與 ISI 效應之影響，在匯流排操作速度瀕臨 極限時能藉由調整到最佳屏蔽比例達到此匯流排所能傳送之最快資料速率，然而反過來 說，屏蔽比例的調整也只有在高速端的應用才得以顯現其優勢，若速度不夠快讓耦合效 應不會干擾到信號轉態，則屏蔽的增加只是徒增負載，造成多餘的功率消耗。且若加入 其他雜訊源在 VDD、地線或是屏蔽線上[24]都有可能主導信號抖動而讓調整屏蔽比例的 效果無法呈現，本文僅針對耦合與 ISI 效應討論而找到適合的屏蔽比例，於實際應用上 需要加上更多雜訊模型才足以在晶片內匯流排上應用。
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