第四章 自動時脈振顫校正之延遲鎖定迴路
4.6 預計量測結果
所提出的可預知頻率具有抖動校正的延遲鎖定迴路，採用的是 0.18 1P6M CMOS 製程，核心面積為 775x845um2 ，圖 4.27 為此晶片的晶片佈局圖。功率消 耗為29m 操作在 400MHz 的時脈下。
CICVInput Buffer
4.27
400MHz 5
個週期。圖4.29 為輸入從 150MHz 到 550MHz 需要鎖定時間的對照總結。可以發 現輸入頻率在接近300MHz 下，所需要的時間較少，是因為初始電壓為 1.0V，所 以需要調整的電壓較少，而隨著頻率越高，所需時間越長，主要是VCDL 在高頻 時的增益較小，頻寬相對就會減少，所需要的時間就比較長。
圖 晶片佈局圖
圖4.28 為輸入和輸出的在 的鎖定情況，從沒鎖定到鎖定總共需要
圖4.28 追鎖情形
200 300 400 500 0
5 10 15
Frequency (MHz)
Lockingme
圖4.29 鎖定時間 V.S 輸入頻率
圖4.30 為輸出頻率為 400MHz 的眼圖比較，在沒有使用假 PFD 的輸出抖動 量為4.18282ps peak-to-peak jitter，780.51fs RMS jitter，而使用一個假 PFD 的情況 下，輸出的抖動量為2.9914ps peak-to-peak jitter，671.54fs RMS jitter。
Ti(cycle)
Without Pseudo PFD With Pseudo PFD 圖4.30 抖動比較(400MHz)
圖4.31 為輸出為 250MHz 到 400MHz 比較使用假 PFD 的沒使用假 PFD 的輸 出抖動表現比較表，可以發現使用假相位偵測器的輸出表現比沒使用的抖動來的 低，其中，jstart external=0，表示 without Pseudo PFD，jstart external=1，表示 with Pseudo PFD。
8
表三:
Specification 圖4.31 抖動比較(250MHz~400MHz)
預計量測的規格為下表三:
Operating Voltage 1.8V
Process 0.18um 1P6M TSMC CMOS Process Min. 150MHz Input frequency range
Max 550MHz
RMS Jitter 671fs@400MHz
Peak to Peak Jitter 2.9ps@400MHz
Lock Time <9 cycles
Power 29 mW@400MHz
2602 280 300 320 340 360 380 400
3 4 5 6 7
Peak to Peak Jitter (ps)
Jstart External = 1 Jstart External = 0
Frequency (MHz)
4.7
132 0MHz
2
Peak-to-Peak Jitter
0.327x0.116mm2 (100MHz)
0.046mm2 0. 5mm2
0.77x0.84mm2 Area(core)
1130 cycles Locking Time
5.25ps@250MHz 3.2ps@130MHz
RMS Jitter
2GHz Operating Min.
range Operating Voltage
[20]
[9]
This Work
15mW@320 mW@13
29mW@400MHz Power
0.07mm
<22 cycles
200 cycles
13 0MHz
2 Peak-to-Peak Jit
0.327x0.116mm2 (100MHz)
0.046mm2
0 5mm2
Are
1130 cycles Locking Time
5.25ps@250MHz .2ps@130MHz
RMS Jitter
2GHz Operating Min.
range Operating Voltage
[20]
[9]
This Work
2mW@13 29mW@400MHz
Power
0.77x0.84mm2
a(core) 0.07mm
<22 cycles
200 cycles
第五章 結論與未來研究方向
本論文中，我們提出可預知頻率含有抖動校正延遲鎖定迴路可以快速鎖 定， 這樣的架構中，有ㄧ個可以預知輸入頻率並改變初始電壓，是這個架構中 最核心的概念，因為我們根據我們的控制電壓的演算法去推斷出每個輸入參考頻 率需要的控制電壓，因此我們的延遲鎖定迴路才能快速的鎖定。接著根據快速鎖 定的架構，我們加上了抖動校正電路，這個電路可以讓我們的延遲鎖定迴路縮小 時脈抖動，在快速鎖定後我們可以讓延遲鎖定迴路的輸出訊號抖動達到一個最小 值。經過量測驗證我們可以確定這些架構是可運作。
遲鎖定迴路，在未來的應用上會越來越廣，但是正因為如此所需要的快速 鎖定和時脈抖動的規格也相對嚴格，因此我們要將整朝延遲鎖定迴路的操作頻率 範圍變廣和輸出訊號的時脈抖動降低為目標。在未來的研究方向，可以增加倍頻 器電路，增加輸出頻率的範圍，並設計可程式化，可以選擇倍頻因子，讓延遲鎖 定迴路的功能更加強大。
在 在
延
參考文獻
[1] Monolithic phase-locked loops and clock recovery circuits: theory and , IEEE press, 1996.
[2] p phase-lock loops,” IEEE Trans. Commun., vol. 28, no.
[3] Phase-locked loops: theory, design and applications, New York:
[4] Cheng, Y. L. Lo “A fast-lock mixed-mode DLL with wide-range operation and IEEE ESSCIRC, Grenoble, France, pp. 189-192, Sep. 2005.
[5] u, and Y. L. Chang “A wide-range DLL-based clock IEEE ICECS., Malta, pp. 798-801, Aug. 2008.
[6] iu, Y., Aibara, Y., Khorramabadi, H.,
– 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital μm CMOS,” IEEE ESSCIRC, Edinburgh, Scotland, UK, pp. 90-94, Sep.
[7] quency Synthesizer Using Two Different
backs,” IEEE International Symposium on Circuits and Systems, Kobe,
[8] en, “A multi-band delay-locked loop with
IEEE ASSCC, Fukuoka, Japan, pp. 441-444,
[9] . Lin, S. I. Liu, “A wide-range delay-locked loop with a fixed IEEE J. Solid-State Circuits, vol. 37, no.8 , pp.
1021-1027, Aug. 2002.
B. Razavi, design
F. M. Gardner, “Charge-pum 13, pp. 1894-1858, Nov. 1980.
R. E. Best, McGraw-Hill, 1998.
K. H.
multiphase outputs,”
K. H. Cheng, C. W. Su, M.J. W
generator with phase error calibration,”
Hoyos, S., Tsang, C.W., Vanderhaegen, J., Ch Nikolic, B., “A 15 MHz
DLL in 0.13 2008.
Chien-Hung Kuo, and Yi-Shun Shih, “A Fre Delay Feed
Japan, pp.2799-2802, May. 2005.
C. H. Kuo, M. F. Lin, and C. H. Ch fast-locked and jitter-bounded features,”
Nov. 2008.
H. H. Chang, J. W
latency of one clock cycle,”
[10] R. Jacob Baker, CMOS Mixed-Signal Circuit design, Wiley Inter-Science, 1998 1] D. H. Wolaver, Phase-locked loop circuit design, Prentice Hall, 1991
2] L. Wang, L. Liu, and H. Chen, “An Implementation of Fast-Locking and Wide-Range
or Spur Suppression,” IEEE Trans. Circuit Syst. II,
lnd, Arpad L. Scholtz, “Jitter Analysis of a Mixed PLL-DLL
able
heng, W. B. Tang, and C. M. Ying, “A Dual-Slop Phase Frequency Detector
laiman, and Zubaida Yusoff, “A Fast-Lock Dual
, and Y. L. Lo, “A Fast-Lock Wide Range Delay-Locked Loop Using
, “A 250-MHz-2-GHz wide-range delay-locked loop,” IEEE [1
[1
11-bit Reversible SAR DLL,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 57, no. 6, pp. 421-425, June. 2010.
[13] F. R. Liao, and S. S. Lu, “A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump f
Exp. Brief, vol. 57, no. 12, pp. 946-950, Dec. 2010.
[14] Md. Sayfullah, B. Ro
Architecture,” IEEE ICECE, Dhaka, Bangladesh, pp. 750-754, Dec. 2008.
[15] K. Chung, J. Koo, S. W. Kim, and C. Kim, “An Anti-Harmonic, Programm DLL-Based Frequency Multiplier for Dynamic Frequency Scaling,” IEEE ASSCC, Jeju, Korea, pp. 276-279, Nov. 2007.
[16] Y. H. Tu, H. H. Chang, C. L. Hung, and K. H. Cheng, “A 3GHz DLL-Based Clock Generator with Stuck Locking Protection,” IEEE ICECS, Athens, pp. 106-109, Dec.
2010 [17] K. H. C
and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop,”
IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 50, no. 11, pp. 892-896, Nov. 2003.
[18] Soh Lip-Kai, Mohd-Shahiman Su
Charge Pump Analog DLL using Improved Phase Frequency Detector,” IEEE VLSI-DAT, Hsinchu, Taiwan, pp. 1-5, Apr. 2007.
[19] K. H. Cheng
Frequency-Range Selector for Multiphase Clock Generator,” IEEE Trans. Circuit Syst.
II, Exp. Brief, vol. 54, no. 7, pp. 561-565, July. 2007.
[20] B. G. Kim, and L. S. Kim
ased frequency
Chang, W. Kim, “ A low-voltage, low power CMOS elay
23, no. 5, pp. 1218-1223, Oct.
frequency
its, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
Transactions on Circuits and System II, vol. 46, pp. 56-62, Jan. 1999.
g a
Delay-Locked Loop with Digital J. Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, Jun. 2005.
[21] T. C. Lee, and K. J. Hsiao, “ The design and analysis of a DLL-b
synthesizer for UWB application, ” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp.
1245-1252, Jun. 2006.
[22] G. Kim, M. K. Kim, B.S.
element, ” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 966-971, July. 1996.
[23] M. G. John and E. L. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization, ” IEEE J. Solid-State Circuits, vol.
1998.
[24] T. H. Su, “Design of a CMOS Delay-Locked Loop based programmable multiplier,” Master Thesis, National Dong-Hwa University, July. 2005.
[25] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-bias techniques,” IEEE J. Solid-State Circu
[26] “Jitter in Clock Sources,” Vectron International.
[27] F. Herzel, and B. Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate,”
IEEE
[28] N. Soo, “Jitter Measurement Technique,” Pericom Application Brief AB36, Nov.
2000.
[29] A. H. Chan, and G. W. Robert, “A Jitter Characterization System Usin Component-Invariant Vernier Delay Line,” IEEE Transactions on VLSI System, vol.12, pp. 79-94, Jan. 2001..
[30] W. M. Lin, K. F. Teng, and S. I. Liu, “A
Background Calibration,” IEEE ASSCC, Taipei, Taiwan, pp. 317-320, Nov. 2009.