Capacitor Multi-Output Mechanism
Various types of SIMO are discussed in chapter 2, from where we can find out and conclude the most appropriate topology to meet the requirement of power supply for cholesteric liquid crystal. Besides, according to our design for energy-saving electronic paper, the proper minimum switch number structure will be used in power delivery path.
Furthermore, additional function of switching capacitor multi-output mechanism is proposed in order to make the structure workable.
3.1 Balanced Dual/Bipolar Outputs Structure
In Chapter 1, we have a conclusion that using boost converter is more efficient comparing with the use of switching capacitor circuits even with larger current driving capability. But it consumes footprint area to generate high enough voltage output using external energy passing transistors and if we want to produce multiple outputs. Thus, the more attractive way to use in my opinion is to apply a SIMO topology having positive and negative outputs which turns uppermost +40V single output and ground into +20V and -20V bipolar outputs. The merit largely lower down the requests of anti-over stress elements and make
energy passing transistors, or power mosfet, fully integrated possible. The idea is the same as SIMO with peak current state-machine control [28] which takes use of a diode attached in the left side of inductor to generate negative voltages. But in different way, instead of using one period divided into several time slots to regulate corresponding outputs in [28], [30] and [37], which have simple structure and minimum cross regulation between various outputs but in the problem of power delivering to energy-hungry channels non-timely if heavy loading in outputs simultaneously. The proposed idea tends to implement the time-multiplexing(TM) control approach [30]-[35], [39], the advantage in which is the immediately gives power to the specific energy-hungry channel. In other words, the power delivering structure is similar to that in [28], but the controlling method is resembling in [40], which means satisfying all output channels in one period. Thus, the ideal topology is shown in Fig. 19, which has the solution to multiple sets of positive and negative outputs, and can be expanded if needed.
Cop,k
L
Iop,k
V
op,kV
INCop,1 Iop,1
V
op,1Con,k Ion,k
V
on,kCon,1 Ion,1
V
on,1Fig. 19. Single Inductor Multiple Sets of Positive/Negative Outputs Converter.
Unfortunately, it’s impossible to use the insane topology since limited footprint area prevents unrestricted extension of bipolar, multiple channels. That is, if the specification of gray level in liquid crystal is 40-level resolution in the region of ±20V, it implies 40 different
output voltages are required and 40 power mos must be integrated into whole chip, which results in above 90% area filling with power delivering elements. Moreover, implementation of time-multiplexing control is difficult in Fig. 19 because of the dilemma in choosing ordered power-distributive control [40] or selecting power first given to the most energy-hungry channel. The property former distributes power orderly but leading to serious chaos of regulating uppermost 40 different voltage with various loading attached in each channel, and the characteristic latter gives power to most energy-hungry channel which means too many different delivering paths happen in each period, easier for instability taken place.
The problem is not caused by the inapplicable of control mechanism, but in the structure of producing 40 output channels which any topology cannot take use of. Does it mean the SIMO structure is not suitable in driving cholesteric liquid crystal, making nonsense in previous discussion? The answer is no.
According to the loading in Gate/Source Driver, pixels of certain row are charged and discharged simultaneously by Gate Driver with ±20V polarity alternation row by row, which implies ±20V are more frequently demanded comparing to others’ voltage levels in Source Driver in the refreshing state. By this way, the final structure adaptive to our power supply system is obviously presented. Driving capability in ±20V voltages are preferably emphasized that SIMO can be adjusted into dual bipolar outputs, and the switching capacitor topology applies to lower driving capability for other output channels. It may be doubted the application of lower efficiency in switching capacitor structure and the responses to the question are not only the preferable methodology comparing to the lowest efficiency in fully use of switching capacitor and comparing to large footprint area in the fully use of SIMO with uppermost to 40 voltage outputs, but also the merits mentioned in next section.
The structure in Fig. 20 is the mixture of boost converter and flyback in Table I, which generates positive and negative voltages.
VG1
Fig. 20. Single Inductor Dual Bipolar High Positive/Negative Outputs (SIDBHO).
Since the SIDBHO Converter structure is applied, as minimum power loss as possible have to be discussed. Power loss of regulators is the combination of the switching loss and the MOSFET’s conduction loss in equation (6). The conduction loss also can classify into boost high-side transistor loss, low-side transistor loss and flyback transistor loss.
Calculating the boost high-side conduction loss is straightforward that the conduction loss is just the I R loss timing the MOSFET’s duty cycle as below: 2 duty ratio for negative voltage channel conduction; V is the on-voltage when diode turns on. D
Calculating the boost high-side conduction loss is straightforward that the conduction loss is just the I R loss timing the MOSFET’s duty cycle as below: 2
conduction loss and switching loss. Conduction loss for boost low-side is given by:
Where (1IOPION) is the rest of one period for boost/flyback inductor charging ratio.
The switching interval begins when the low-side MOSFET driver turns on and begins to supply current power MOSFET’s gate to charge its input capacitance. There is no switching loss until VGS reaches the MOSFET’s VTH therefore power loss equal zero.
When VGS reaches VTH, the input capacitance (CISS) is being charged and ID (the MOSFET’s drain current) is rising linearly until it reaches the current IL which is presumed to be Iout. During this period (t1) the MOSFET is sustaining the entire positive output voltage
Fig. 21. Transient Waveform of VDS and ID Curve in Switching Losses on Power MOSFET.
2
Now, we enter t2. At this point, Iout is flowing through low-side MOSFET, and the VDS
begin to fall. All of the gate current will be going to recharge CGD. During this time the current is constant (at Iout) and the voltage is falling fairly linearly from VOP to 0, therefore:
The switching loss for any given edge is just the power that occurs in each switching interval, multiplied by the duty cycle of the switching interval:
The efficiency of switching regulator is defined as the ratio of the output power consumption and input power supplies, formed as below:
The input power supplies consist of the output consumption (PO), switching loss (PSW), conduction loss (PCOND), quiescent loss (PQ) and other losses (PElse) in parasitic elements.
quiescent loss that was consumed by controllers of switching regulators. The smaller quiescent loss had higher efficiency. A high efficiency results in a high performance extending the energy resource’s life.
In order to make the power loss as small as possible, the conduction loss and switching loss must be lower and lower. Conduction loss has already determined by the sizes of energy passing transistors, that is, power mos, before designing the supply system and it depends on the range of loading condition. However, we can observe the most efficient approach for low switching-loss operation. In Table III, SIDBHO uses the control method of one period divided
2
into two regulating intervals. First input accumulates charge for boost required and stores in inductor and discharge into positive output by inductor’s continuously property. In the second interval input charges for flyback required again and discharge into negative output. By this way, cross regulation can be suppressed down but in the problem of energy to power-hungry channel non-timely. Additional, the switching loss increases due to the higher combination of energy delivery paths.
Table III. Possible Combination for Energy Delivery Path―Type I.
Energy Delivery Path Inductor Current v.s. Time
Charging
In Table IV, SIDBHO takes use of time-multiplexing control scheme. First input accumulates enough charges stored in inductor and discharge into positive output and then into negative output. By this way, the switching loss can be lower down comparing to Table III due to the lower combination of energy delivery paths
Flyback
Table IV. Possible Combination for Energy Delivery Path―Type II.
Energy Delivery Path Inductor Current v.s. Time
Charging
In Table V, the energy delivery approach is similar to Table IV, but in different discharging way which exchanges the order of positive and negative outputs, whose control scheme applies to our system actually. The reason is related to the current sensors by sensing voltage of right terminal in inductor which will be discussed next chapter. By using topology in Table V, it can make the current sensor more accurate and save the anti-error circuits prevent from mistake sensing.
Table VI concludes the control scheme of energy delivery path in Table V. In first path the slope of inductor rises to store charge and at this time SW1 and SW2 work. Secondly, stored charge delivers to negative and inductor slope becomes negative, in which only SW1 changes state. Finally, the rest charges delivers to positive path and inductor waveform goes back to the same position in previous period, and SW1, SW2 and SW3 changes simultaneously.
Table V. Possible Combination for Energy Delivery Path―Type III.
Energy Delivery Path Inductor Current v.s. Time
Charging
Table. VI. The Summary of Inductor Current Path in SIDBHO Converter of Type III.
Path
Function
Sign IL Slope
1 charge
2 flyback
L V VIN OP L
VON