國
立
交
通
大
學
電機與控制工程學系
碩
士
論
文
應用於膽固醇液晶顯示器之單電感雙極性正負高壓
輸出直流直流電源轉換器
Single Inductor Dual/Bipolar High Voltage Outputs
DC-DC Converter Applicable to Cholesteric Liquid
Crystal Display
研究生：范銘彥
指導教授：陳科宏 博士
應用於膽固醇液晶顯示器之單電感雙極性正負高壓輸出直流直流
電源轉換器
Single Inductor Dual/Bipolar High Voltage Outputs DC-DC Converter
Applicable to Cholesteric Liquid Crystal Display
研 究 生：范銘彥 Student：Ming-Yan Fan
指導教授：陳科宏 Advisor：Ke-Horng Chen
國 立 交 通 大 學
電 機 控 制 工 程 學 系
碩 士 論 文
A Thesis
Submitted to Department of Electrical and Control Engineering
College of Electrical Engineering
National Chiao Tung University
in partial Fulfillment of the Requirements
for the Degree of
Master
in
Electrical and Control Engineering
August 2011
Hsinchu, Taiwan, Republic of China
中華民國一百年八月
應用於膽固醇液晶顯示器之單電感雙極性正負高壓輸出直流直流
電源轉換器
研究生：范銘彥 指導教授：陳科宏博士
國立交通大學電控工程研究所碩士班
摘
要
電子設備如今不只是被工作所需要，因應娛樂與互動式介面需求，或是靜態低消耗 功率的電子閱讀器被消費市場所重視且快速發展。需要擁有長時間使用與待機的電子閱 讀器，類紙式閱讀器中的膽固醇液晶顯示器，有別於市面上常見液晶顯示器，具有雙穩 態特性，能夠在不更新閱讀器頁面之時穩定呈現。因此，為了有效使用有限的電池能量， 電源管理系統為晶片系統中非常重要的一環。故本文提出一個運用於切換式電源轉換器 的技術，以期在此切換式電源轉換器的電路中提供穩定之正負電壓驅動膽固醇液晶顯示 器。 本論文所提出的內容，是運用單一輸入與單一外部電感，產生雙極性正負高壓輸出 之直流直流電源轉換器。多組輸出電壓解決傳統切換式升壓電源轉換器所需較多外部元 件，耗費面積的問題；以及解決傳統電荷幫浦電路低驅動能力與低效率之原有結構的缺 陷。本系統亦使用多路複用技術，在單一周期即完成輸出電壓所需能量。 另外提出毋需外部幫助而自我偏壓之電荷幫浦電路，提供驅動訊號以幫助上述之單 電感正負輸入之切換式電源轉換器，也具備較低驅動能力之多組電壓輸出以提供液晶顯 示器灰階顯示。 本論文所提出的方法運用於電流模式直流/直流升壓正負電壓轉換器上，並用台灣 積體電路公司點二五微米製程來實現。實驗結果顯示本論文的方法可在不增加太多額外 的外部元件的前提下，提供多組正負電壓輸出以驅動膽固醇液晶顯示器。
Single Inductor Dual/Bipolar High Voltage Outputs DC-DC Converter
Applicable to Cholesteric Liquid Crystal Display
Student： Ming-Yan Fan Advisor： Dr. Ke-Horng Chen
Department of Electrical and Control Engineering
National Chiao-Tung University
ABSTRACT
In this thesis, a single inductor dual/bipolar high voltage outputs technique is proposed to generate dual outputs to provide driving capability of cholesteric liquid crystal display. Accompany with slope compensation and system compensation, two channel dc-dc converter with positive and negative high voltages can be proved stable. By this technique, it largely reduces area occupation comparing with boost converter producing multiple outputs and resolves the difficulty of efficiency and driving ability in charge pumping supplying system. Besides, the technique uses its unique property and makes it possible to integrate controller and energy delivery elements facing high voltages inside one chip. In addition, the concept of fully balanced self bias switching capacitor structure is proposed to offer specific driver for single inductor structure, and to generate multiple outputs with lower driving ability to apply to gray level implementation, which provides extra two functions to compensate the drawback of lower efficiency in its born defects. The test chip was fabricated by TSMC 0.25μm BCD process, and experimental results show the verification of maximum up to nearly 7V in positive channel and minimum down to near -20V in negative channel.
誌 謝
三年的碩士班生涯，要感謝許多的人在學習這條路上的鼎力幫助。首先要感謝我的 指導教授 陳科宏博士。您不厭其煩的教導、生活經驗的傳承、幽默風趣的言談都深深 的留在學生的心中。除此之外，充分的給予學生挑戰訓練的機會，並給予豐富的資源及 優良的器材，讓實驗室擁有良好的討論風氣與認真的研究氛圍，更是使我成長的原動力。 感謝實驗室的全體夥伴們在研究生活中的互相扶持和鼓勵。感謝裕農學長帶我入門 與教導。特別感謝昱輝學長擔任實驗室的扛壩子與救火隊，沒有你實驗室不會有今日良 好的討論環境與研究氣氛，沒有你許多人包括我在內無法快速跳出在電路的缺陷裡，你 是我至今遇過最具有實力以及良好研究態度的學長。感謝博士班耀沂學長，讓我學到了 許多書本上學不到的知識，更是我聊天訴苦的對象。感謝博士班梓期學長，為實驗室帶 來不一樣的電路領域與觀點，還有歡笑氣氛。感謝同儕士偉開朗活潑的態度，為實驗室 帶來輕鬆詼諧的氣氛。感謝同儕智宇、琮瑛、王為、逸群、典融平日在課業及研究上的 討論與幫忙。 感謝博士班小契學長、昭彰學長、俊賢學長和漢翔學長給予學業上及生活上的諮 詢。感謝已畢業的學長，俊禹學長、銘信學長、士榮學長、緯權學長、柄境學長、友僑 學長、國林學長的照顧與指導。感謝學弟妹冠宇、淳仁、玉萍、以萍、怡婷、雅萍，能 夠與你們共同解決問題，真的很棒。也感謝學弟暐中、嘉隆、大龍、尙祐、俊彥、祐儕、 之樸、柏憲、睿紘、祖為，看到你們就看到實驗室未來的希望。 另外要特別感謝我的女朋友靖淋，一起為未來的目標加油打拼，一起陪著我在實驗 室奮鬥的日子永遠不會忘記。煩躁的生活中互相切磋與互相勉勵，失意時互相加油打 氣，彼此分享快樂難過喜樂與平靜，真的非常謝謝妳。 最後要感謝我的父母和兄姐，因為你們的鼓勵和支持，以及生活上的幫助，使我能 順利完成碩士學業。也正因為你們的鼓舞打氣，成為我的最佳避風港。每當我不如意時， 總能屹立不搖且持續保持積極樂觀的態度，並讓我決定可以繼續深造，挑戰自己，在人 生的道路上昂首闊步的繼續前進，心中的感謝並非三言兩語可以表達形容。 僅以此論文獻給我愛的人及愛我的人，家人們、同學們、朋友們和所有關心我的人。 因為有你們，使本論文豐富不少，謝謝你們。 銘彥 于 處暑 國立交通大學 中華民國一百年八月Contents
Chapter 1 ... 1
Introduction to Cholesteric Liquid Crystal Display(Ch LCD) and Driving System ... 1
1.1 Introduction to Paper-Like Display ... 1
1.2 Background of Cholesteric Liquid Crystal ... 3
1.3 Driving Knowledge of Cholesteric Liquid Crystal Display ... 6
1.3.1 Driving Type (Passive/Active Matrix) ... 6
1.3.2 Driving Signal... 8
1.3.3 Driving System ... 12
1.4 General Power Supply Circuits ... 14
1.4.1 Linear Regulators ... 14
1.4.2 Switching Capacitor Circuits ... 15
1.4.3 Inductor Switching Regulators ... 15
1.5 Design Motivation ... 19
1.6 Thesis Organization ... 20
Chapter 2 ... 21
Introduction to Single Inductor Multi-Output DC-DC Converters ... 21
2.1 Concept ... 21
2.2 Literatures Review ... 22
Chapter 3 ... 27
Balanced Dual/Bipolar Outputs Structure Based on Switch Capacitor Multi-Output Mechanism ... 27
3.1 Balanced Dual/Bipolar Outputs Structure ... 27
3.2 Fully Symmetric Switching Capacitor Based Multi-Output with Self Biasing Mechanism ... 36
Chapter 4 ... 40
Implementation of Proposed SIDBHO DC-DC Converter ... 40
4.1 Current Sensor and Slope Compensation Circuit ... 41
4.2 System Compensation Technique for Boost and Flyback in Current Prograqmming Mode ... 49
4.3 Oscillator and Saw-Tooth Generator ... 53
4.4 Soft Start-up Circuit ... 54
4.5 Reference Voltage Source and Power-On Circuit... 56
Chapter 5 ... 59
Experimental Results ... 59
5.1 Chip Micrograph & Specification Table ... 59
5.2 SIDBHO Converter ... 60
Chapter 6 ... 62
Conclusions and Future Work ... 62
6.1 Conclusions ... 62
6.2 Future Work ... 62
Figure Captions
Fig. 1. Primary Approaches to Electronic Displays... 2
Fig. 2. Structure of Single Cholesteric Liquid Crystal ... 3
Fig. 3. States of Cholesteric Liquid Crystal ... 4
Fig. 4. Cholesteric Texture Transitions ... 5
Fig. 5. Passive Matrix Type ... 7
Fig. 6. Active Matrix Type ... 7
Fig. 7. Response in Bistable Cholesteric Reflective Display to Voltage Pulse ... 9
Fig. 8. Pixel States with Various Driving Voltage ... 11
Fig. 9. Brief Block Diagram of Driving System in Cholesteric liquid Crystal Display ... 12
Fig. 10. The Schematic of A Low Drop-Out Linear Regulator... 14
Fig. 11. The Schematic of A Close Loop Switching Capacitor Voltage Doubler ... 15
Fig. 12. The Simple Architecture of Buck Converter ... 16
Fig. 13. Different Power Management Designs. ... 22
Fig. 14. The State Machine With Hysteretic CCM Control Method ... 23
Fig. 15. The Charge Control Method of SIDO DC-DC Converter ... 23
Fig. 16. The Block Diagram of SIDO DC-DC Converter... 24
Fig. 17. The Synchronous Boost Converter With Freewheeling Current Feedback ... 25
Fig. 18. The Five-Output SIMO Converter With Ordered Power-Distributive Control ... 26
Fig. 19. Single Inductor Multiple Sets of Positive/Negative Outputs Converter ... 28
Fig. 20. Single Inductor Dual Bipolar High Positive/Negative Outputs (SIDBHO). ... 30
Fig. 21. Transient Waveform of VDS and ID Curve in Switching Losses on Power MOSFET 31 Fig. 22. Luminance versus Input Voltage ... 37
Fig. 23. Switching Capacitor Based Multi-Output Mechanism ... 38
Fig. 24. Self Biasing Circuit for Switching Capacitor Structure ... 39
Fig. 25. Block Diagram of SIDBHO DC-DC Converter ... 40
Fig. 26. Transition Points in Use of Signals Vsum, Vepn and Vep ... 41
Fig. 27. Current Sensor Circuits ... 42
Fig. 28. Simulation Results in Current Sensor Circuits ... 44
Fig. 29. Inductor Current at Stable and Unstable Oscillation in Current-Mode Converter ... 44
Fig. 30. The Perturbation Waveform of Inductor Current ... 45
Fig. 31. Current-Mode Control Signal with the Compensation Ramp and Inductor Current .. 47
Fig. 32. Steady-State and Perturbed Inductor Current Waveforms with Compensation ... 47
Fig. 33. Inductor Current with Compensation Ramp in DC-DC Converter ... 49
Fig. 34. The Different Positions of the Compensation Zero at Steady State ... 52
Fig. 35. Oscillator and Saw-Tooth Generator ... 54
Fig. 36. Soft Start-up Circuit. ... 55
Fig. 38. The Schematic of Bandgap Reference Circuit... 57
Fig. 39. Chip Micrograph ... 59
Fig. 40. Measured Waveform of SIDBHO-part I ... 60
Table Captions
Table I. Three Architecture of Switching Regulators ... 17
Table II. Comparisons of the Different Power Supply Circuits ... 18
Table III. Possible Combination for Energy Delivery Path―Type I ... 33
Table IV. Possible Combination for Energy Delivery Path―Type II ... 34
Table V. Possible Combination for Energy Delivery Path―Type III ... 35
Table VI. The Summary of Inductor Current Path in SIDBHO Converter of Type III ... 36
Chapter 1
Introduction to Cholesteric Liquid
Crystal Display(Ch LCD) and Driving
System
1.1 Introduction to Paper-Like Display
In the past, the invention of computer helps people with job requiring detailed computation, and trivial file processing in the office, which seems to be the specific roles of handing serious and tough work. Nowadays the popularity of internet and electronic facilities, people can search faster and get more information. Additional, considering the various requirements such as entertainment and interactive interface with people, electronic facilities are not only the demands from job, but also attached importance to consumer market such as personal digital assistant (PDA), full-motioned video and animation, or static, low power consuming electronic reader. In other words, electronic and information facilities combine work, entertainment and out life, which become the most indispensable part.
Regarding to the requirement of multi-function of electronic facilities, displays, which have directly interaction with eyes, need to coordinate with vision states, and should act corresponding to the change of vision angle, light or environment indoors and outdoors. Recently many corporations and research centers devote to the development of displays. As shown in Fig. 1 [1], followings are the principles of electronic displays: Transmissive displays
work by modulating a source of light, such as a backlight, using an optically active material such as a liquid-crystal mixture. Reflective displays work by modulating ambient light entering the display and reflecting it off of a mirror-like surface. Emissive displays such as OLEDs make use of organic materials to generate light when exposed to a current source.
From last paragraph, we know the paper-like reading displays [2] developed continuously by various companies and research units to overcome the difficulty in reading when facing the change of light outdoors and indoors, moreover, to achieve power conservation and substrate material saving to coincide with the concept of environment protection. Additionally, improvement of readability and transient response time would be expected to consumer market.
Portable paper-like reading displays [2] have various types: Electrophoresis Displays, known as EPD, take use of colorful charged balls to have black and white appearance using external electric field. Electrochromic Displays, known as ECD, use the discoloration material caused by electricity to change the oxidation/reduction states and light absorption spectrum. Twisting Ball Displays, known as TBD, present dark and bright states using a small ball accompanied with dark/bright and different electric properties when external electric field activates. Cholesteric Liquid Crystal Displays, known as Ch-LCD, use the
cholesteric-structure liquid crystal and characteristic of bi-stable to maintain in brightness and darkness.
Take comparison of four display technology above, this thesis would focus on Ch-LCD which has bi-stable, high contrast ratio and high color appearance.
1.2 Background of Cholesteric Liquid
Crystal
Shown in Fig. 2 [3], cholesteric liquid crystal (Ch-LCD), means liquid crystals have similar structure compared with cholesteric spiral structure which can be changed by electricity to present black and white. As shown in Fig. 3 [4], the electricity cross the electrode of display panel would change states of Cholesteric liquid crystal. There’re two stable states in Ch-LCD. One is planar texture state, the other one is focal conic texture.
Fig. 3. Structure of Single Cholesteric Liquid Crystal
In the planar state,where the helical axis is perpendicular to the cell surface, the electric field of the incident light is parallel to the liquid crystal director in some regions, and the light is absorbed by the eyes. The focal conic texture has an optical appearance quite
different from that of the planar texture. When the liquid crystal is in the focal conic texture, which is a polydomain structure, with the helical axis more or less parallel to the cell surface, and incident light is either diffracted or scattered in the forward direction. Whenever liquid crystal is in planar state or focal conic, textures are stabilized at zero electricity field. The homeotropic texture, where the helical structure is unwound with the liquid crystal director perpendicular to the cell surface, the electric field of normal incident light is always perpendicular to the liquid crystal director, and the light passes through the material with little absorption. Homeotropic texture, which has to be activated by continuously electricity field different from planar texture and focal conic texture, usually use to act reset state in display.
Fig. 4. States of Cholesteric Liquid Crystal
After knowing some basic proper nouns about cholesteric liquid crystal, it’s important to have the flow chart of different states transitions which will be related to when and what kind of driving signals should be sent to control the state appearance.
Fig. 4 shows the transitions of cholesteric texture [4] which we can get accompany with the real use of electronic paper (e-paper). When the initial is planar texture state, in which our eyes detect the light reflected by display and interpreted as “bright” or “white”, would like to change to “dark” state in the refreshing e-paper, there are two ways to process: one is to operate with a high voltage to enter into homeotropic texture as the reset state, and then a high voltage off slowly to step into focal conic texture; the other one is directly taking use of
a low voltage, but that would cause liquid crystal change slowly.
On the other side, when the initial is focal conic texture state, in which our eyes cannot detect the light reflected by display because of light scattering and diffracting interior of the liquid crystal, and interpreted as “dark” or “black”, would like to change to “bright” state in the refreshing e-paper, there is only one way to go: to operate with a high voltage to enter into homeotropic texture and soon after a high voltage off quickly to step into planar texture.
1.3 Driving Knowledge of Cholesteric
Liquid Crystal Display
After understanding the development of paper-like display such as cholesteric liquid crystal and its background, the next discussions will focus on the driving knowledge of cholesteric liquid crystal display in order to design corresponding power supply system combining part of driver function. The following paragraphs would be divided into three parts: driving type, driving signal and driving system.
1.3.1 Driving Type (Passive/Active Matrix)
The driving types for liquid crystal can be divided into two parts: passive matrix type and active matrix type in Fig 5 and Fig 6 respectively. Passive matrix type is used in earlier LCD displays, where liquid crystal is in the place between the upper plate and lower plate. Upper and lower plate’s material is metal similar which can be controlled by gate driver signals (G1, G2, … Gn) and source driver signals (S1, S2, … Sn) where liquid crystal in each pixel changes states corresponding to different effective voltage levels driving. A pixel in a passive matrix type must maintain its state without active driving circuitry until it can be refreshed again.
Active matrix is a type of flat panel display, currently the overwhelming choice of notebook computer manufacturers. Comparing to passive matrix type, active matrix contains extra TFTs, known as thin film transistor, to act as switches to determine when and where to control states of liquid crystal. This method provides a much brighter, sharper display than a passive matrix of the same size. The addressing approach is to use gate driver (G1, G2, …Gn)
to control the TFT switches’ timing to decide when and where to change states of each pixel, and source driver (S1, S2, …Sn) send signals from front terminals such as timing controller or
microprocessor to determine which state exactly in specified pixel. From panel driver and power supplier’ point, the advantage of addressing scheme in active matrix is less driving capability of gate driver since controlling TFT switches. On the other side, the drawback is the requirement of extra VCOM driver [5].
G1 G2 Gn S1 S2 Sn G1 G2 Gn S1 S2 Sn
Fig. 6. Passive Matrix Type Fig. 7. Active Matrix Type
Passive matrix addressed displays such as cholesteric liquid crystal display do not need the switch-component of an active matrix display because it has a built-in bistability. Technology for electronic papers also have a form of bistability which are addressed with passive matrix addressing scheme. In this thesis, we use passive matrix as the cholesteric liquid crystal driving type based on its simple and easier addressing scheme.
1.3.2 Driving Signal
From last paragraph we decide which matrix type used in cholesteric liquid crystal display, and in Fig. 4 we know the brief voltage strength–texture states transitional flow chart. This section is based on the knowledge previous and introduces what types of gate and source driving signals would be applied and then the corresponding states in pixel.
The response of a typical bistable cholesteric liquid crystal reflective display to voltage pulses is shown in Fig. 7 [6]. The voltage pulse width was 40 ms in the condition of cell thickness was 5μ m. Curve a is the response of the material initially in the bright, planar texture and if the voltage pulse is below V1, the material remains in the planar texture. When
the voltage pulse in the region between V1 and V2, some liquid crystals remain in the planar
texture, and the others are switched to the focal conic texture, which forms so-called “gray level” in the mixture of planar and focal conic texture. The higher the voltage pulse, the more liquid crystals are switched to the focal conic texture, and the lower the reflectance becomes. When voltage is equal to V2, focal conic texture is acquired, and state goes into completely
dark. When voltage is in the region between V2 and V3, some are switched to the focal conic
texture, and the other are switched to the homeotropic texture during the pulse and relax back to the planar texture after the pulse. The higher the voltage, the more return to the planar texture, and the higher the reflectance becomes. When pulse is higher than V3, the material is
switched to the homeotropic texture during the pulse and relaxes to the planar texture after the pulse.
V1 V2 V4V3 V5
Low High
a
b
Fig. 8. Response in Bistable Cholesteric Reflective Display to Voltage Pulse.
(a) The material is in the planar texture before the use of voltage pulse. (b) The material is in the focal conic texture before the use of voltage pulse.
Curve b is the response of the material initially in the focal conic texture. When the voltage is below V4, the voltage pulse doesn’t make any effect on liquid crystal and material
remains in the dark, focal conic texture. When pulse is between V4 and V5, some are switched
to the homeotropic texture during the pulse and relax to the planar texture after the pulse, and others remain in the focal conic texture, which forms gray level display. The higher the voltage, the more domains are switched to the planar texture, and the higher the reflectance becomes, in other words, gray level is near to bright image. When the voltage is above V5, the
material is switched to the homeotropic texture during the pulse and relaxes to the planar texture after the pulse.
The response of the material depends on the pulse width. For a shorter pulsing time, all the voltages, from V1 to V5, must be shifted to higher values based on the principles of driving
liquid crystal whose two terminals rely on charge accumulation. In other words, pulsing time decreases with increasing voltage levels.
In our design, gate driving signals (G1, G2, …Gn) and source driving signals (S1, S2, …Sn)
Gate Driving Signals Select ( 5 2) 2 1 V V Gk k = 1 ~ n (1) Non-Select Gk0 k = 1 ~ n (2)
Source Driving Signals
Planar ( 5 2) 2 1 V V St t = 1 ~ n (3) Focal conic ( 5 2) 2 1 V V St t = 1 ~ n (4) Gray Level ( 5 2) 2 1 ~ ) 2 5 ( 2 1 V V V V St t = 1 ~ n (5) In Fig. 8(a) and Fig. 8(b), pixels in each row are selected using equation (1), accompany with different source driving signals in equation (3),(4),(5) will generate corresponding effective voltage Vpixel across pixel to charge or discharge and then determine which texture
state shows up. In Fig. 8(a), pixels are selected to write in data with pulse (black solid line) whose voltage level is equal to equation (1), if source driving signals (blue dash line) are using equation (3) that source and gate driving signals have the opposite polarities, the effective voltage Vpixel across pixel, equation (1) minus equation (3), has the equivalence to V5
which would make liquid crystal planar texture and high reflectance display; when voltage strength in equation (4) is applied to source driving signals in Fig. 8(b), source and gate driving signals have the same polarities, and the effective voltage Vpixel across pixel is V2,
much lower than that in Fig. 8(a). In the circumstances, whenever cholesteric liquid crystal is initially in planar or focal conic texture, material has the stability at low reflectance state finally. In the gray level driving condition, whatever voltage level is specified in equation (5) which is in the region between positive polarity in equation (4) and negative polarity in equation (3), Vpixel always situates between V2 and V5, and the variation of reflectance between
lowest and highest position is observed.
In Fig. 8(c) and Fig. 8(d), pixels in each row are non-selected using equation (2), in which gate driving signals are terminated and pixels are inactivated whatever source driving signals are. In this moment, Vpixel in various pixels are always equal or smaller than the
absolute value of equation (3) and (4) whose pulse magnitude is designed smaller than V1 to
keep states unchanged. In other words, when Gk = 0V, whatever type of source driving signals
are, the display remains its appearance since the effective voltage pulse Vpixel across pixel
smaller than V1.
½ (V5+V2)
-½ (V5+V2)
-½ (V5-V2) ½ (V5-V2)
Vpixel = V5, Planar, Bright
½ (V5+V2)
-½ (V5+V2)
-½ (V5-V2) ½ (V5-V2)
Vpixel = V2, Focal Conic , Dark
-½ (V5-V2) ½ (V5-V2) Vpixel ≦ ½(V5-V2) < V1 State unchanged -½ (V5-V2) ½ (V5-V2) Select Non-Select Vpixel ≦ ½(V5-V2) < V1 State unchanged Source Gate (a) (b) (c) (d)
Fig. 9. Pixel States with Various Driving Voltage.
According to the document [7] released from CHUNGHWA PICTURE TUBES, LTD, the breaking point voltages (Vi , i= 1, 2, 3, 4, 5) consistent with that in Fig. 7 is 5V, 10V, 27V,
25V and 30V. When regarding the maximum required voltage of gate driving signals in equation (1), half of the addition V2 to V5 equaling to 20V is applied. Thus, in the next driving
1.3.3 Driving System
After understanding the principle of passive matrix addressing scheme and which type signals are used in gate/source driving, brief block diagram of driving system in Fig. 9 is introduced in this section.
First, Timing Controller receives input signals coming from previous stage such as microprocessor or external stimulus. After decoding in Timing Controller, Xclk , Xstart and Yclk ,
Ystart , Ydata , Ylatch send into Gate and Source Driver separately. Xstart activates when users want
to refresh Ch-LCD panel, and then addressing mechanism starts: G1 is addressed in the first
high enable of Xclk , and pixels in Row1 are activated in the meanwhile G2~ Gn are inactivated
with 0V driven, and S1~ Sn write data in simultaneously; next G2 is addressed in the second
high enable of Xclk , andpixels in Row2 are activated in the meantime S1~ Sn write data in;
rows by rows until the last Rown completes data writing.
Ch-LCD Panel Source Driver (Shift Register + DAC)
G a te D ri ve r Input Timing Controller Ystart Yclk Xclk VSH ≤ +20V VGH (+20V) VGL (- 20V) Power Management VGH/VGL/VSH/VSL GND VSL ≥ -20V Xstart Ydata Ylatch
One important thing worthy to notice is that liquid crystal should be driven by AC signals [8] shown as Fig. 8 in order not to accumulate too many charges on the two terminals of electrode to have bad impacts on physical and chemical characteristics, which generates blurred image, lifetime decreasing and unrecoverable damage on liquid crystal. Based on this concept, same magnitude but with opposite polarity voltage pairs are required. In other words, if VGH = +20V is applied to gate driver and unavoidably VGL = -20V is necessary to achieve polarity alteration on liquid crystal.
In Source Driver part, after Ystart activating, shift register starts to latch Ydata in every
positive edge of Yclk. By this way, serial data array transforms into parallel array stored in
storage register. When data array transformation’s done, enable of Ylatch would sends all data
into DAC and buffer to driving pixels at the same time in vertical or column direction. Accompany with gate driver signals (G1, G2, …Gn) sent out continuously instead of
simultaneously, source driver signals vary with different Gk time slot.
From equation (1), (2) and (3), we know the determination of states in planar texture, focal conic texture and gray level display depends on electrical field strength sent by Source Driver. And it can be found that the highest voltage VSH and lowest voltage VSL required by Source
Driver are in the region between +20V and -20V, which are the same with VGH, VGL
required by Gate Driver generated by Power Management. In other words, Power
Management not only produces typical +20V and -20V, but also multiple voltages inside the
range to make cholesteric liquid crystal in various states. Besides, it’s necessary to have enough driving capability of VGH/VGL/VSH/VSL to satisfy the charging/discharging mechanism and speed. Next part, advantage and drawback in various power sources are discussed and analyzed, furthermore find out the most appropriate solution fit in cholesteric liquid crystal panel driving system.
1.4 Power Source
In this section, we will give a brief introduction to three types of most common regulators, linear regulators, switching capacitor circuits, and Inductor Switching Regulators. Finally, we give a comparison about these three types of regulators.
1.4.1 Linear Regulators
As shown in Fig. 10, the linear regulator [9]-[11] consist of a error amplifier to correct input and output difference, a pass device to supply load current, and a resistive feedback network. The structure is the most compact without complex control circuit, results in smaller chip size and cost. The linear regulator utilizes the feedback network to construct shut negative feedback effect to regulate the output voltage. In this way, this kind of regulator does not need switching clock, so the output noise can be minimized and the output voltage does not exist ripple. Without dual storage components, linear regulator only can be operated in buck operation. The efficiency of linear regulator is about the output voltage dividing input voltage. The highest efficiency occurs that output voltage is near input voltage, i.e. low dropout operation. The supply load ability depends on pass device’s size.
1.4.2 Switching Capacitor Circuits
As shown in Fig. 11, this is a conventional charge pump converter [12]-[15]. During ψ1 phase, the input voltage charges Cs to input voltage. During ψ2 phase, the output equals to input voltage adding voltage across Cs, and gets twice input voltage. With hysteric feedback control, the output is regulated at desired output voltage. The charge pump can also be operated in buck or boost mode, but the efficiency is higher in boost mode. The control circuit is more compact than switching converters, but more complex than linear regulators. Due to switching clock, charge pump also suffers from EMI and noise problems. But these problems are slighter than switching converters’, results from smaller switching frequency in the range of hundreds of Kilo-Hertz. The supply load ability of charge pump is weak, because this depends on capacitor size and switching frequency.
Fig. 11. The Schematic of A Close Loop Switching Capacitor Voltage Doubler.
1.4.3 Inductor Switching Regulators
As shown in Fig. 12, this is a conventional voltage mode switching buck converter [16]-[20]. It compares the output voltage with reference voltage to decide the duty cycle.
When power PMOS conducts, the supply voltage will charge the inductor and capacitor. And in the next time, the power NMOS conducts, so the inductor will be discharged to the capacitor. Due to dual storage components, inductor and capacitor, the switching converter can be operated in buck or boost operation. Generally speaking, the efficiency can be achieved above 90% under heavy load condition. Meanwhile, with higher switching frequency in the range of hundreds of Kilo-Hertz to several Mega-Hertz, the storage components can be designed smaller to save the cost. But the EMI and noise problems become critical. Depended on efficiency requirement, the control circuit is much larger than the other two and the cost is the most. The supply load ability is the largest always in the range about hundreds of milliamps to several amps.
Fig. 12. The Simple Architecture of Buck Converter.
Therefore, the switching regulators can classify into three topologies as functional works. Listed in Table , are buck, boost and flyback converters.
The first regulator called as buck converter because its property that step down the input voltage with respect to output node. The conversion ration M(D) is written as M D( )D. The second regulator called as boost converter because its property that step up the input voltage with respect to output node. The conversion ration M(D) is written as ( ) 1
1
M D
D
.
The last regulator called as flyback converter also named buck-boost converter because its property that step up or down the input voltage with respect to output node. The conversion ratio M(D) is written as ( ) 1 D M D D .
There are many advantages of switching regulators to compare with the linear regulators and charge pumps. Switching regulator had high current efficiency because it used power MOSFET as switches and inductor, capacitors as energy stored elements. When the switched
Table I. Three architecture of switching regulators.
Architecture Conversion Curve
Buck + - Load Vin Vo Co L Control S1 S2 0.2 0.4 0.6 0.8 1.0 D Vi ( ) M D D ( ) M D 0.2 0.4 0.6 0.8 1 0 Boost + - Load Vin Vo Co L Control S2 S1 0.2 0.4 0.6 0.8 1.0 D Vi 1 ( ) 1 M D D ( ) M D 1 2 3 4 5 0 Flyback + - Load Vin Vo Co L Control S1 S2 0.2 0.4 0.6 0.8 1.0 D Vi ( ) M D -5 -4 -3 -2 -1 0 ( ) 1 D M D D
transistor operated in the cutoff region, it had no power dissipation. When the switched transistor operated in triode region, it was nearly a short circuit with little voltage drop across it, and had little power dissipation. Hence, almost power dissipation was spent in output node; high power efficiency could be achieved numerically in the range 80% to 90%.
Switching regulator also had disadvantages. There were more complexity in circuit design than the linear regulators and also required discrete components such as inductor and capacitors. Furthermore, the transition response time and output noise were larger than the linear regulators.
A comparison table between linear regulators, charge pumps and switching regulators are listed in Table II. Switching regulators are the best choices for power supplies driving portable application because of their high efficiency and high power capability.
Table II: Comparisons of the different power supply circuits.
Linear
Regulators
Charge
Pumps
Switching
Regulators
Efficiency Low Medium High
Power Capability Medium Medium High
Footprint area Compact Moderate Large
Cost Low Medium High
Complexity Low Medium High
1.5 Design Motivation
When new types of display such as active matrix organic light emitting diode(AMOLED), electrochromic displays(ECD), electrophoresis displays(EPD), twisting ball displays(TBD), and cholesteric liquid crystal display(Ch-LCD) show up to change generally people’s lives, which are regarded as the next generation industry, various custom-designed panel drivers are designed and manufactured corresponding to different purposed using. Many approaches are proposed [21]-[25] to enhance speed of AMOLED, and some methods even products[26], [27] are brought up to fit panel’s characteristics.
In the previous discussion of general power supply methodology, boost dc-dc converters and switching capacitor circuits are usually applied to Ch-LCD due to their property of promoting voltage to much higher voltage levels, in which the laced of voltage multiple property in linear regulators cannot be used. The advantage of boost converters are obviously high efficiency and high driving capability mentioned in Table II. Thinking to uppermost ten pikofara of the capacitor loading in each cholesteric liquid crystal pixel, when panel’s size becomes larger, capacitance of liquid crystal and the parasitic capacitance, parasitic resistance of bonding wires are sure to cost the speed, conducing the increasing driving capability of the power supply to compensate the transient performance, which would turn into a serious requests if switching capacitor circuits are used. Besides, if the violent approach is utilized to directly enlarge the stored capacitors and area of passing transistors in order to pass more driving current through in switching capacitor structure, there’s too much energy consumes in the on-resistance of every passing transistor and lead to energy and area inefficiency. From this point of view, boost converters are the most qualified candidate for driving liquid crystal.
But considering another side, large voltage difference between two terminals of liquid crystal in Fig. 7 reaches to 40V boost converters have to supply. Under the circumstances,
high sustained, up to 40V across drain and source terminals MOSFETs both in high and low side in the right hand of inductor are unavoidably implemented. If foundry cannot support the integration circuit(IC) resources, it cannot be avoided to use two external MOSFETs to produce one channel and high voltage output, which results to the waste of area. Furthermore, conventional boost converter structure have the characteristics that one input source promote a higher voltage output counting on energy storage elements of an inductor and a capacitor. The property leads to the result that N outputs needed in gray level driving require N sets of energy storage, which doesn’t gain any benefit to achieve numerous voltages by largely consuming area.
Summary of all, switching capacitor circuits can generate any composition of voltage level required when considering gray level display, but have the dilemma of driving capability and power efficiency. Boost dc-dc converters have the merits of high efficiency even with stronger current driving, but growing up in area waste when more outputs are produced.
Therefore, seeking one effective approach in dc-dc converters to satisfy all the demands of high efficient/driving capability and the use of multiple voltages is urgent in cholesteric liquid crystal display. In the following chapters, the optimum solution to the request will be proposed and discussed step by step.
1.6 Thesis Organization
The concept of single inductor multiple output dc-dc converter is organized in chapter 2. Proposed single inductor dual/bipolar positive negative high voltage outputs and self biasing switching capacitor technique are illustrated in chapter 3. Circuit implementation of the proposed technique is described in chapter 4. Experimental results are shown in chapter 5. Finally, the conclusion and future work are made in chapter 6.
Chapter 2
Introduction to Single Inductor
Multi-Outputs DC-DC Converters
2.1 Concept
Today’s field of power management requires high power conversion efficiency, fast line/load transient response, and small volume of the power module. In particular, cell phones, digital cameras, MP3 players, PDAs and portable products require varied voltage levels of power supplies for delivery to different sub-modules in portable products. Thus, there are different designs that provide different voltage levels as shown in Fig. 13. Low dropout (LDO) regulator arrays are one of the designs for different voltage levels as depicted in Fig. 13(a), where the index i is from 1 to n which is used to index the nth output. However, LDO regulator arrays sacrifice power conversion efficiency and greatly reduce battery life. The other solution is illustrated in Fig. 13(b), which combines with different inductive switching converters. The high power conversion efficiency is ensured by the inductive switching converter. However, the large number of inductors occupies the large footprint area and increase fabrication cost.
To achieve microminiaturization and high power conversion efficiency for a power management unit, the single inductor multiple output (SIMO) DC-DC converter has been developed as a suitable solution. The conceptual SIMO DC-DC converter is shown in Fig. 13(c). It only uses one inductor component to generate multiple voltage levels for different
sub-modules in the portable products. The SIMO DC-DC converter not only reduces the footprint area and fabrication cost but also provides highly power conversion efficiency [28]. However, all load current conditions of the multiple output terminals arise in the current level of the inductor. When the load current condition of each output accumulates in the same inductor, the design challenges of the SIMO DC-DC converter such as cross-regulation, power conversion efficiency, system stability, and lack of flexibility of both the buck and boost must be seriously addressed.
VDD1
Large Dropout Voltage VDD2 VDDi LDO n VDDn Switching Converter VBAT LDO i LDO i LDO i Switching Converter 1 VBAT Switching Converter 2 Switching Converter i Switching Converter n VDD1 L1 VDD2 L2 VDDi Li VDDn Ln SIMO Switching Converter VBAT L VDD1 MSW1 VDD2 MSW2 VDDi MSWi VDDn MSWn (a) (b) (c)
Fig. 103. Different power management designs. (a) Use of many LDO regulators. (b) Use of many switching converters. (c) Use of a single-inductor and multiple-output converter.
2.2 Literatures Review
Several topologies and control techniques have been proposed to implement SIMO DC-DC converters [29]-[40]. The SIMO DC-DC converter in [28] uses the hysteretic continuous current mode (CCM) control method and state machine to regulate output voltage. The proposed single-inductor multiple positive/negative output dual-loop DC-DC converter in Fig. 14 operates all output voltage levels (positive and negative) independently on a cycle by cycle base. The control of the individual channels is managed by a state machine (first loop) which takes care of the power stage switching pattern and allows the hysteretic converter to run in a pseudo-continuous current mode (PCCM) to guarantee a high
power conversion capability. The second loop works as a variable peak current control to minimize the inductor current. It will be demonstrated why running with a controlled peak current also yields in a small output voltage ripple and how the state-machine can help to further control the amount of energy delivered into one output channel.
Vgl FBL INPUT COMP’s Vgh Vref FBH Vgh Vref FBM C B A IN P U T R E G IS T E R CLKZ LO G IC S T A T E “ R U LE S ”
BUSY current Peak regulation Power ON/OFF sequence control CLK O U T P U T R E G IS T E R Power stage Previous States L=10uH P1 N1 D3 VGL 0.1uF 2.2uF VIN N3 D2 V GL 0.1uF N2 D1 VBOOT 1uF P2 “RULES” -Channel “Priorities” -Channel sequencing -Invalid State detection -Auto Restart -“Current Burst” control -Power-Save Operation STATES: A, A*, B, C, IDLE IL IPEAK tOFF A B A C A A C A* IDLE B A Inductor Current time
Fig. 14.The State Machine With Hysteretic CCM Control Method [28].
Vg RS RS2=NRS M4a M2a M2b M4b M3a M1a M1b M3b M3c current mirrors Rs3 Cia RSTa Cib RSTb VRs Vib Via L S1 S2 cmp cmp cmp Logic & Buffer S1 S2 S3a S3b IDC EA EA Ve a Ve b V refa Vrefb ba bb Voa Vob Voa Vob Iob Ioa Cb Ca S3a S3b S1 S2 S3a S3b IDC I1 charg e φ1 φ2 φ3 φ4 IL φa φb T 2T current sensor
The work in [29] proposed the charge control method and divided one period to regulate the multiple output voltages. This converter in Fig. 15 required fewer switches than the conventional design. Comparing the simulation results of the non-inverting fly-back converter with that of the buck/boost converter, a 5% improvement in efficiency is achieved with the same load condition. Also, it can be achieved good line and load regulation and minimizes cross-regulation by a pre-defined and fixed freewheeling current level IDC. Owing
to the high freewheeling current level, the power conversion efficiency is greatly decreased in light load condition.
The works in [30] and [37] calculate the cross-regulation problem when one period is divided to regulate the multiple boost output voltages. This converter in [30]-[35] and [39] adopts time-multiplexing (TM) control in providing two independent supply voltages using only off-chip inductor. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The block diagram of SIDO DC-DC converter in [30] is shown in Fig. 16. Furthermore, the work in [37] proposed the PCCM which involves the advantages of CCM and discontinuous conduction mode (DCM).
Sa Sb IL φa S1 D1aT D1bT D2aT D3aT φb D2bT D3b T m1a m2a m1b m2b Qa Qb Vg L S1 Sb Sa Vob Cob Rob Voa Coa Roa
The works in [38] are proposed to monitor freewheeling current as the inductor current control method for dual boost output voltages. Fig. 17 shows the architecture of a synchronous boost converter with freewheeling current feedback. Unlike conventional converters, an error amplifier, rather than the output voltage, is used to regulate the freewheeling current IF. Since freewheeling current does not go negative however, there
should be a DC offset level for the feedback loop to be controlled properly. Slope compensation is not necessary in this control loop, although the switch current, is used for duty cycle control like in a conventional current-programmed mode (CPM) converter. Because there exists a freewheeling period in every cycle, the operation is similar to that of a DCM converter. Sn So Sf o n off off on on off DnT DfT IL Ipk Ifw DoT A1 A1 Ifs Ioffset=Ifs T=1/fs Load increase on off off on o n off DnT DfT IL DoT A2 Ifs T=1/fs A2 Vg L Sf Sn Cok Iok IL IF In So Sok Vok Io Co Vo CMP2 Vref Vn OHI R S Q Q Vnb R S Q Q Vn Vnb fs CMP1 Rs*Ins Ve Cc Ioffset Error amplifier Ifs
The work in [40] orders power distribution of four boost output voltages. The ordered power-distributive control (OPDC) arranges four boost outputs Vo1, Vo2, Vo3, and Vo4 in
descending order of priority to, one by one, share the charge from the inductor in every switching cycle or, more correctly, every power distribution cycle. Its first three output voltages are controlled using comparators and are thus called comparator-controlled output voltages, while the last-ordered output is proportion-integration (P-I) controlled with an error amplifier that is responsible for the converter’s total charge. Therefore, in this OPDC, all of the errors of the preceding comparator-controlled outputs are transferred and accumulated to the last, which is the only one requiring a compensation network in the feedback loop. The architecture of the five-output SIMO converter is shown in Fig. 18.
Vg L Off-chip digital signals Io1 ref1 Programmabl e Reference Generator ref2 ref3 ref4 Vo 1 Scaler 1 ref1 cp1 Vo 2 Scaler 2 ref2 cp2 Vo 3 Scaler 3 ref3 cp3 Vo 4 Scaler 4 ref4 ota Compensatio n network PWM Generator 3rd 2nd 1st Logic Order Control (for OPDC) Dead-time Logic Control & Gate drivers Supplied by Vo1 Vf Vs 1 Vs 2 Vs 3 Vs 4 NMOS SX CN1 CN2 VoN Vs4 S4 Io4 Co4 Vo4 Vs3 S3 Io3 Co3 Vo3 Vs2 S2 Io2 Co2 Vo2 Vs1 S1 Io1 Co1 Vo1 Over-Current detection Peak- and Zero-Inductor-Current
Sensor Sf Vf SX S1 DT D’T D1T S2 D2T S3 D3T S4 Sf D4T DfT IL 0 DCM IL(1) 0 IL(2) 0 IL(3) 0 IL(4) 0
Chapter 3
Balanced Dual/Bipolar Outputs
Structure Based on Switching
Capacitor Multi-Output Mechanism
Various types of SIMO are discussed in chapter 2, from where we can find out and conclude the most appropriate topology to meet the requirement of power supply for cholesteric liquid crystal. Besides, according to our design for energy-saving electronic paper, the proper minimum switch number structure will be used in power delivery path. Furthermore, additional function of switching capacitor multi-output mechanism is proposed in order to make the structure workable.
3.1 Balanced Dual/Bipolar Outputs
Structure
In Chapter 1, we have a conclusion that using boost converter is more efficient comparing with the use of switching capacitor circuits even with larger current driving capability. But it consumes footprint area to generate high enough voltage output using external energy passing transistors and if we want to produce multiple outputs. Thus, the more attractive way to use in my opinion is to apply a SIMO topology having positive and negative outputs which turns uppermost +40V single output and ground into +20V and -20V bipolar outputs. The merit largely lower down the requests of anti-over stress elements and make
energy passing transistors, or power mosfet, fully integrated possible. The idea is the same as SIMO with peak current state-machine control [28] which takes use of a diode attached in the left side of inductor to generate negative voltages. But in different way, instead of using one period divided into several time slots to regulate corresponding outputs in [28], [30] and [37], which have simple structure and minimum cross regulation between various outputs but in the problem of power delivering to energy-hungry channels non-timely if heavy loading in outputs simultaneously. The proposed idea tends to implement the time-multiplexing(TM) control approach [30]-[35], [39], the advantage in which is the immediately gives power to the specific energy-hungry channel. In other words, the power delivering structure is similar to that in [28], but the controlling method is resembling in [40], which means satisfying all output channels in one period. Thus, the ideal topology is shown in Fig. 19, which has the solution to multiple sets of positive and negative outputs, and can be expanded if needed.
Cop,k
L
Iop,kV
op,kV
IN Cop,1 Iop,1V
op,1 Con,k Ion,kV
on,k Con,1 Ion,1V
on,1Fig. 19. Single Inductor Multiple Sets of Positive/Negative Outputs Converter. Unfortunately, it’s impossible to use the insane topology since limited footprint area prevents unrestricted extension of bipolar, multiple channels. That is, if the specification of gray level in liquid crystal is 40-level resolution in the region of ±20V, it implies 40 different
output voltages are required and 40 power mos must be integrated into whole chip, which results in above 90% area filling with power delivering elements. Moreover, implementation of time-multiplexing control is difficult in Fig. 19 because of the dilemma in choosing ordered power-distributive control [40] or selecting power first given to the most energy-hungry channel. The property former distributes power orderly but leading to serious chaos of regulating uppermost 40 different voltage with various loading attached in each channel, and the characteristic latter gives power to most energy-hungry channel which means too many different delivering paths happen in each period, easier for instability taken place. The problem is not caused by the inapplicable of control mechanism, but in the structure of producing 40 output channels which any topology cannot take use of. Does it mean the SIMO structure is not suitable in driving cholesteric liquid crystal, making nonsense in previous discussion? The answer is no.
According to the loading in Gate/Source Driver, pixels of certain row are charged and discharged simultaneously by Gate Driver with ±20V polarity alternation row by row, which implies ±20V are more frequently demanded comparing to others’ voltage levels in Source
Driver in the refreshing state. By this way, the final structure adaptive to our power supply
system is obviously presented. Driving capability in ±20V voltages are preferably emphasized that SIMO can be adjusted into dual bipolar outputs, and the switching capacitor topology applies to lower driving capability for other output channels. It may be doubted the application of lower efficiency in switching capacitor structure and the responses to the question are not only the preferable methodology comparing to the lowest efficiency in fully use of switching capacitor and comparing to large footprint area in the fully use of SIMO with uppermost to 40 voltage outputs, but also the merits mentioned in next section.
The structure in Fig. 20 is the mixture of boost converter and flyback in Table I, which generates positive and negative voltages.
VG1 VG2 VG3
V
on (-20V) D M1 M2 M3 Con Cop Rep Ren Ion L IopV
op (+20V)V
INFig. 20. Single Inductor Dual Bipolar High Positive/Negative Outputs (SIDBHO). Since the SIDBHO Converter structure is applied, as minimum power loss as possible have to be discussed. Power loss of regulators is the combination of the switching loss and the MOSFET’s conduction loss in equation (6). The conduction loss also can classify into boost high-side transistor loss, low-side transistor loss and flyback transistor loss.
Calculating the boost high-side conduction loss is straightforward that the conduction loss is just the I R loss timing the MOSFET’s duty cycle as below: 2
ON D ON
COND
I
V
D
P
2
(7) Where ION is average loading current on negative output (VON) terminal; DON is theduty ratio for negative voltage channel conduction; V is the on-voltage when diode turns on. D
Calculating the boost high-side conduction loss is straightforward that the conduction loss is just the I R loss timing the MOSFET’s duty cycle as below: 2
Where RDS ON( ) is at the maximum operation MOSFET junction temperature (TJ MAX( ));
OP
I is average loading current on positive output (VOP) terminal; D is the duty ratio for OP
boost positive voltage channel conduction. Boost low-side loss are also comprised of
MOSFET SW COND
P
P
P
(6) OP ON DS OP CONDI
R
D
P
2 ( )
(8)conduction loss and switching loss. Conduction loss for boost low-side is given by:
Where (1IOPION) is the rest of one period for boost/flyback inductor charging ratio.
The switching interval begins when the low-side MOSFET driver turns on and begins to supply current power MOSFET’s gate to charge its input capacitance. There is no switching loss until VGS reaches the MOSFET’s VTH therefore power loss equal zero.
When VGS reaches VTH, the input capacitance (CISS) is being charged and ID (the
MOSFET’s drain current) is rising linearly until it reaches the current IL which is presumed to
be Iout. During this period (t1) the MOSFET is sustaining the entire positive output voltage
across it, the energy in MOSFET during t1 is:
)
1
(
) ( 2 OP ON ON DS OUT CONDI
R
D
D
P
(9) OP ON ON ON OP ON OP OP OUTD
D
D
I
D
D
D
I
I
1
1
(10)Fig. 21. Transient Waveform of VDS and ID Curve in Switching Losses on Power MOSFET.
2
)
(
1 1 OP OP tt
V
I
P
(11)Now, we enter t2. At this point, Iout is flowing through low-side MOSFET, and the VDS
begin to fall. All of the gate current will be going to recharge CGD. During this time the
current is constant (at Iout) and the voltage is falling fairly linearly from VOP to 0, therefore:
The switching loss for any given edge is just the power that occurs in each switching interval, multiplied by the duty cycle of the switching interval:
The efficiency of switching regulator is defined as the ratio of the output power consumption and input power supplies, formed as below:
The input power supplies consist of the output consumption (PO), switching loss (PSW),
conduction loss (PCOND), quiescent loss (PQ) and other losses (PElse) in parasitic elements.
quiescent loss that was consumed by controllers of switching regulators. The smaller quiescent loss had higher efficiency. A high efficiency results in a high performance extending the energy resource’s life.
In order to make the power loss as small as possible, the conduction loss and switching loss must be lower and lower. Conduction loss has already determined by the sizes of energy passing transistors, that is, power mos, before designing the supply system and it depends on the range of loading condition. However, we can observe the most efficient approach for low switching-loss operation. In Table III, SIDBHO uses the control method of one period divided
2
)
(
2 2 OP OP tI
V
t
P
(12) S OP OP SWV
I
t
t
F
P
(
)
2
)
(
2 1 (133)100%
O O ff in O Q SW COND ElseP
P
E
P
P
P
P
P
P
(14)into two regulating intervals. First input accumulates charge for boost required and stores in inductor and discharge into positive output by inductor’s continuously property. In the second interval input charges for flyback required again and discharge into negative output. By this way, cross regulation can be suppressed down but in the problem of energy to power-hungry channel non-timely. Additional, the switching loss increases due to the higher combination of energy delivery paths.
Table III. Possible Combination for Energy Delivery Path―Type I.
Energy Delivery Path Inductor Current v.s. Time
Charging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period Boost Discharging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period Charging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period
In Table IV, SIDBHO takes use of time-multiplexing control scheme. First input accumulates enough charges stored in inductor and discharge into positive output and then into negative output. By this way, the switching loss can be lower down comparing to Table III due to the lower combination of energy delivery paths
Flyback Discharging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period
Table IV. Possible Combination for Energy Delivery Path―Type II.
Energy Delivery Path Inductor Current v.s. Time
Charging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period Boost Discharging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period Flyback Discharging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period
In Table V, the energy delivery approach is similar to Table IV, but in different discharging way which exchanges the order of positive and negative outputs, whose control scheme applies to our system actually. The reason is related to the current sensors by sensing voltage of right terminal in inductor which will be discussed next chapter. By using topology in Table V, it can make the current sensor more accurate and save the anti-error circuits prevent from mistake sensing.
Table VI concludes the control scheme of energy delivery path in Table V. In first path the slope of inductor rises to store charge and at this time SW1 and SW2 work. Secondly,
stored charge delivers to negative and inductor slope becomes negative, in which only SW1 changes state. Finally, the rest charges delivers to positive path and inductor waveform goes back to the same position in previous period, and SW1, SW2 and SW3 changes simultaneously.
Table V. Possible Combination for Energy Delivery Path―Type III.
Energy Delivery Path Inductor Current v.s. Time
Charging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period Flyback Discharging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period Boost Discharging Von Con Cop Ion L Iop Vop VIN SW1 SW2 SW3 IL Time One Period
Table. VI. The Summary of Inductor Current Path in SIDBHO Converter of Type III.
Path
FunctionSign
I
LSlope
1
charge
2
flyback
L V VIN OP L VON3
boost
RelationV
OP&V
ONV
ONSwitches SW1 & SW2
SW1
L VINSW1, SW2 & SW3
V
OP 3.2 Fully Symmetric Switching
Capacitor Based Multi-Output with
Self Biasing Mechanism
Since single inductor multiple sets of positive/negative output converter is not suitable to produce because of the complexity in control scheme, multiple outputs are still required to act as gray-level driving in liquid crystal. In conventional approach, gray level voltages are the responsible of gamma reference voltage circuits, which are formed by several resistors to composite different ratio structure in order to produce a correction curve to compensate the non-linearity for lamination versus input voltage[8]in Fig 22. The approach is unavoidable to design corresponding set of voltages in easier and straight way, but it is obviously an inefficient method to use resistor-string since there’s a leakage path all the time even when no refreshing is required in displays.
