Fig. 40 shows the measurement result of SIDBHO Converter, positive output voltage reaches nearly 5V and negative voltage nearly -9.2V in clock frequency of 770kHz.
V
OP=
4.957VV
ON=
-9.17VC
LKI
LKHz770
Fig. 40. Measured Waveform of SIDBHO-part I.
It presents the stability of high duty conversion ratio in dc dc converter combing boost and flyback function. In Fig. 41 shows the minimum voltage of negative channel achieves nearly -20V but in the problem of not high enough in positive channel since the leakage current happens in switching capacitor structure which supports the driver in boost part.
Instead, in the implementation environment, diode parallel to M3 in the high-side of boost converter in Fig. 25 is applied to verify the function of close-loop, but to avoid the over-stress happens, the highest positive output voltage can only arrive nearly 7V in maximum tolerance range.
V
OP= 6.883V
V
ON=
-18.98V
C
LKI L
KHz720
Fig. 41. Measured Waveform of SIDBHO-part II.
5.3 Self Bias Switching Capacitor
As mentioned in last paragraph, leakage problem happens because the wrong biasing on body terminal of each transistor, and it causes large leakage due to the wrong voltage bias in Deep N-well and NBL. Fortunately the power of this structure separates from others to make SIDBHO workable, but still have an impact on it.
Chapter 6
Conclusions and Future Work
6.1 Conclusions
In this work, a single inductor dual/bipolar high voltage outputs technique is proposed.
Accompany with slope compensation and Type II system compensation, two channel positive and negative high voltages dc dc converter can be proved stable. Owing to the proposed technique, it largely reduces area occupation comparing to conventional boost converter and solves the dilemma of efficiency and driving capability in charge pumping power supplies.
Moreover, SIDBHO uses its characteristics and makes it possible to integrate controller and energy delivery elements facing high voltages inside chip. In addition, the concept of fully balanced self biasing switching capacitor topology is proposed to not only provide specific driver for SIDBHO structure, but to generate multiple outputs with lower driving ability to apply to gray level implementation. The test chip was fabricated by TSMC 0.25μm BCD process, and experimental results show the verification of maximum up to nearly 7V in positive channel and minimum down to near -20V in negative channel.
6.2 Future Work
Proposed fully balanced self biasing switching capacitor topology support for SIDBHO and gray level driving, which overcomes the cost of charge pump and provide two extra functions and makes itself valuable. But there’s problem in designing circuits when circuits’
implementation. In the future works, to fix the leakage problem is the most urgent mission.
After completely verifying SIDBHO and fully balanced self biasing switching capacitor structure, highly integration of the circuits mentioned above and multi-channel Gate/Source Driver with timing control inputs is the next step to process, which finally reaches all-in-one integrated circuit to provide next generation product of paper-like cholesteric liquid crystal display.
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