Fully Symmetric Switching Capacitor Based Multi-Output with Self Biasing

2 flyback

L V V_IN _OP L

V_ON

3 boost

Relation VOP &VON VON

Switches SW1 & SW2 SW1 L

V_IN

SW1, SW2 & SW3 VOP



3.2 Fully Symmetric Switching

Capacitor Based Multi-Output with Self Biasing Mechanism

Since single inductor multiple sets of positive/negative output converter is not suitable to produce because of the complexity in control scheme, multiple outputs are still required to act as gray-level driving in liquid crystal. In conventional approach, gray level voltages are the responsible of gamma reference voltage circuits, which are formed by several resistors to composite different ratio structure in order to produce a correction curve to compensate the non-linearity for lamination versus input voltage [8] in Fig 22. The approach is unavoidable to design corresponding set of voltages in easier and straight way, but it is obviously an inefficient method to use resistor-string since there’s a leakage path all the time even when no refreshing is required in displays.

Fig. 22. Luminance versus Input Voltage.

To solve the inefficient problem and the function to drive gray level in liquid crystal, the proposed switching capacitor based multi-output structure is shown in Fig. 23. The mechanism uses charge pump concept and fully symmetric structure, where uses C2, C3, C5, C₆ pumped by same amplitude, non-overlapping clock-like with opposite phase signals of V_IN and VINB , and put charges from higher voltage level side to the middle lower side of C1, C4

and C₇, thus, the stable voltages of V₁, V₂ and V₃ are generated. The concept is similar to the situation that water containers in the two sides fill in enough water in the middle containers and keep constant level of water same with the amplitude of V_IN and V_INB. When V_INB is low and VIN’s high, charges from VIN flow into C1 by Msw1 to keep V1 constant and refill the voltage level of C₃ by M_sw4 in 1^st floor; at 2^nd floor, V_c1 is pumped by V_IN and pass charges through Msw5 and Msw8 to increase level in C4 and C6 respectively. In the opposite phase, when V_IN is low and V_INB’s high, charges from VINB flow into C₁ by M_sw2 to keep V₁ constant as previous action and refill the voltage level of C2 by Msw3 in 1^st floor; at 2^nd floor, Vc2 is pumped by VINB and pass charges through Msw6 and Msw7 to increase level in C4 and C5

respectively. It cannot deny the switching capacitor topology has lower efficiency, too, but it does better comparing to resistor-string structure. Moreover, the topology can be expanded by module with dash line in Fig. 23 to fit the more requests of voltages.

Driver

Driver Driver

Driver Driver

Driver Driver

Driver Driver Driver

VIN

V

V

V

VINB VIN

V^b3 V^b4 Vb7 Vb8

V^b1 V^b2

Vb5 Vb6

Msw1 Msw2

Msw3 M^sw4

M^sw5 Msw6

M^sw7 M^sw8

Msw9 M^sw10

Vb4 Vb3

V^b8 V^b7

C¹

C2 C3

C⁴

C5 C6

C7

Module

Fig. 23. Switching Capacitor Based Multi-Output Mechanism.

The bias of each passing transistor for switching capacitor would be trivial and careful in order not to make any mosfet take the risk of over-stress problem [41], [42]. To achieve every element stress free, and to overcome bias problem, Fig. 24 shows the self biasing circuit to compatible with topology in Fig. 23. The bias voltages of Vb₁~Vb₈ are clock-like signals to drive passing transistors that charge pumping procedure works appropriately, which are generated by switching capacitor structure itself and from modules of inverter in self biasing circuit. On the contrary, the bias V1, V2 in modules of inverter are implemented by stable voltages of switching capacitor topology, and finally forms cross-bias fully symmetric switching capacitor circuit.

V

Fig. 24. Self Biasing Circuit for Switching Capacitor Structure.

The last but not least, it’s applicable for Power Mosfet of M3 in boosting positive side in Fig. 20. Because the process used in this thesis is TSMC 0.25μ m BCD, which provides mosfet having the properties of maximum 5V in VGS. It means the minimum level of VG3 should not be lower than 15V since voltage in source terminal of M3 is 20V, whose power mosf’s driver should not simply be composed by normal level shifter and inverter-chain, instead, switching capacitor topology can be applied as special level shifter which shift digital signals from logic with core voltage into high level, which avoid over-stress problem.

In summary, the invention of switching capacitor topology and its self basing circuit provides the special driver for boosting high side PowerMos M3 in Fig. 20, and make a cross-bias balanced circuits, requiring no external bias voltage, and finally, another type of gamma reference generator having driving capability for gray level.

Chapter 4

Implementation of Proposed SIDBHO DC-DC Converter

The overall topology is shown as Fig. 25, which contains power delivery elements such as transistors(M1,M2,M3), external inductor(L), diode(DON), and energy storage capacitors(COP, C_ON) we discussed previous chapter, and contains two error amplifiers(EA_P, EA_N) in two closed loops to regulate positive and negative voltages which use compensation technique we implement. Current programming mode is applied in this structure which uses current sensor producing sensing signal Vs and addition of sawtooth generator, playing the role of slope compensation producing signal V_slope, to prevent unstable.

Vref

Fig. 25. Block Diagram of SIDBHO DC-DC Converter

Besides, peak circuit takes the summary of error signals (Vep, Ven) of two channels to decide how much energy, V_epn, is required in each period, and then takes use of comparator (Comp) and signals of Vsum, Vepn and Vep in Fig. 26 to determine the transition points of inductor current in Fig. 26. When the transitions happen in comparators, the digital control signals V_CP, VCE and VCLK from clock generator would enter Logic & Deadtime part, then pass through Level Shift, Switching Capacitor and charge the working condition of energy delivery elements.

In this chapter, the detailed working principles of circuits will be discussed.

Vsum

One Period Time

Vepn

Vep

Fig. 26. Transition Points in Use of Signals Vsum, Vepn and Vep

4.1 Current Sensor and Slope