The CRL consists of a VCO, prescaler, divider, multiphase generator, phase selector (MUX), and a gating phase frequency detector (GPFD). Incorporating with the data demodulator, it recovers carrier frequency and clock from the QPSK modulation signal for frequency down conversion and data demodulation.
The LC tank VCO at 2.4 GHz with 3 bits coarse tuning is introduced in section 3.2.
Based on complementary architecture, it improves phase noise performance thanks to a more symmetric output waveform [36]. Also, it benefits from two fold negative conductance for power saving. Here both C3 and C4 are accumulation mode MOS varactors for fine frequency tuning. In addition, SC1 and SC2 are added in parallel for coarse tuning to cope with PVT variations.
Fig. 6.13 shows the schematic of charge pump and loop filter. To alleviate reference spurs induced by current mismatch of up and down currents (IU2 and ID2) due to channel length modulation, a regulated current feedback loop consisted of A2, IU1, and ID1 is employed.
Here IU1 and ID1 are replica of IU2 and ID2, and the pumping currents can track each other by adjusting the gate voltage of the current source [34].
The divider chain in the feedback path of the CRL is composed of a high speed divided-by-19 divider followed by a divided-by-8 divider, as shown in Fig. 6.14. The divided-by-19 divider is composed of a 4/5 prescaler, a divide-by-4 divider and a control logic. Fig. 6.14(b) shows the timing diagram. To reduce power dissipation as well as propagation delay, TSPC flip-flops with embedded NAND gate are incorporated in the dividers, as shown in Fig. 6.14(c). The synchronous divided-by-8 divider also performs as a multi-phase generator. Fig. 6.14(a) shows the circuit schematic. The 8 phases output signals are then utilized to capture QPSK symbols, and one of them is passed to the GPFD for phase tracking.
6.4. Experimental Result
The single-chip crystal-less wireless receiver has been fabricated in a 0.18 μm CMOS process, and powered by a 1.8 V supply. A single channel experimental prototype is implemented to demonstrate the concept. The power dissipation for the RF/analog front-end (LNA + mixer + post amplifier + channel selection filter) is about 9.6mW, while the data demodulator and CRL consumes about 10.8mW. Fig. 6.15 shows the chip photograph. The
108 Chapter 6. Reference-Less Frequency Synthesizer and Receiver chip size is 1.75 x 1.55 mm2, and is mounted on a printed circuit board for measurement.
The rejection of out band interferers mainly relies on external band selection filter. By using TA0532A SAW filter, the out band interferers are suppressed 40 dB. Besides, a 6th order low pass filter is implemented incorporating post amplifier for channel selection in this design. To emulate the RF signal at the transmitter side, a 1Mbps QPSK modulated signal is generated by Tekronix AWG7000B arbitrary waveform generator, and then up converted to 2.416 GHz through R&S SMIQ03 signal generator. For BER < 10-3, the in band signal to interference ration must be higher than 15 dB to maintain phase locked. With -65dBm input signal at the receiver side, the measured recovered spectrum is shown in Fig. 6.16. It can be seen that the closest spurs are at 1MHz offset corresponding to the data rate.
The measured settling time of the CRL is shown in Fig. 6.17, the duration of preamble should be larger than 90 μsec for frequency synchronization. The proposed architecture can extract the carrier frequency directly from the RF signal without resort to extra resonator based reference. The measured phase noise performance is shown in Fig. 6.18, which is about -111 dBc/Hz at 1 MHz offset. The phase noise performance is also comparable to RF frequency synthesizer with crystal reference. Fig. 6.19 shows the eye diagram of demodulated I/Q signal. It reveals clear eye for the data demodulation as well.
Table 6.2 shows the performance benchmark for 2.4 GHz wireless sensor applications.
Compared to the prior art, the proposed receiver accomplishes frequency down conversion as well as OQPSK demodulation without extra ADCs, on chip reference, and additional carrier recovery loop in the base band. It achieves much higher data rate (1Mbps) in contrast to the prior art. Besides, the measured phase noise is also comparable to RF frequency synthesizer with crystal reference.
6.5. Conclusion
This paper proposes a novel single chip wireless QPSK receiver without resort to extra resonator based reference. In contrast to conventional architectures, the receiver recovers the RF carrier frequency directly from the incident radio signal for frequency down conversion.
Meanwhile, it accomplishes phase and frequency tracking as well as QPSK demodulation simultaneously. Thus no additional base-band ADCs or timing recovery loop are required in this receiver. It greatly improves the system integration level.
Fig. 6.15 Chip microphotograph
Fig. 6.16 Measured recover spectrum of the local oscillator
110 Chapter 6. Reference-Less Frequency Synthesizer and Receiver
Fig. 6.17 Measured frequency locking time
Fig. 6.18 Measured phase noise performance
Fig. 6.19 Eye diagram for demodulated signal
112 Chapter 6. Reference-Less Frequency Synthesizer and Receiver
Table 6.2 Performance benchmark for 2.4 GHz receiver for WSN
Reference This work [115] [116] [117]
components required RF filter
RF filter (a) BAW DCO locked by a crystal-based ADPLL
(b) LNA and mixer only (c) LNA, mixer and LO (d) excludes crystal oscillator (e) receiver mode
Conclusion
7.1. Summary
In this dissertation, the CMOS circuit techniques for frequency synthesis and wireless communication is presented. To conquer the encountered challenges in contemporary communication systems, the frequency synthesis techniques and circuit skills are developed.
First, a 38/114 GHz switched-mode standing wave oscillator (SWO) capable of synchronous locking is presented. The SWO is capable of generating fundamental and triple output frequency in the sub-THz range by nature. Different excitation modes are enabled by digital control without resort to other high speed circuits or edge combiner. Additionally, incorporating mode enabling and sub-harmonic injection locking, the proposed SWO can be synchronized to external reference to further improve phase noise performance. The close-in phase noise is improved by about 18 dB with the proposed scheme when the SWO is with synchronous lock. The experimental prototype was fabricated using a low leakage 65 nm 1P9M triple-well CMOS technology.
Secondly, a 10 GHz LC-type DCO achieves a 75 KHz frequency resolution with 10 GHz operating frequency for an all-digital PLL (ADPLL). The frequency resolution can be further enhanced by employing high speed dithering. The measured phase noise is -102dBc/Hz at 1MHz offset, while consumes 3.9 mW from a 1V power supply. Besides, a 40 GHz 11% tuning range DCO using the proposed linear variable inductor (VID) is introduced for 60 GHz UWB system. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in 90-nm digital CMOS process, the DCO is capable of covering frequency range from 37.6 to 43.4 GHz.
Thirdly, a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system using direct frequency synthesis technique is demonstrated. Based on a single phase locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers
114 Chapter 7. Conclusion are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. From experimental results, the image spurs are suppressed below -45dBc and improved by more than 22 dB incorporating with I/Q calibration using 0.18-μm CMOS technology.
Finally, a 2.4 GHz reference-less single chip wireless receiver for 1Mbps QPSK demodulation is implemented for demonstration. The receiver accomplishes LO carrier recovery and data demodulation directly from the RF received signal without a need of resonator-based reference source and extra baseband ADC. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip using 0.18-μm CMOS technology, the total power consumption is 20.4mW.
The proposed techniques in this dissertation can conquer the challenges coming from modern communication systems. Additionally, more circuit techniques can be inspired for future development.