LC-Type Digitally Controlled Oscillator
4.3. High Resolution Digitally Controlled Oscillator
In this section, the design and implementation of the digitally controlled oscillator (DCO) will be illustrated. The implemented block diagram of the DCO system is shown in Fig. 4.19.
The DCO receives a 25-bits wide control word CDCO[24:0] from the loop filter without a sign bit and delivers a differential signal with frequency around 10 GHz to the buffers.
Due to its relatively good phase noise, ease of implementation, and better rejection of common-mode additive noise, a cross-coupled inductance capacitance (LC) oscillator is chosen. The MOS implementation of a LC oscillator can be classified into two major categories: NMOS only structure and complementary structure which uses both NMOS and PMOS in a cross-coupled fashion to compensate the power loss in LC resonator.
It has been reported that there are several reasons for the superiority of the complementary cross-coupled pair over the NMOS-only structure. The complementary structure offers higher transconductance for a given current, which results in faster switching of the cross-coupled differential pair. It also offers better symmetry of the waveform, which results in a smaller 1/f3 noise corner. Nevertheless, the single NMOS-only topology is chosen over the complementary one to enable the oscillators to operate in the current limited region for low voltage supply.
Since the tail current can contribute as much as 15% to the total phase noise [47] when the MOS of the current source is operated in saturation region, a PMOSs operated in linear region is used as biasing to reduce its noise contribution. The nominal bias current is 3mA and an on-chip regulator is introduced to stabilize the bias condition.
54 Chapter 4. LC-Type DCO
4.3.1. Circuit Implementation
In this section, the design and implementation of the digitally controlled oscillator (DCO) will be illustrated. The implemented block diagram of the DCO system is shown in Fig. 4.19.
The DCO receives a 25-bits wide control word CDCO[24:0] from the loop filter without the sign bit and delivers a differential signal with frequency around 10GHz to the buffers.
Due to its relatively good phase noise, ease of implementation, and better rejection of Fig. 4.19 Diagram of DCO system
common-mode additive noise, the cross-coupled inductance capacitance (LC) oscillator is chosen. The MOS implementation of the LC oscillator can be classified into two major categories: NMOS only structure and complementary structure which uses both NMOS and PMOS in a cross-coupled fashion to compensate the power loss in LC resonator.
Since the tail current can contribute as much as 15% to the total phase noise [47] when the MOS of the current source is operated in saturation region, a PMOSs operated in linear region is used as biasing to reduce its noise contribution. The nominal bias current is 3mA and an on-chip regulator is introduced to stabilize the bias condition.
In an ideal LC oscillator, the frequency fOSC and the period TOSC of the oscillation are a nonlinear function of the tank capacitance Ctank. In the traditional voltage controlled LC oscillator, frequency tuning is achieved by controlling the effective tank capacitance with an analog control signal. The variable capacitor is typically implemented by the diode or the MOS varactor which has a non-linear relationship between the capacitance and the tuning voltage.
In the concept of the digital tuning, the oscillation frequency is made to be proportional to the input digital control word CDCO. To achieve digital tuning of the oscillation frequency, the varactor can be used but only two voltage levels are applied. In the implemented DCO system, NMOS with control signal short to drain and source is used as the inversion type varactor and each varactor operates in either high or low capacitance state. When the source voltage, drain voltage drop to zero and the gate potential VG is 1V, an inversion layer exists below the gate oxide region. This structure behaves likes a parallel-plate capacitor with only a silicon oxide dielectric in between and the capacitance of the varactor is relatively high. As the control signal rise to 1V, the depletion region is formed under the gate oxide and a small overlap capacitance dominants the capacitance of the varactor. By this way, the digital tuning can be achieved by controlling the amount of the MOS varactors in high capacitance state.
Today’s advanced CMOS process makes it possible to create extremely small varactors which have controllable capacitance in the order of hundreds of atto farads and results in relatively fine frequency resolution in the digital tuning LC oscillator. Fig. 4.20 shows the simulation result of the C-V curve of a NMOS varactor with gate voltage tie to 1V.
56 Chapter 4. LC-Type DCO
In order to lower the area and the parasitic capacitance of the varactor bank, the whole bank is divided into 3 different weighted sub-banks. As shown in Fig. 4.19, the varactor bank incorporating 7-bits binary-weighted coarse tuning to cover the required tuning range and a 10-bits unity weighted fine tuning to ensure linearity. The layout of the coarse tuning bank is constructed with 128 identical NMOS varactors and each control signal drives different number of the varactors. For instance, CDCO[17] drives a single varactor while CDCO[18]
controls a pair of the varactors.
In order to optimize the area usage, the 10-bit fine tuning bank is organized in the matrix of the elementary cells. As shown in Fig. 4.21, each cell includes a local decoder and two varactors with shorted drain and source terminals. The gate terminals of the 1024 cells are shorted together and AC coupled to the tank through a series capacitor Cs, which reduces the equivalent capacitance and enhanced the frequency resolution. Depending on the control Fig. 4.20 Gate capacitance v.s. drain and source voltage, VC, of a simulated NMOS varactor with L=0.08μm, W=0.16μm
Fig. 4.21 The schematic of fine tune cell
0 0.2 0.4 0.6 0.8 1
signals R, L and C, each cell can be turned either into high capacitance mode or low capacitance mode. The condition for the cell to behaves as a large capacitance is
( )
[i] [i] [j] 1 L + R C⋅ =
(4.22)
The binary weighted control code CDCO[17:8] is first converted to thermometer code and then the tuning information R[31:0], L[31:0] and C[31:0] are latched to avoid glitches. The local logic implemented in the cells decode the row and column information in such a way that each odd row is filled up from column 1 to column 32, while each even row is filled up from column 32 back to column 1 of the matrix. The serpentine topology [46] and the dummy cells on the boundary of the matrix ensure good matching between the elements in adjoining rows.
The structure of the ΣΔ modulator is illustrated in Fig. 4.23. It is implemented as digital second-order MASH-type architecture [47] which can be conveniently realized in digital
(a) (b)
Fig. 4.22 (a) The layout view and (b) the EM simulation results of the inductor
Z-1
Fig. 4.23 Diagram of the 2nd MASH-II order ΣΔ modulator
0 5 10 15 20
58 Chapter 4. LC-Type DCO
domain by cell based design flow. Its output is fed to three ΣΔ cells which have the same structure as the fine tuning cell with R[i] and L[i] tie to 1 and 0, respectively. Table 4.1 reports the tuning characteristics of the DCO.
Due to the lack of the inductor models in the process development kit (PDK) of this 90nm mixed-mode CMOS process, a symmetric inductor coil with center tap is drawn and an EM simulation is taken to extract the characteristic of the inductor. In order to improve the quality factor, the top copper metal layer with 810nm thickness is used to construct the inductor. Also, the inductor layout is covered by some dummy-block layers to prevent automatic metal pattern filling procedure which is now standard in advance sub-micron process. Fig. 4.22 shows the layout view, the inductance and the quality factor of the symmetric inductor. It can be seen from simulation results that the inductor has a quality factor of about 9 around 10 GHz.
4.3.2. Experimental Result
To evaluate the performance of the implemented DCO, the DCO is applied to an ADPLL. The chip microphotograph is shown in Fig. 4.24. The DCO core area occupies about 480μm × 250μm of area and is mounted on a FR-4 PCB to verify. The DCO tuning curves have been characterized in open loop configuration by externally setting a 25 bits digital input code via the multiplexer in front of the DCO. The output frequency measurement is performed by the Agilent E4448A spectrum analyzer with internal frequency counter function. Since measuring the whole tuning curve of the DCO entails the programming of Fig. 4.24 Chip microphotograph of the DCO applied to an ADPLL
225=33554432 different DCO control codes which consumes extremely long time to complete the measurement, the tuning curve of each varactor bank was characterized individually while keeping other control code of other banks unchanged. The measurement process has been automatized using a PC with a GPIB IEEE488.1 interface card and a MATLAB program. The MATLAB routine generates sequentially all the input codes and provides the serial control data to the chip via the parallel port. After each code has been sent, the output frequency of the synthesizer is measured by the Agilent E4448A, and the result is communicated back through the GPIB interface to the PC. The results are automatically stores to the memory of the PC and can be post-processed by MATLAB. Higher accuracy of the measurement is obtained by averaging up to 100 measurement results with the same DCO control code.
Linearity is important to have a value of KDCO which is independent from the operating point of the BBPLL on the tuning curve. Nevertheless, more important is the uniformity of Fig. 4.25 Measured DCO frequency versus control code of coarse tuning bank CDCO[24:18]
Fig. 4.26 Measured DCO frequency versus control code of fine tuning bank CDCO[17:8]
60 Chapter 4. LC-Type DCO
the minimum frequency step, or, in other terms, the differential nonlinearity (DNL) of the tuning curve. Too large nonlinearity may cause unstable condition in locking process and would worsen the output jitter and spurious tone performance. Under nominal conditions, the maximum (CDCO=33554432) and minimum (CDCO=0) output frequency measured are 10.2GHz and 9.78GHz, respectively. Fig. 4.25 shows the measured tuning characteristics of the DCO versus different control codes of coarse tuning bank CDCO[24:18] while the control code of fine tuning bank CDCO[17:8] and ΣΔ bank CDCO[7:0] are set to 2’b1000000000 and 2’b10000000, respectively. Due to the digital tuning scheme which does not suffer from the highly nonlinear frequency versus voltage characteristics and low voltage headroom, it can be seen that the tuning curves are much more linear than the typical tuning curves of a conventional LC VCO. The measured average frequency step is 2.8MHz per LSB of coarse tuning bank and the DNL is less than 0.42LSB. Fig. 4.26 reports the DCO output frequency with the frequency step as functions of control code of the unity-weighted fine tuning bank CDCO[24:18]. The average frequency step measured is about 75kHz per LSB of fine tuning bank. The frequency resolution is further enhanced to 250 Hz per LSB by employing high speed dithering through an 8-bit ΣΔ second order modulator.
Fig. 4.27 shows the phase noise plot of the free running DCO at 9.98GHz, measured with Agilent E4448A spectrum analyzer with phase noise personality. The measurement results are (-102dBc/Hz at 1MHz offset) agreed with the simulation counterpart where the phase noise at 1MHz offset is about -103 dBc/Hz. Better phase noise value is obtained for higher output frequency where the varactor banks are in low capacitance mode. When the Fig. 4.27 Measured DCO frequency step versus control code of ΣΔ bank CDCO[17:8]
Fig. 4.27 Measure open loop phase noise from 9.98GHz carrier
0 200 400 600 800 1000
MOS in the varactor bank enters inversion mode, the energy loss due to the effective resistance of channel and metal connections would increase. Thus, the quality factor of the LC tank reaches its minimum value at high capacitance state when the output frequency is lowest.
4.4. Conclusion
The design considerations of a DCO including quantization and dithering noise are introduced. The proposed linear variable inductor consists of a transformer and a reconfigurable transmission line. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. The 6-bits DCO can operate at 40 GHz with 14% frequency tuning range. It is capable of covering frequency range from 37.6 to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10-MHz offset, and the output power is -11 dBm. On the other hand, a 10 GHz LC-type DCO achieves a 75 KHz frequency resolution with 10 GHz operating frequency. The frequency resolution is further enhanced to 250 Hz per LSB by employing high speed dithering through an 8-bit MASH-11 ΔΣ modulator.
The measured phase noise is -102dBc/Hz at 1MHz offset, while consumes 3.9 mW from a 1V power supply.