This section presents several suggestions for future investigations into the techniques for frequency synthesis.
Higher oscillation mode can obtain a multiple output frequency but lower the output power in penalty. The antenna array techniques that could be employed to combine the electromagnetic power in space domain, which has no limitation of voltage head room, to enhance output power. The on chip antenna arrays have low area in sub-THz frequency range, or a flip chip and MEMs techniques could achieve low cost and high antenna gain.
The frequency resolution of DCO for 60 GHz UWB is an issue. A finer frequency resolution could be achieved by high speed dithering through ΔΣ modulator. A transmission line with programmable phase velocity may be another solution.
In chapter 5, the chip size is large. It can be improved by using more advance CMOS technology instead of 0.18 μm CMOS process.
To be more robust against in band interferers in reference-less receiver, a more elaborate channel selection filter can be adopted. Besides, the noise outside of a channel can also be filtered out to improved sensitivity level.
Bibliography
[1] MultiBand OFDM Physical Layer Proposal for IEEE 802.1 Task Group 3a, MultiBand OFDM Alliance SIG, Sep. 14, 2004.
[2] S. M. Rezaul Hasan, “Analysis and Design of a Multistage CMOS Band-Pass Low-Noise Preamplifier for Ultrawideband RF Receiver,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 4, pp. 638–651, Apr. 2010.
[3] Amin Q. Safarian, Ahmad Yazdi, and Payam Heydari, “Design and Analysis of an Ultrawide-Band Distributed CMOS Mixer,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 5, pp. 618–629, May 2005.
[4] Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, and Gin-Kou Ma, “A 14-band Frequency Synthesizer for MB-OFDM UWB Application.” in IEEE Int.
Solid-State Circuits Conf. Dig.Tech. Papers, Feb. 2006, pp. 126–127.
[5] Jri Lee, “A 3-8GHz Fast-Hopping Frequency Synthesizer in 0.18-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 566–573, Mar. 2006.
[6] Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi, and Seong Su Park, “A 6.3-9GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications,”
IEEE J. Solid-State Circuits, vol.40, no. 8, pp.1671-1679, Aug. 2005.
[7] Raf Roovers, Domine M. W. Leenaerts, Jos Bergervoet, Kundur S. Harish, Remco C. H.
van de Beek, Gerard van der Weide, Helen Waite, Yifeng Zhang, Sudhir Aggarwal, and Charles Razzell, “An Interference-Robust Receiver for Ultra-Wideband Radio in SiGe BiCMOS Technology,” IEEE J. Solid-State Circuits, vol.40, no. 12, pp.2563-2572, Dec.
2005.
[8] B. Razavi, Turgut Aytur, Fei-Ran Yang, Ran-Hong Yan, Han-Chang Kang, Cheng-Chung Hsu, and Chao-Cheng Lee, “A 0.13-μm CMOS UWB Transceiver,” in IEEE Int. Solid-State Circuits Conf. Dig.Tech. Papers, Feb. 2005, pp. 216–217.
[9] Remco C. H. van de Beek, Domine M. W. Leenaerts, and Gerard van der Weide, “A Fast-Hopping Single-PLL 3-Band MB-OFDM UWB Synthesizer,” IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1522–1529, July. 2006.
[10] Chien-Chih Lin and Chorng-Kuang Wang, “A Regenerative Semi-Dynamic Frequency Divider for Mode-1 MB-OFDM UWB Hopping Carrier Generation,” in IEEE Int.
Solid-State Circuits Conf. Dig.Tech. Papers, Feb. 2005, pp. 206–207.
[11] Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, Jose Silva-Martinez, and
116 Bibliography Edgar Sanchez-Sinencio, “An 11-Band 3–10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 935–948, April. 2007.
[12] Chao-Shiun Wang, Wei-Chang Li, Chomg-Kung Wang, Homg-Yuan Shih, and Tzu-Yi Yang, “A 3-10 GHz Full-Band Single VCO Agile Switching Frequency Generator for MB-OFDM UWB,” IEEE Int. Asian Solid-State Circuits Conf. Dig.Tech. Papers, Nov.
2007, pp. 75–78
[13] Tanaka A., Okada H., Kodama H., and Ishikawa H, "A 1.1V 3.1-to-9.5GHz MB-OFDM UWB Transceiver in 90nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig.Tech.
Papers, Feb. 2006, pp. 398–407.
[14] Werther, O., Cavin, M., Schneider, A., Renninger, R., Liang, B., Bu, L., Jin, Y., and Marcincavage, J., “A Fully Integrated 14-Band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF Transceiver,” in IEEE Int. Solid-State Circuits Conf. Dig.Tech. Papers, Feb.
2008, pp. 122–601.
[15] Hui Zheng and Howard C. Luong, “A 1.5 V 3.1 GHz–8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp.
1250–1260, June. 2007.
[16] Tai-You Lu and Wei-Zen Chen, “A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System,” in IEEE Int. Solid-State Circuits Conf. Dig.Tech. Papers, Feb. 2008, pp. 126–601.
[17] Chinmaya Mishra, Alberto Valdes-Garcia, Faramarz Bahmani, Anuj Batra, Edgar Sánchez-Sinencio, and Jose Silva-Martinez, “Frequency planning and synthesizer architectures for multiband OFDM UWB radios,” IEEE Trans. Microwave Theory and Tech., vol. 53, no. 12, pp. 3744–3756, Dec. 2005.
[18] Tai-You Lu and Wei-Zen Chen, “A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System,” to be published in IEEE Trans.
Very Large Scale Integration Systems.
[19] Jui-Yuan Yu, Ching-Che Chung, Hsuan-Yu Liu, Yu-Wei Lin, Wan-Chun Liao, Terng-Yin Hsu, and Chen-Yi Lee, “A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling” in Symp. VLSI Circuit Dig. Tech. Papers, Jun. 2006, pp. 236–237.
[20] Wolfgang Eberle, Jan Tubbax, Boris Come, Stephane Donnay, Hugo De Man, and Georges Gielen, “OFDM-WLAN receiver performance improvement using digital
2002, pp. 111–114.
[21] Chun-Huat Heng, Manoj Gupta, Sang-Hoon Lee, David Kang, and Bang-Sup Song, “A CMOS TV Tuner/Demodulator IC With Digital Image Rejection,” in IEEE J. Solid-State Circuits, pp. 2525-2535,Dec. 2005.
[22] Srenik S. Metha, David Weber, Manolis Terrovitis, Keith Onodera, Michael P. Mack, Brian J. Kaczynski, Hirad Samavati, Steve Hung-Min Jen, William Weimin Si, MeeLan Lee, Kalwant Singh, Sunetra Mendis, Paul J. Husted, Ning Zhang, Bill McFarland, David K. Su, Teresa H. Meng, and Bruce A. Wooley, “An 802.11g WLAN SoC,” in IEEE J. Solid-State Circuits, pp. 2483-2491, Dec. 2005.
[23] Iason Vassiliou, Kostis Vavelidis, Theodore Georgantas, Sofoklis Plevrids, Nikos Haralabidis, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Yiannis Kokolakis, Panagiotis Merakos, Jacques C. Rudell, Akira Yamanaka, Stamatis Bouras, and Ilias Bouras, “A Single-Chip Digitally Calibrated 5.15-5.825-GHz 0.18-μm CMOS Transceiver for 802.11a Wireless LAN,” in IEEE J. Solid-State Circuits, pp. 2221-2231, Dec. 2003.
[24] Lawrence Der and Behzad Razavi, “A 2-GHz CMOS Image-Reject Receiver With LMS Calibration,” in IEEE J. Solid-State Circuits, pp. 167-175, Feb. 2003.
[25] Mostafa A. I. Elmala and Sherif H. K. Embabi, “Calibration of Phase and Gain Mismatches in Weaver Image-Reject Receiver,” in IEEE J. Solid-State Circuits, pp.
283-289, Feb. 2004.
[26] Jan Crols and Michel S. J. Steyaert, “A Single-Chip 900 MHz CMOS Receiver Front-End with a High Performance Low-IF Topology,” in IEEE J. Solid-State Circuits, pp. 1483-1492, Dec. 1995.
[27] Sung Ho Wang, Joonho Gil, Ickjin Kwon, Hyung Ki Ahn, Hyungcheol Shin, and Beomsup Kim, “A 5-GHz Band I/Q Clock Generator using a Self-Calibration Technique”
in Proc. European Solid-State Circuit Conf., Sept. 2002, pp. 807–810.
[28] Ari Yakov Valero-Lopez, Sung Tae Moon, and Edgar Sanchez-Sinencio,
“Self-Calibrated Quadrature Generator for WLAN Multistandard Frequency Synthesizer,”
in IEEE J. Solid-State Circuits, pp. 1031-1041, May 2006.
[29] Raymond Montemayor and Behzad Razavi, “A Self-Calibrating 900-MHz CMOS Image-Reject Receiver” in Proc. European Solid-State Circuit Conf., Sept. 2000, pp.
320–323.
[30] M. Faulkner, T. Mattsson and W. Yates, “Automatic adjustment of quadrature modulators,” Electron. Lett., vol. 27, no. 3, pp. 214–216, Jan. 1991.
118 Bibliography [31] Sherif Galal and Behzad Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator
Driver in 0.18-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.
2138–2146, Dec. 2003.
[32] Wei-Zen Chen and Da-Shin Lin, “A 90-dBΩ 10-Gb/s Optical Receiver Analog Front-End in 0.18-μm CMOS Technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 3, pp. 358–365, Mar. 2007.
[33] Zhenghao Lu, Kiat Seng Yeo, Wei Meng Lim, Manh Anh Do, and Chirn Chye Boon,
“Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 3, pp. 461–472, Mar.
2010.
[34] Thomas H. Lee, Hirad Samavati and Hamid R. Rategh, “5-GHz CMOS Wireless LANs,”
IEEE Trans. Microwave Theory and Tech., vol. 50, no. 1, pp. 268–280, Jan. 2002.
[35] Wei-Zen Chen and Dai-Yuan Yu, “A Dual-band Four-mode Delta Sigma Frequency Synthesizer,“ Radio Frequency Integrated Circuit Symposium, pp. 206-207, June., 2006.
[36] Woogeun Rhee, Bang-Sup Song, and Akbar Ali, “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order ΔΣ Modulator,” in IEEE J. Solid-State Circuits, pp. 1453-1460, Oct. 2000.
[37] Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, and Bram Nauta, “A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-Band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 392–393, 393a.
[38] Behzad Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE J.
Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sept. 2004.
[39] Chung-Yu Wu, Min-Chiao Chen, and Yi-Kai Lo, “A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18μm CMOS for V-Band Applications,”
IEEE Trans. Microwave Theory and Tech., vol. 57, no. 7, pp. 1629–1636, July 2009.
[40] Song-Yu Yang, Wei-Zen Chen, and Tai-You Lu, “A 7.1 mW, 10 GHz all digital frequency synthesizer with dynamically reconfigured digital loop filter in 90-nm CMOS technology,” IEEE J. of Solid-State Circuits, vol. 45, no. 3, pp. 578–586, Mar. 2010.
[41] R. B. Staszewski, Chih-Ming Hung, K. Maggio, J. Wallberg, D. Leipold, and P. T.
Balsara, "All-digital phase-domain TX frequency synthesizer for bluetooth radios in 0.13μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 272.
Mobile Phones," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp.2469-2482, Dec. 2005.
[43] Hsiang-Hui Chang, Ping-Ying Wang, J.-H. C. Zhan et al., "A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2008, pp. 200-606.
[44] Chun-Ming Hsu, M. Z. Straayer, and M. H. Perrott, "A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," in IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, Feb. 2008, pp. 340-617.
[45] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, Wiley-Interscience, 2006.
[46] N. Da Dalt, E. Thaller, P. Gregorius, and L. Gazsi, "A Compact Triple-Band Low-Jitter Digital LC PLL with Programmable Coil in 130-nm CMOS," IEEE J. of Solid-State Circuits, vol. 40, pp. 1482-1490, 2005.
[47] R. B. Staszewski, Chih-Ming Hung, N. Barton, Meng-Chang Lee, and D. Leipold, "A Digitally Controlled Oscillator in a 90 nm Digital CMOS Process for Mobile Phones,"
IEEE J. of Solid-State Circuits, vol. 40, pp. 2203-2211, 2005.
[48] Imran Bashir, Robert B. Staszewski, Oren Eliezer, Bhaskar Banerjee, and Poras T.
Balsara ”A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter,” IEEE J. Solid-State Circuit, vol.46, no. 2, pp. 403-415, Feb. 2011.
[49] Jingcheng Zhang, Khurram Waheed, and Robert B. Staszewski, “A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter,” IEEE Trans.
Circuit Syst. I, vol. 57, no. 8, pp. 2010–2207, Aug. 2010.
[50] Robert B. Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Ken Maggio, and Poras T. Balsara, “SoC With an Integrated DSP and a 2.4-GHz RF Transmitter,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 13, no. 11, pp. 1253–1265, Nov. 2005.
[51] Ali Hajimiri and Thomas H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE J. of Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[52] Ali Hajimiri and Thomas H. Lee, “Design Issues in CMOS Differential LC Oscillators,”
IEEE J. of Solid-State Circuits, vol. 34, no. 5, pp. 717–724, Feb. 1999.
[53] Emad Hegazi, Henrik Sjoland, and Asad A. Abidi, “A Filtering Technique to Lower LC Oscillator Phase Noise,” IEEE J. of Solid-State Circuits, vol. 36, no. 12, pp.
120 Bibliography 1921–1930, Dec. 2001.
[54] Pietro Andreani and Ali Fard, "A 2.3GHz LC-Tank CMOS VCO with Optimal Phase Noise Performance," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2006, pp. 691-700.
[55] Swaminathan Sankaran, Chuying Mao, Eunyoung Seok, Dongha Shim, Changhua Cao, Ruonan Han, Daniel J. Arenas, David B. Tanner, Stephen Hill, Chih-Ming Hung, and Kenneth K. O. "Towards Terahertz Operation of CMOS," ISSCC Dig. Tech. Papers, pp.
202-203, 203a, Feb. 2009.
[56] Daquan Huang, Tim R. LaRocca, M.C. Frank Chang, Lorene Samoska, Andy Fung, Richard L. Campbell, and Michael Andrews., "Terahertz CMOS Frequency Generator Using Linear Superposition Technique," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.
2730-2738, Dec 2008.
[57] Eunyoung Seok, Changhua Cao, Dongha Shim, Daniel J. Arenas, David B. Tanner, Chih-Ming Hung, and Kenneth K. O. "A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna," ISSCC Dig. Tech. Papers, pp. 472-629, Feb. 2008.
[58] William F. Andress and Donhee Ham "Standing Wave Oscillators Utilizing Wave-Adaptive Tapered Transmission Lines," IEEE J. Solid-State Circuits, vol. 40, no.
3, pp. 638-651, Mar. 2005.
[59] Jun-Chau Chien and Liang-Hung Lu, "Design of Wide-Tunning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1942-1952, Sept. 2007.
[60] F. Ben Abdeljelil, W. Tatinian, L. Carpineto and G. Jacquemod, "Desigin of a CMOS 12GHz Rotary Travelling Wave Oscillator with Switched Capacitor Tuning," RFIC Dig.
Tech. Papers, pp. 579-582, Jun. 2009.
[61] J. Kim, J.-O. Plouchart, N. Zamdmer, R Trzcinski, K. Wu, B. J. Gross, and M. Kim "A 44GHz Differentially Tuned VCO with 4GHz Tuning range in 0.12μm SOI CMOS,"
ISSCC Dig. Tech. Papers, pp. 416-417, Feb. 2005.
[62] Donhee Ham and William F. Andress, "Standing Wave Oscillators Utilizing Wave-Adaptive Tapered Transmission Lines," ISSCC Dig. Tech. Papers, pp. 380-553, Feb. 2004.
[63] Sai-Wang Tam, Hsing-Ting Yu, Yanghyo Kim, Eran Socher, M.C. Frank Chang, and Tatsuo Itoh, "A Dual Band mm-Wave CMOS Oscillator with Left-Handed Resonator,"
RFIC Dig. Tech. Papers, pp. 477-480, Jun. 2009.
[64] Tai-You Lu and Wei-Zen Chen, “A 38/114 GHz Switched-Mode and Synchronous Lock Standing Wave Oscillator,” IEEE Microwave and Wireless Components Letters, vol. 21, no. 1, pp. 40-42, Dec. 2010.
[65] Jri Lee, Huaide Wang, Wen-Tsao Chen, and Yung-Pin Lee, "Subharmonically injection-locked PLLs for ultra-low-noise clock generation," ISSCC Dig. Tech. Papers, pp. 92-93, 93a, Feb. 2009.
[66] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, ”Millimeter-Wave CMOS Design,” IEEE J. Solid-State Circuit, vol.40, no. 1, pp. 144-155, Jan. 2005.
[67] B. Razavi, “A 60-GHz CMOS Receiver Front-End,” IEEE J. Solid-State Circuit, vol. 41, no. 1, pp. 17-22, Jan. 2006.
[68] B. Razavi, “CMOS Transceivers for the 60-GHz Band,” in IEEE Radio Frequency Integrated Circuit Symposium Dig., San Francisco, CA, Jun. 2006, pp. 11-13
[69] T. Yao, M. Gordon, K. Yau, M. T. Yang, and S. P. Voinigescu, “60-GHz PA and LNA in 90-nm RF-CMOS,” in IEEE Radio Frequency Integrated Circu Symposium Dig., Jun.
2006, San Francisco, CA, pp. 147-150
[70] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Bronderson, ”A 60-GHz Down-Converting CMOS Single-Gate Mixer,” in IEEE Radio Frequency Integrated Circu Symposium Dig., Long Beach, CA, Jun. 2005, pp. 163-166.
[71] A. Hajimire, “mm-wave silicon ICs: challenges and opportunities,” in IEEE Custom Integrated Circuits Conference (CICC), Dig., Sep. 2007, pp. 741-747.
[72] B. Razavi, “A millimeter-wave CMOS heterodyne receiver with on-chip LO and divider,”
IEEE J. Solid-State Circuit, vol.43, no. 2, pp. 477–485, Feb. 2008.
[73] C. S. Wang, J. W. Huang, S. H. Wen, S. H. Yeh, and C. K. Wang, ”A CMOS RF front-end with on-chip antenna for V-band broadband wireless communications,” in Proc. European Solid-State Circuit Conf., Sep. 2007, pp. 143-146.
[74] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Brodersen, “A highly integrated 60GHz CMOS front-end receiver,” in IEEE Int. Solid-State Circuit Conf. Dig., Feb.
2007, pp. 190–191.
[75] A. Parsa and B. Razavi, “A 60GHz CMOS receiver using a 30GHz LO,” in IEEE Int.
Solid-State Circuit Conf. Dig., Feb. 2008, pp. 190–191.
[76] T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tsutsumi, and I. Seto, “A 60-GHz CMOS receiver with frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1030–1037, Apr. 2008.
122 Bibliography [77] H. Wang, “A 50GHz VCO in 0.25μm CMOS,” in IEEE Int. Solid-Satate Circuits Conf.
Dig. Tech. Papers, Feb. 2001, pp. 372-373.
[78] M. Teibout, “A 51GHz VCO in 0.13μm CMOS,” in IEEE Int. Solid-Satate Circuits Conf.
Dig. Tech. Papers, Feb. 2002, pp. 300-301.
[79] C. Cao and K. K. O, “Millimeter-wave voltage-controlled oscillators in 0.13-μm technology,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1297–1304, Jun. 2006.
[80] D. Huang, W. Hant, N.-Y.Wang, T. W. Ku, Q. Gu, R.Wong, and M.-C. F. Chang, “A 60 GHz CMOS VCO using on-chip resonator with embedded artificial dielectric for size, loss and noise reduction,” in IEEE Int. Solid-Satate Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 314-315.
[81] K. Ishibashi, M. Motoyoshi, N. Kobayashi, and M. Fujishima, “76GHz CMOS voltage-controlled oscillator with 7% frequency tuning range,” in Symp. VLSI Circuit Dig. Tech. Papers, Jun. 2007, pp. 176-177.
[82] J. Borremans, M. Dehan, K. Scheir, M. Kuijk, and P. Wambacq, “VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS,” in IEEE Radio Frequency Integrated Circu Symposium Dig., Jun. 2008, Atlanta, Georgia, pp.
135-138
[83] H. K. Chen, H. J. Chen, D. C. Chang, Y. Z. Juang, and S. S. Lu, “A 0.6 V, 4.32 mW, 68 GHz low phase noise VCO with intrinsic-tuned technique in 0.13 μm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 7, pp. 467-469, Jul. 2008.
[84] N. H. W. Fong, J. O. Plouchart, N. Zamdmer, D. Liu, L. F. Wagner, C. Plett, and N. G.
Tarr, “Design of Wind-Band CMOS VCO for Multiband Wirless LAN Application,”
IEEE J. Solid-State Circuit, vol. 38, no. 8, pp. 1333-1342, Aug. 2003.
[85] M. Demirkan, S. P. Bruss, and R. R. Spencer, “Design of wide tuning-range CMOS VCOs using switched coupled-inductors,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp.
1156–1163, May 2008.
[86] L.Geynet, E. D. Foucauld, P. Vincent, and G. Jacquemod, “Fully-Integrated Multi-Standard VCOs with switched LC tank and Power Controlled by Body Voltage in 130nm CMOS/SOI,” in Proc. IEEE Radio Frequency Integrated Circuit Symp., 2006.
[87] Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu, and Tai-You Lu, “A 60-GHz, 14% Tuning Range, Multi-Band VCO with a Single Variable Inductor,” in IEEE Asian Solid-Satate Circuits Conf. Dig. Tech. Papers, Nov. 2008, pp. 129-132.
[88] Tim LaRocca, Jenny Liu, Frank Wang, Dave Murphy, and Frank Chang “CMOS Digital
Frequency Tuning and Low Phase Noise,” IEEE Inter. Micro. Sym., pp. 685–688, July 2009.
[89] Raffaella Genesi, Francesco M. De Paola, and Danilo Manstretta “A 53 GHz DCO for mm-Wave WPAN,” IEEE Custom Integrated Circuits Conference, pp. 571–574, Sept.
2008.
[90] Taeksang Song, Hyoung-Seok Oh, Euisik Yoon, and Songcheol Hong, “A low-power 2.4-GHz current-reused receiver front-end and frequency source for wireless sensor network, ” IEEE J. Solid-State Circuits, vol. 42 no. 5, pp. 1012-1022, May 2007.
[91] Ben W. Cook, Axel. D. Berny, Alyosha Molnar, Steven Lanzisera, and Kristofers S. J.
Pister, “An ultra-low power 2.4GHz RF transceiver for wireless sensor networks in 0.13μm CMOS with 400mV supply and an integrated passive RX front-end, ” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 370-371.
[92] Namjun Cho, Joonsung Bae, and Hoi-Jun Yoo, “A 10.8 mW Body Channel Communication/MICS Dual-Band Transceiver for a Unified Body Sensor Network Controller, ” IEEE J. Solid-State Circuits, vol. 44 no. 12, pp. 3459-3468, Dec. 2009.
[93] Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, and Shoji Otaka “A 950-MHz Rectifier Circuit for Sensor Network Tags With 10-m Distance, ” IEEE J. Solid-State Circuits, vol. 41 no. 1, pp. 35-41, Jan. 2006.
[94] Denis C. Daly and Anantha P. Chandrakasan “An Energy-Efficient OOK Transceiver for Wireless Sensor Networks, ” IEEE J. Solid-State Circuits, vol. 42 no. 5, pp. 1003-1011, May 2007.
[95] Jere A. M. Jarvinen, Jouni Kaukovuori, Jussi Ryynanen, Jarkko Jussila, Kalle Kivekas, Mauri Honkanen, and Kari A. I. Halonen “2.4-GHz Receiver for Sensor Applications, ” IEEE J. Solid-State Circuits, vol. 40 no. 7, pp. 1426-1433, July 2005.
[96] G. Retz, H. Shanan, K. Mulvaney, S. O’Mahony, M. Chanca, P. Crowley, C. Billon, K.
Khan, P. Quinlan, “A Highly Integrated Low-Power 2.4 GHz Transceiver Using a Direct-Conversion Diversity Receiver in 0.18μm CMOS for IEEE802.15.4 WPAN” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 414–415.
[97] Antonio Liscidini, Marika Tedeschi, and Rinaldo Castello, “A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 370–620.
[98] Jerald Yoo, Long Yan, Seulki Lee, Yongsang Kim, and Hoi-Jun Yoo “A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12μW Wirelessly
124 Bibliography Powered Sensor for a Continuous Health Monitoring System, ” IEEE J. Solid-State Circuits, vol. 45 no. 1, pp. 178-188, Jan. 2010.
[99] Wei-Zen Chen, Wei-Wen Ou, Tai-You Lu, Shun-Tien Chou, and Song-Yu Yang, "A 2.4 GHz Reference-less Wireless Receiver for 1Mbps QPSK Demodulation," Proc. of ISCAS, June 2010, pp.1627–1630.
[100] M. S. McCorquodale, S. M. Pernia, J. D. O’Day, G. Carichner, E. Marsman, N. Nguyen, S. Kubba, S. Nguyen, J. Kuhn, and R. B. Brown, “A 0.5-to-480 MHz self-referenced CMOS clock generator with 90 ppm total frequency error and spread-spectrum capability,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp.
524–525.
[101] K. Sundaresan, P. Allen, and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp.
433–442, Feb. 2006.
[102] C. Zhang and K. Makinwa, “Interface electronics for a CMOS electrothermal frequency-locked-loop,” in Proc. ESSCIRC, Sep. 2007, pp. 292-295.
[102] C. Zhang and K. Makinwa, “Interface electronics for a CMOS electrothermal frequency-locked-loop,” in Proc. ESSCIRC, Sep. 2007, pp. 292-295.