Let the cascade divide ratio of the prescaler and feedback divider be N, fLO denote the VCO frequency, and fIF represent the IF frequency. At the onset for data receiving, a constant phase preamble (fRF) from the transmitter is received, and the voltage controlled oscillator (VCO) is preset to its highest frequency which is larger than fRF. The CRL is operated in the frequency acquisition mode, as illustrated in Fig. 6.2(b). Meanwhile, the phase selector (MUX) passes a fixed divider output phase (one of φ0 to φ7) to the GPFD. The down converted signal fIF, where fIF = fLO – fRF , is then compared to fLO/N by the GPFD. If fLO – fRF
> fLO/N, fLO decreases so that fIF is reduced more than fLO/N for N > 1. Contrarily, if fLO/N >
fLO – fRF, fLO increases so that fIF is increased more than fLO/N. By the negative feedback mechanism, when the loop is settled
Mod_CTL fd (=fLO/N)
(a)
f2
f1
fcon
Kd Cycle
fIF
(b)
Fig. 6.3 (a) Frequency discriminator (b) timing diagram of edge counter
N f f
f
fIF = LO− RF = LO (6.1)
Thus the local frequency is determined by N and the RF input frequency, where
RF
LO f
N f N
1
= − (6.2)
The frequency locking detector is realized by a frequency discriminator. Fig. 6.3 illustrates detailed circuit schematic, which is based on the concept of edge counting [18].
As is described in (6.1), when the loop approaches locked, the IF frequency (fIF) would be equal to the divider output (fd = fLO/N). In order to improve the resolution for frequency detection, fd is scaled down by 2Kd to generate a control signal fcon. The high and low level of fcon alternatively performs as gating pulse of fIF, whose counting edges are stored in two latches. In this design, if the contents of latches fall within (Kd±2), the confident counter will be toggled. When the contents in latches hit the target consecutively, implying that fLO
approaches locked state, the status of frequency locked is then resolved by the confident counter.
To successfully demodulate M-ary phase modulation signal, the IF signal should fall into one of the M phase zones during data demodulation. It means that the frequency difference between fIF and fd should be within a locking window before the CRL steps into phase demodulation. For an M-ary PSK modulation signal, let fs be the symbol rate, it can be shown that the lower bound of Kd can be derived as
94 Chapter 6. Reference-Less Frequency Synthesizer and Receiver
When the loop approaches locked, the receiver will acknowledge transmitter for data receiving. The mode control signal (Mod_CTL) will then switch the CRL to phase tracking
Ⅰ
Fig. 6.4 (a) QPSK signal constellation (b) demodulator (c) timing diagram
mode, as illustrated in Fig. 6.2(c). Afterwards, the CRL will keep track the carrier frequency as well as demodulate the QPSK signal simultaneously.
Fig. 6.4 illustrates the scheme for QPSK demodulator and timing diagram for the gating PFD. At the post amplifier output, fIF switches its phase among (0o, 90o, 180o, and 270o) periodically at symbol rate (fs), as is shown in Fig. 6.4(a). For QPSK demodulation, the divider output fd (fd = fLO /N) generates 8 phases (φ0 to φ7)to capture fIF. Here (φ0, φ2, φ4, φ6) divides the signal constellation into 4 zones, and the IF signal is directly demodulated by detecting the operating zones (I, II, III, IV) that fIF falls into. This is accomplished by sampling (φ0 to φ7) using fIF followed by edge detector and decoder. The I/Q digital output is then demodulated after confident counter, as is shown in Fig. 6.4(b).
In each phase zone, the targeted phase for frequency tracking and phase synchronization is (φ1, φ3, φ5, φ7) respectively. The demodulator then switches its corresponding targeted phase according to the demodulated I/Q data through the MUX to the GPFD. Thus the CRL can continuously track the RF signal to maintain the stability of VCO output frequency during data receiving. To avoid mis-disturbing the carrier frequency during phase switching in QPSK signaling, a timing controller in the demodulator will generate gating pulse (GP) to enable the GPFD, as also shown in Fig. 6.4(c). In each symbol time (Ts=1/fs), let the clock cycles (Tck=1/fIF) for data demodulation (zone detection) be tdm, the setup time for next data period phase transition be tsu , and the ratio between IF frequency (fIF) and symbol rate (fs) be K, i.e.,
IF s
K f
= f (6.4)
During these intervals (tdm+tsu), the GPFD is disabled by GP. The active period (GDC) for the GPFD becomes
The loop bandwidth for the CRL during phase tracking and data demodulation mode is designed by taking GDC into account. On the other hand, the tracking bandwidth against noise disturbance for data demodulation reflects in tdm. Both suggest that a higher K improves
96 Chapter 6. Reference-Less Frequency Synthesizer and Receiver
its robustness for demodulation and carrier tracking performance, but also demands a wider bandwidth IF amplifier and demodulator.
6.2.2. Behavior
The stability of the wireless carrier recovery loop is investigated using a PLL-like linear (a)
(b)
(c)
Fig. 6.5 (a) Receiver behavior model (b) equivalent model and (c) noise model
Kpd, VCO gain be Ko, and the transfer function of loop filter and post amplifier be F(s) and L(s) respectively.
The phase transfer function from the received RF signal θi,RF to the VCO output θo,VCO
can be derived as
where G(s)=KpdKoF(s)/s. In this design, the bandwidth of post amplifier is much higher than the IF frequency such that the phase shift caused by L(s) is negligible. Thus the system transfer function can be simplified as
( )
If N >>1(N = 152 in this case), the system transfer function can be approximated as
( )( )
Thus the signal transfer function is the same as that of a typical PLL with feedback factor equal to 1, as is shown in Fig. 6.5(b). The loop gain G(s) can be designed to maintain its stability accordingly. Fig. 6.5(c) illustrates the noise model of the receiver front end, where θn,front-end denotes the excess noise caused by the receiver front-end, and NF is the corresponding noise figure. We have
98 Chapter 6. Reference-Less Frequency Synthesizer and Receiver Thus the VCO phase noise will be elevated by the noise figure of the receiver front-end after phase locked. The designed parameters are summarized in Table 6.1, and the simulated settling behavior is shown in Fig. 6.6.
The GPFD is compared at IF frequency (Kωs) and is periodically enabled and disabled by the gating pulses (GP) for an active period of GDC, which is generated from the I/Q demodulator at a symbol rate (ωs). Assuming that the voltage ripple caused by the nonidealities of PFD, charge pump and periodically gating is represented as
( ) ( ) sin( )
where GDC should be greater than zero to maintain the close loop system. Eq. (11) reveals that the reference spurs will spread at multiples of ωs at double side of the center frequency.
On the other hand, the higher data rate results in a lower reference spurs. The maximum spurs will occur at n=K (ωspurs=ω0±Kωs) which dominates the SFDR of output spectrum. Therefore, the SFDR can be approximated as
It can be seen that the SFDR is improved by a factor of 20log(GDC) since the GPFD only activates for a short period. The SFDR will be the same as that of a conventional PLL if GDC equals to 1. In this design, ωs is the 1 MHz symbol rate, ωm (ωIF) is the 16MHz IF signal, and GDC is around 0.25.
6.3. Circuit Implementation
This section illustrates circuit design of the building blocks in Fig. 6.2 including SSB mixers, VCBUF, multiplexers and PLL. The two stage SSB mixers are design based on different topology due to its input power level and required linearity. The VCBUF are
Table 6.1 Designed parameters
System parameters
N 152
K fIF/fs=16
Kd 128
GDC 0.25
CRL parameters
VCO frequency 2.2 – 2.6 GHz
VCO gain (Ko) 100 MHz/V
Charge pump current (Icp) 60 μA
Loop bandwidth 500 KHz
Phase margin 65°
Fig. 6.6 The simulated settling behavior
100 Chapter 6. Reference-Less Frequency Synthesizer and Receiver
composed of gain-calibrated and phase-calibrated buffers which have similar frequency response over wide frequency range. To speed up the switching time, current steering technique is adopted. An active shunt-shunt feedback is employed to achieve broadband operation. Finally, a second order charge-pump PLL operating in 2.4 GHz is demonstrated.
6.3.1. Low Noise Amplifier
Conventionally, low noise amplifiers in RF receiver are based on common-source [108]
or common-gate [109] architectures, as are shown in Fig. 6.7. Common-source LNA (CSLNA) in general has better noise performance compared to their common-gate counterpart (CGLNA). However, it requires two on-chip inductors for narrow band input matching [110]. Contrarily, CGLNA only needs a single inductor for input matching, as shown in Fig. 6.7(b). It can provide broadband matching depending on the quality factor of the resonator (Ls, Cpad + Cgs). The noise figure of a common gate LNA can be derived as
Fig. 6.7 Low-noise amplifier based on (a) common-source and (b) common-gate topology
2
where α and γ are bias-dependent parameters. To further improve its noise performance, differential gm-boosted CGLNA topology is adopted in this design [109]-[111]. Fig. 6.8 shows the detailed circuit schematic. Its noise figure can be derived as
( )
where A ~ 1 by differential excitation. By choosing CC >> Cgs, the noise figure can be derived as Fig. 6.8 The differential gm-boosted CGLNA
102 Chapter 6. Reference-Less Frequency Synthesizer and Receiver
(6.15) shows that the noise figure performance can be improved compared to (6.13) thanks to differential gm boosted technique. On the other hand, its power consumption can be reduced for input matching.