Fast Hopping and Ultra Wide-Band Frequency Synthesizer
5.2.2. I/Q Calibration Algorithm
For frequency synthesis utilizing SSB mixer, I/Q vectors of the sub harmonics in the first stage SSB travel through different traces and inevitably suffer from gain and phase mismatches. It leads to spur generation at the mixer output. To effectively suppress the image spurs, I/Q calibration algorithm is needed to get rid of gain and phase error.
Typically, I/Q corrections in wireless receiver can be classified into three folds. The first type detects and corrects I/Q imbalances all in the digital base band [18]-[20]. The second type detects I/Q imperfection in the digital base band, while corrects it in the RF/analog front-end [21]-[23]. The third type accomplishes I/Q calibrations in the analog domain [24]-[28] with auxiliary circuits like tunable RC networks or DLL. In this design, I/Q calibration algorithm [29] is implemented with digital tuning capability using phase interpolator. It only requires additional power detector and comparator operated at low frequency without complicated digital circuitries to save power.
Let the I/Q vectors with gain imbalance be represented as E (AˆG1 1,0) and E (0,AˆG2 2),
Under this circumstance, the I/Q trace diagram would become elliptic, as is shown in Fig.
5.5(a). To monitor E and ˆG1 E , test vectors (1,0) and (0,1) are applied at the input of the ˆG2 2nd stage SSB mixer (SSB Mixer2 and SSB Mixer3), as is shown in Fig. 5.6. The gain error is extracted through power detector and comparator, whose output adjust the weighting factors of a vector calibrated buffer (VCBUF), so as to diminish ∆ . A
(a)
(b)
(c)
Fig. 5.5 The trace diagram under (a) gain mismatch, (b) phase mismatch and (c) ratio of output vectors with phase and amplitude error during phase calibration
72 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
On the other hand, for I/Q vectors with phase error ( θ∆ ), the trace diagram would become inclined elliptic shape with tilting angle ( θ∆ ), as shown in Fig. 5.5(b). Let E and ˆP1
ˆP2
E respectively represent vectors (A, A) and (A, -A), we have
( )
( )
1 2
ˆ 2 1 sin
ˆ 2 1 sin
P P
E A
E A
θ θ
= + ∆
= − ∆ (5.7)
For phase error calibration, test vectors (1,1) and (-1, 1) are applied at the input of the 2nd stage SSB mixer, whose output are then captured by power detector and compensated by the VCBUF as well, as illustrated in Fig. 5.6. By forcing EˆˆP1 = EP2 , it turns out that ∆ =θ 0. If a small gain error still exists after gain calibration, the output vectors E and ˆP1 E ˆP2 can be derived as
Fig. 5.6 The I/Q calibration architecture
2 2 convergent analysis for gain and phase calibration. With a gain error distribution form 0 to 2 dB, the phase error can be diminished to zero by equalizing E and ˆP1 E . ˆP2
The phase calibration is preceded by gain calibration, and this procedure is exercised alternatively to equalize the amplitudes of the testing vectors, so as to diminish the gain and phase error. In this design, the gain and phase tuning are 4 bits digitally controlled to fulfill
(a)
(b)
Fig. 5.7 (a) The SSB mixer architecture and (b) the 1st stage SSB mixer
74 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
the accuracy for side band rejection (> 40 dB).
5.3. Circuit Implementation
This section illustrates circuit design of the building blocks in Fig. 5.1 including SSB mixers, VCBUF, multiplexers and PLL. The two stage SSB mixers are design based on different topology due to its input power level and required linearity. The VCBUF are composed of gain-calibrated and phase-calibrated buffers which have similar frequency response over wide frequency range. To speed up the switching time, current steering technique is adopted. An active shunt-shunt feedback is employed to achieve broadband operation. Finally, a second order charge-pump PLL operating in 8.448 GHz is demonstrated.
Fig. 5.7 (a) illustrates the architecture of the 1st stage SSB mixer, and its core cell is shown in Fig. 5.7 (b). As the voltage swing at the divider output is as high as 300 mVpp, passive mixer is adopted for the 1st stage SSB mixer (SSB Mixer1) to mitigate linearity and Fig. 5.8 The 2nd stage SSB mixer
noise issues while reducing power consumption. According to simulation result, the input 1-dB compression point of the mixer is approximately 0 dBm, and the conversion gain is -5 dB.
On the other hand, to suppress harmonic tones and compensate gain loss of the preceding stage, the 2nd stage SSB mixers (SSB Mixer2 and SSB Mixer3) are composed of Gilbert-type mixers (M1-M6, M7-M12, Ms1-Ms4) with tunable resonator as output load, as is shown in Fig. 5.8. The center frequency of the resonator is adjusted by tuning a capacitor
(a)
(b)
Fig. 5.9 (a) Gain calibration buffer (b) I vector after gain calibration
76 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
bank (C1-C4) along with the band switching of the frequency synthesizer. Also, the quality factor of the resonator is enhanced by a negative impedance converter (M13 and M14), which is controlled along with band switches to compensate LC-tank Q variations.
The I/Q vectors of the odd harmonics of 264 MHz travel through different traces and inevitably suffer from gain and phase mismatches when they reach the 2nd stage SSB mixers.
To alleviate the image spurs caused by I/Q imbalance, a vector calibrated buffer (VCBUF) incorporating current DAC is inserted between the two stage mixers to compensate the gain
(a)
(b)
Fig. 5.10 (a) Phase calibration buffer (b) Q vector after phase calibration
and phase error, as is shown in Fig. 5.1.
Fig. 5.9 and Fig. 5.10 illustrate the circuit schematic and vector diagram for gain and phase calibration respectively. The two circuitries are identical and have similar frequency response over a wide frequency range. Both the I/Q vectors after calibration (Iˆ ,cal Qˆ ) is cal indirectly synthesized by phase interpolations. We have
ˆˆ ˆ
ˆ ˆˆ 0
cal in in
cal in in
Q Q I
I Q I
α β
= + ×
= × + × (5.9) (a)
(b)
Fig. 5.11 (a) Gain and (b) phase simulation results of VCBUF
78 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
Here the weighting factors α and β are utilized for phase and gain calibration respectively, which are adjusted by 4 bits current DACs with about 100μA per step and can be calibrated and stored separately for each channel. Fig. 5.11 shows the simulation results of VCBUF. The
(a)
Fig. 5.12 (a) MUX1 and (b) MUX2 circuit schematic
gain controlled range is ±1dB with 0.07dB per step, and the phase tuning range is ±12° with 0.8° per step which is designed based on the Monte-Carlo simulation under process variation.
Besides, the sel and selb signal is utilized to invert I and Q vectors for up or down single side band frequency conversion. Incorporating with the vector calibrated buffer, the image rejection ratio for the SSB mixer can be suppressed below –45 dBc.
Fig. 5.12(a) shows the 1st stage multiplexer. A common gate switching stage is utilized to improve signal isolation and suppress harmonic mixing in SSB Mixer1. The circuit schematic of the 2nd stage multiplexer is shown in Fig. 5.12(b), where one of the 14-band carriers is selected by the parallel input transconductance stage. Broad band operation of 10 GHz is achieved by employing active shunt-shunt feedback [30][31][32]. The 2nd stage SSB mixers along with MUX2 provide 5dB gain to compensate the power loss of the preceding stage. It provides side band rejection up to 60 dB incorporating with the dynamically active 2nd stage SSB mixer.
A charge-pump based phase-locked loop is adopted for generating the harmonics of 264 MHz. The PFD in this design incorporates true-single phase clocking (TSPC) D flip-flop with combinational logic for higher resolution. The simulated dead zone is less than 5 ps.
The core circuit of the charge pump is shown in Fig. 5.13, which is basically composed of current steering switches (M1-M4) and pumping current IU2 and ID2. As the terminal voltage of the LPF is approaching the rail potential (VDD or ground), the pumping up and down currents (IU2 and ID2) will become unbalanced due to the channel length modulation effect. This will result in unequal up and down pulse width in the locked state, and thus induces reference spur.
To alleviate this problem, a regulated current feedback loop consisted of A2, IU1, and ID1 is Fig. 5.13 The charge pump circuit
80 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
employed. Here IU1 and ID1 are replica of IU2 and ID2, and the pumping currents can track each other by adjusting the gate voltage of the current source [33].
Moreover, when both UP and DN are disabled, a unity gain buffer A1 is utilized to track the terminal voltages of the current source to that of the loop filter, so as to alleviate charge sharing effect when the pumping circuits are resumed. However, during the locking process when only UP or DN is asserted, for example, UP is high and DN is low, the tail current source intends to pull down the source node of M3 and M4 if the slew rate of A1 is limited.
Consequently, when the DN pulse is resumed, the imbalance of pumping currents is unavoidable. To solve this problem, we propose an improved charge pump circuit with auxiliary current steering switches (M5, M6) and (M7, M8) [34], which are controlled by Vc1 and Vc2. Here
1 2 C C
V UP DN
V DN UP
= ⋅
= ⋅ (5.10)
The currents IU3 and ID3 are also replica of IU2 and ID2. The auxiliary current switches are employed to keep the tail current IU2 and ID2 alive to prevent the source node of current Fig. 5.14 Chip microphotograph
switches from being over charged or discharged. According to simulation results, the reference spurs induced by pumping current imbalance can be improved by about 20 dB with the proposed circuit technique.
The LC tank QVCO is discussed in section 3.2 with experimental results. Based on complementary architecture, it improves phase noise performance thanks to a more symmetric output waveform [35]. Also, it benefits from two fold negative conductance for power saving. Both Cv1 and Cv2 are accumulation mode MOS varactors for fine frequency tuning. In addition, C1, C2, C3 and C4 are added in parallel for coarse tuning to cope with PVT variations.
The divider chain in the feedback path of the PLL is composed of CML flip-flops. For the first stage divider which operates at 8.5 GHz, shunt-peaking technique is adopted.
5.4. Experimental Result
The experimental prototype of the UWB frequency synthesizer has been fabricated in a 0.18-μm CMOS technology. It provides in-phase and quadrature phase signals for the 14 band carriers through I/Q mixer pairs. Fig. 5.14 shows the chip micrograph. The chip size is 2.5×2.2 mm2, which is mainly occupied by LC resonators. Operating under a single 1.8 V Fig. 5.15 The measured PLL output spectrum
82 Chapter 5. Fast Hopping and UWB Frequency Synthesizer power supply, this chip dissipates 65 mA.
The PLL output spectrum at 8448MHz is shown in Fig. 5.15. The output power is about -12 dBm after the cable loss is taken into account. The reference spur at 264MHz offset is lower than 55 dBc. Fig. 5.16 illustrates the phase noise performance from the 8448 MHz carrier. The measured phase noise is about –98 dBc/Hz at 1 MHz offset, and the integrated rms jitter is about 2.2°.
The worst case image spurs occur for band-11 frequency synthesis (8.712 GHz). As the gray lines shown in Fig. 5.17, the image spur at 8184 MHz is about –22 dB below the main carrier without SSB mixer I/Q calibration. It can be suppressed below –45 dBc when the calibration is on. The improvement is more than 22 dB. On the other hand, as are discussed in section 5.2.1, the remaining spurs at 7656 MHz and 9768 MHz are dominated by the nonlinearities of the SSB mixers, which are 40 dB below the main carrier. Fig. 5.18 shows the output spectrum for band 2 (3.96 GHz, ω1-ω2) carrier generation, whose closest spur is also 528 MHz away from the main carrier. It can be seen that the image spur at 4488 MHz can be reduced by 8 dB after calibration. The remaining spurs generated by the nonlinearities of the SSB mixers are also 40 dB below the main carrier. Fig. 5.19 summaries output spectrum for other frequency bands generations, including band-7 (ω1-7ω2), band-9 (ω1-3ω2), and band-13 (ω1+5ω2). In these cases, their spurious free dynamic rang is mainly dominated by the harmonics of mixers, while their image spurs are less pronounced. The output power is distributed from -18 dBm to -26 dBm, and corresponding spurious free dynamic range is more than 33 dB for the full band carrier generation. When the output frequency hops from band-10 to band-11, the measured settling time is 1.59 ns, as is shown in Fig. 5.20.
Table 5.1 summarizes the performance benchmark with the prior arts. The proposed architecture is reduced the number of PLLs and SSB mixers in cascade, so as to mitigate spurs generation and reduce power consumption. Additionally, the image spurs cause by I/Q imbalance of SSB mixers can be alleviated by applying off-line I/Q calibration. In contrast to conventional analog tuning technique [12], the I/Q vector can be adjusted by 8 bits DAC to facilitate digital control. The spurious tones is reduced by more than 10 dB in contrast to the prior art [11][13][15]. For a fully integrated (PLL included) full-band carrier generation, the experimental prototype consumes the least power compared to the prior art [4].
Fig. 5.17 The measured output spectrum at 8712 MHz (band 11) Fig. 5.16 The measured PLL phase noise
84 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
Fig. 5.18 The measured output spectrum at 3960 MHz (band 2)
(a)
(b)
(c)
Fig. 5.19 The measured output spectrum at (a) 7656 MHz (band 9) (b) 9468 MHz (band 13) and (c) 6600 MHz (band 7)
86 Chapter 5. Fast Hopping and UWB Frequency Synthesizer
5.5. Conclusion
In conclusion, we propose a 3-10 GHz, 14 band CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. The spur issues of cascaded SSB mixers in direct frequency synthesis method are investigated in detail, and also verified with theoretical analysis, circuit simulation, and experimental results. The frequency synthesizer is based on a single PLL and two stages SSB frequency mixing architecture. It alleviates harmonics mixing and pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer. It also improves the side band leakage issues. Finally, we further improve the spurious tones by applying off-line I/Q calibration. By gain and phase adjustment, the image spurs can be reduced and suppressed below -45dBc. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply.
Fig. 5.20 Measured switching behavior from 8.1 GHz to 8.7 GHz
Table 5.1
Performance benchmark of MB-OFDM UWB frequency synthesizers
Reference This work [14]