Chapter 4 Circuit Implementation
4.4 Comparison
The comparison of this work and previous researches are listed at Table 4.11 and Figure 4.24, in order to compare the design result, we define the figure-of-merit as:
⎟ ⎠
Table 4.11 Comparison of this work
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The FOM comparison shows that the power consumption of proposed SDM is lowest compared to other researches while the FOM is still above average. The SNR versus power comparison is shown at Figure 4.24.
Performance Comparison
Figure 4.23 SNR versus power comparison comparisons
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Chapter 5
Testing Setup and Measurement
A testing setup for fabricated chip is presented in this chapter. And a costumed designed printed circuit board (PCB) is designed and fabricated to integrate the targeting prototype chip in order to measure the performance metrics of proposed design. Following by the setup for measurement, the experimental results is presented and discussed. And the performance summary is summarized in the end of this chapter.
5.1 Testing Environment Setup
The testing environment setup is shown as Figure 5.1. It includes a printed circuit board (PCB) including a device under test (DUT) board, a logic analyzer (Agilent 16902A), an audio signal generator (Stanford Research DS360), a power supply (E3610A), a mixed-signal oscilloscope (Agilent 54641D) and a PC to analyze the output bit stream of proposed modulator.
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Figure5.1 experimental test chip
As shown in Figure 5.1, the input signal is generated by audio signal generator, and the digit output is fed to the logic analyzer, then load to PC for MATLAB simulation. A PCB board combines the clock generator (a crystal oscillator) and a device under test (DUT) to measure the chip. The photograph of the measurement environment is shown at Figure 5.2.
Figure 5.2 Photograph of the measurement environment
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5.2 Measurement Result
The measurement result of proposed chip is failed. The probably reason is that the transistor size of the output buffer is too small to push the ESD PAD and the parasitic capacitance of the packages as Figure 5.3 shows.
Figure 5.3 Probably problem of output buffers
Stage1 Stage 2
1um/0.18um 4um/0.18um
Table 5.1 Output buffer device ratio summaryDue to the problem of this layout, we modify the design as Figure 5.4, and it is modified by following principles:
1. ESD protection for analog input signals while the output pad is pure pad to reduce chip area and measuring core power of proposed SDM.
2. Wider metal for power lines.
3. Independent PAD for different supply voltage: AVDD, DVDD, IOVDD to measure the power respectively.
4. A larger output buffer of six stages is used, the device ratio is listed at Table 5.2.
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Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6
1/0.18um 3/0.18um 9/0.18um 27/0.18um 81/0.18um 243/0.18um
Table 5.2 the modified output buffer device ratio summary
Figure 5.4 modified version of layout
We also take the measurement of the core power into considerations of the modified version of layout, we use three independent supply voltage pads for analog circuits (part A), clock generator circuit (part B) and output buffer (part C), respectively. The
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simulation results of the power consumption for three parts are listed at Table 5.3, and the post layout simulation results are shown at Figure 5.5. The simulated result of SNR and SNDR are listed at Table 5.4.
A A+B A+B+C
Power(uW) 14.3 18.0 25.4
Table 5.3 Power consumption for three parts circuits
Figure 5.5 8192-point FFT of the modified layout
Unit(dB) Pre-Simulation
Post-Simulation Modified layout
SNR 69.1 63.4
61.3
SNDR 68.4 58.7
57.9
Table 5.4 Comparison of this modified layout
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5.3 Summary
The circuit present in this thesis is implemented by design considerations described in Chapter 3 and circuit design implementation in Chapter 4.This work emphasized the complete design flow for low-power design and the current optimization of the OTA by discussing the slewing-settling trade-off of it.
The predicted resolution of the SDM is 11.2 bits (68.4dB), and the post-simulation result is 9.6 bits (58.7dB). It can be used in the audio electrical portable devices applications.
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Chapter 6 Conclusions
This thesis describes the design and implementation of a low-power second-order sigma-delta modulator (SDM) with CIFF structure for audio-band applications. A single stage class-A positive feedback OTA with current optimization has been presented to lower the power of SDM.
Using 0.18um CMOS technology, this modulator achieves SNR of 63.4dB with 16KHz bandwidth. With a moderate target signal-noise-ratio (SNR), it is suitable for battery-based operation system, such as mp3 players, biomedical electronic and digital hearing aid instrument applications. The simulation results show that the power consumption is 18uW. It is the lowest compared to references [2]-[9].
The future work is to integrate the modified version from the problems of proposed SDM. A low-power measurement consideration is included in the modified SDM design consideration.
After this modified layout, a high resolution sigma-delta modulator can be done using the same method of optimizing the power of the OTA.
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