Organization

In Chapter 2, the beginning is the overview of the analog-to-digital converters (ADC). After them, the quantization issues, oversampling and noise shaping are introduced. Then the performance metrics of sigma-delta modulators (SDM) end this chapter.

Chapter 3 describes the system level design considerations, including the analysis of the power issues of SDM, the topology selections and the limitations and non-ideal effects of the SDM.

Chapter 4 discusses the topics of sub-circuits that will be used to realize the proposed SDM circuit, which includes an OTA, a comparator, a clock generator, capacitors and switches. The pre-simulation and post-simulation results are given. The layout level design will be described in this sequence.

In Chapter 5, the testing environment is present, including the instruments and the testing circuits on printed circuit board (PCB).The experimental results for the SDM, which is fabricated in a 0.18um 1P6M 1.8V standard CMOS technology with MIM process will be summarized.

4

Chapter 2

SDM Fundamentals

This chapter begins with a brief overview of analog-digital converter (ADC).

Following by the classification of ADC, the oversampling and noise shaping is introduced and considered and defined mathematically. The performance metrics of targeting ADC is than described in the end of this chapter.

2.1 A brief Introduction of ADC

The ADCs are fed a continuous-time analog signal to convert discrete-time digital signals. In order to perform the analog to digital conversion, two steps should be down. The first is the discretization of the continuous analog signal, which is called sampling. After sampling, the quantization step is followed by digitizing the amplitude of the discrete signal, as shown in Figure 2.1.

Figure 2.1 Block diagram of an ADC

5

For an ADC, there are two important parameters, input signal bandwidth and resolution, and different types of ADCs are developed according to different input signal bandwidth and resolution requirements as depicted in Table 2.1. Among the ADCs, the sigma-delta ADC is suitable to medium to high resolution applications in the audio frequency range.

Category Structure

Low-to-Medium Speed

High Accuracy

Integrating ADC Sigma-Delta ADC

Medium Speed , Medium Accuracy Successive approximation ADC High Speed

Low-to-Medium Accuracy

Pipeline ADC Flash ADC Table 2.1 various kinds of ADCs

Since the process of quantization is a classification process in amplitude, there is always an error in an ADC, and the quantization error

e is smaller than the

_q quantization stepΔ of the ADC, as depicted in Figure 2.2.

− ≤ Δ 2 e

^q

≤ Δ 2

(2.1)

6

Figure 2.2 Transfer curve of ADCs

The quantization stepΔ is called the least significant bit (LSB) of the ADC, where

2

ref N

Δ = V

. If we assume that the quantization noise is white noise, it is uniformly

distributed between 2

±

LSB

, as Figure 2.3:

2

12 ⎟

⎠

⎜ ⎞

⎝

⎛ Δ

Δ 2

− Δ 2

Figure 2.3 Power spectral density of quantization noise

7

Therefore, the power of the quantization error can be derived as:

For a sinusoidal input signal, its maximum peak value without clipping is 2 2

N Δ

, where N is the bit number of the quantizer. Thus the sinusoidal signal power equals

to:

From the equation, if the quantization noise can be modeled as a noise source, we can calculate the signal-noise-ratio (SNR) of an ideal N-bit ADC:

( )

10log 10log 10log 2 10log 6.02 1.76( )

2

8

2.2 Oversampling and Noise Shaping

This section describes the principle and the theorem of the digital signal processing technique. We discuss oversampling first, which is followed by noise shaping.

2.2.1 Oversampling

For a signal bandwidth of

f , the Nyquist rate is 2

_B

f .A Nyquist ADC represent

_B that the sampling frequency of the ADC is at Nyquist rate. Moreover, an ADC with the oversampling technique can also improve the SNR. Its sampling rate

f is greater

_S more times than the signal bandwidth 2

f , and the oversampling ratio is defined

_B as

B s

f OSR f

= 2 , as Figure. 2.4, than the quantization power spectral density is reduced to:

Figure 2.4 Quantization noise in an oversampled converter Thus the peak SNR equals to:

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2.2.2 Noise Shaping

With oversampling technique, the SNR increase 0.5 bit if sampling frequency is doubling. In addition to use oversampling technique to improve the performance of ADCs, we can use noise shaping technique to further increase the SNR of the ADC, by applying a loop filter before the quantizer and introducing the feedback, a

noise-shaping modulator is built and new noise transfer function is realized.

A basic Sigma-Delta modulator is shown in Figure 2.5, it contains a loop filter, a quantizer and a feedback loop. If we assume that the DAC feedback gain is unity, than we can express the output of the SDM is:

Y z ( ) = STF z X z ( ) ( ) + NTF z E z ( ) ( )

(2.7)

Figure 2.5 A linear model of the sigma-delta modulator

Where STF(z) represents the signal transfer function and NTF(z) represents the noise transfer function. And the STF(z) and NTF(z) can be calculated as:

10

With the large gain of H(z) at the frequency band, the STF(z) will approximate unity and the NTF(z) is going to approximate zero over the signal band. Thus the quantization noise is further attenuated than only by oversampling.

2.3 Performance Metrics

The performance metrics is shown at Figure 2.6 with a full scale sine wave to ADC, performed a Discrete Fourier Transform (DFT) to map into Fast Fourier Transform (FFT) spectrum. Some of the performance metrics are listed below, while the unit is

“dB”.

1. SFDR: the abbreviation of “spurious free dynamic range”. Difference between the fundamental bin and the highest harmonic bin.

2. SNR: the abbreviation of “signal to noise ratio”. Fundamental power divided by the power of the bins in the FFT other than DC, fundamental and first N harmonic bins.

3. SNDR: the abbreviation of “signal to noise and distortion ratio”. Fundamental power divided by the power of the bins in the FFT other than DC and fundamental bins.

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4. ENOB: the abbreviation of “effective number of bits”, which is defined at Equation 2.10:

1.76 ( ) 6.02

ENOB = SNDR − dB

(2.10)

5. DR: the abbreviation of “dynamic range”. Effective input range when SNR remains positive.

0 2 4 6 8 10 12 14

x 10⁴ 0

20 40 60 80 100 120 140

Frequency [Hz]

Output spectrum [dB]

Figure 2.6 Performance metrics

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Chapter 3

System Considerations

This chapter discusses actual SDM design considerations. We begin with reviewing previous researches then consider power issues in traditional SDM design, and the system parameter considerations are discussed in Section 3.2. Several non-idealities such as gain requirement, settling of OTA and capacitor sizing are discussed in the end of the chapter.

3.1 Power Issues in SDM

There are many researches about how to reduce the power of the sigma-delta modulator for audio band applications in recent years [2-9].

A switched-OPamp technique combined with a dc level shift has been proven to allow proper operation under low VDD conditions (0.7v),thus lower the power consumption[2]; A new fully differential CMOS class AB Operational Amplifier with a charge-pump is proposed [3]; And a load-compensated OTA with rail-to- rail output swing and gain enhancement is used in a 90nm technology [4]; And a 0.6v folded-cascode OTA topology is used in a 2-2 cascade delta-sigma ADC design with a resistor-based sampling technique[5]. A switched-current SDM is used for a bio-acquisition Microsystems with 0.8v power supply. And a Digital Hearing Aid

13

chip is proposed [7]; Then a ADC is designed and optimized for a CMOS image sensor[8]; Finally, a 4^th order SDM is presented with a single stage class A OTA and positive feedback[9].

The comparisons of above researches are listed as Table 3.1:

Technology VDD Signal BW(KHz)

Table 3.1 Summary of previous SDM papers

Among these researches, a part of them adopt some special analog circuits, such as switched-Opamp technique[2], switch-current topology[6] or resistor-based sampling technique[5] to reduce the power. Moreover, because that the power consumption of a SDM is most consumed at the OTA in loop filter, therefore some of them choose adaptive OTA topology to reduce power [3][4][7][8][9].

14

From above researches, we can observe that the former have a low supply voltage, but generally they often have larger chip area due to the use of extra component.

Furthermore, using a low-power OTA in loop filter is an effective method to lower the power consumption of SDM because that the power consumption of a SDM is most consumed at the OTA in loop filter.

There are several specifications we must take care when designing an OTA (such as gain requirement, bandwidth, slew-rate, phase margin, output swing…etc) in Sigma-Delta A/D system conveniently. The specifications of the OTA in these researches are listed at Table 3.2. From the table, we can observe these specifications are followed by the “rule of thumbs” in traditional ADC design mostly. A lack of specification detail analysis is happened in these researches.

OP Architecture Fs (MHz)

Table 3.2 Specification comparison of OTA

In fact, traditional design rules are not optimized according to low-power concern, so specifications optimization is needed in low-power demand SDM design.

Therefore, we try to use a suitable OTA topology, and then we optimize the power

15

consumption by minimizing the total current consumption of OTA such as Figure 3.1 shows in this thesis. No special technology or extra analog devices is needed, thus the chip area and cost are also lower compared to previous researches.

Figure 3.1 power consumption in an OTA

3.2 System Parameter Considerations

Our design goal is to achieve a lowest power consumption SDM while the target SNR (DR) is high enough for audio band portable electric devices applications. There are many trade-offs when designing a low-power SDM, thus three steps are followed in this section to determine the system parameters of the SDM, topology decision, architecture selection and coefficient decision, respectively.

16

3.2.1 Topology Decision

The first step to design a sigma-delta modulator is to determine the system level parameters based on the modulator specifications while the power consumption can be minimized. The power consumption formula:

^{Power = × = × × I V f c} ( ^Vdd )

² (3.1)

Therefore, we must choose the supply voltage we used in this thesis. The basic principle is to reduce power, and in TSMC 0.18um technology, vtn+vtp～0.9v, so we choose supply voltage is one volt for some design.

The system-level parameters include oversampling ratio (OSR), the loop filter order (L), the number of the quantizer level (N).

First we decide N. Because the power consumption of the quantizer increases proportionally with N, and a multi-bit quantizer have more complicated DAC structure, thus will make whole circuit more complicated and consume more power, so for a low-power SDM design, the number of the quantizer should be minimized, so we choose N=1.

Second, because single-stage structure has more advantages on low-power design, for example simple analog circuit, good circuit mismatch characteristic, so single stage architecture is selected.

Therefore, for a target SNR, the oversampling ratio (OSR) can be made after deciding the loop filter order n:

17

A higher loop filler order n have more switches and integrators, lower sampling frequency, and higher order of n has more stability issue. So we have to make a trade-off between the order and the sampling frequency. If we compare different order N by simple estimation (suppose power consumption is proportional to sampling frequency), we can know that for loop filter order 2, 3, and 4, we can have similar power consumption as Table 3.3 shows.

Power Consumption (unit in uW) Loop filter

Table 3.3 Power comparison of different loop filter order

Therefore, a second order architecture, 1-bit with OSR=64 is chosen because of the simplicity of the analog circuits, thus we can use simpler circuit to achieve the same target SNR.

18

3.2.2 Architecture Selection

The most general single stage topology in the SDM design is the CIFB architecture, and it is shown at Figure 3.2:

Figure 3.2 Chain of Integrators with distributed feedback(CIFB)

The input and output relation in CIFB topology can be expressed as:

Y z ( ) = Z X Z

⁻²

( ) (1 + − Z

^{−1 2}

) E Z ( )

(3.3) Where the STF and NTF are given by

2 1 2

( ) , ( ) (1 )

STF z = Z

⁻

NTF Z = − Z

⁻ (3.4)

Where the output of integrator one and two are:

( )

1 1 1 1

1 (1 ) (1 ) ( )

y = Z

⁻

− Z

⁻

X Z − Z

⁻

− Z

⁻

E z

(3.5)

^{y 2 = Z X Z}

⁻²

( ) ^{− Z}

⁻¹

^{(1 − Z}

⁻¹

^{) ( ) E z}

(3.6)

From the equations, we can know that the output signal of the integrators are the functions of input signal x(z), so if we want to have a full scale input signal x(z), than there will be a large output swing at y1(z) and y2(z),hence the power of the OPAMP will increased .

19

If the x(z) has a smaller input signal, than the target SNR of the modulator will be degraded. So this feature make the CIFB topology have some restriction for low-power design.

Because the nature restriction of the CIFB architecture, another architecture is chosen for low-power design [1], the CIFF architecture have some advantages, and its figure is shown at Figure 3.3:

Figure 3.3 Chain of integrators with weighted feed-forward summation. (CIFF)

The input and output relation in CIFF topology can be expressed as:

)

Where the STF and NTF are given by:

2

Where the output of integrator one and two are:

( ) ^Z

20

From above equations, we observed that the output signals of two integrators y1 and y2 in CIFF structure are not contain the input signal x(z),which means that this loop filter process E(z) only, thus the output swing requirements of the loop filter will decrease ,it means that the slew-rate requirement is not critical when we design the OPAMPs in loop filter[3], so it is more suitable for low-power applications.

3.2.3 Coefficient Decision

In a general structure of CIFF sigma-delta modulator like Figure 3.4, the modulator contains five coefficients: two integrator gain (a1, a2) and three summation factor (b0, b1, b2):

Figure 3.4 Simulink model of a 2^nd-order CIFF SDM

From the Delta-Sigma Toolbox, give order=2, OSR=64, the noise transfer function (NTF) that have SNR(max):

21

Figure 3.5 a second order CIFF SDM And from calculation of the Figure 3.5,

( )

After deciding the transfer function of the SDM, we must decide which combination of (a1, a2, b1, b2, b3) we will use. Because our design target is to achieve low-power, and the most important feature of a low power SDM is that the signal swing at the loop filter output must be small.

22

Figure 3.6 A general linear model of SDM

Figure 3.6 is a general case first-order SDM, we can know that when the coefficient a1 is larger, the output swing of the loop filter is larger ,then the power consumption is larger of the whole modulator; therefore, if we want to have a smaller signal swing, the a1 coefficient must be minimized.

However, if a1 is too small, the stability of the SDM will be degraded because the signal will overload, and the SNR will decrease, so we must make a trade-off between the coefficients.

In this work, we choose a1=0.25 and b1=3,combined above requirement, capacitor matching and the signal scaling issues, the coefficients of the second-order modulator is listed at Table 3.4:

Integrator Coefficients Feed-Forward Coefficients

a1=0.25 b0=1

a2=1 b1=3 b2=1

Table 3.4 Coefficient of proposed SDM

23

Under the coefficients, the modified NTF becomes:

( )

5 . 0 25 . 1 ) 1

(

₂

2 '

+

−

= −

z z

Z z

NTF

(3.13)

It cause a slightly change of the NTF pole and it will not degrade the SNR significantly.

The ideal Output spectrum of 8192-point FFT with 8k input signal is shown at Figure 3.7, the simulation result reveals that the SFDR exceed 78dB.

Fig.3.7 Ideal 8192 point FFT of proposed SDM architecture

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3.3 Non-idealities Considerations

The above simulations show an ideal model of the second-order sigma-delta modulator. However, there are some non-ideal effects in analog circuit design and it is unavoidable, so we must evaluate the non-ideal effect to make our designs meet the desired margin.

3.3.1 Gain requirement

The transfer function of an ideal integrator:

1

However, the gain of OTA cannot be infinite in circuit design, when a finite gain is A in an OTA, the transfer function will become:

1

Figure 3.8 a switched-capacitance circuit in SDM

25

A finite gain of OTA means that the pole of the H(Z) will depart from unit circle, and when the distance of the zero exceed about

1 1 S I

C C OSR π

⋅

, the noise attenuation of NTF begins to degrade, so the lower limit of A is about 40 dB[10].

3.3.2 Settling of the OTA

In a switched-capacitance circuit, the loop filter can be separately into two parts, namely the sampling period and the integration period, as shown at Figure 3.9:

Figure 3.9 Sampling and integration period of a loop filter

When the loop filter is at integration period, the settling behavior of the OTA can be derived as the Figure 3.10. A slewing is happened when a large output change of the loop filter. When the differential input voltage is less than

2 V

_OV, the OTA enters linear settling region. Because of the speed limitation of the OTA, settling error will occur at the end of integration period as the Figure 3.10 shown, so we must take settling error into consideration when designing OTA.

26

Figure 3.10 Settling behavior of OTA

3.3.3 Capacitor Sizing

The input-referred thermal noise of the integrator is:

s

n

C

V

² =

KT

, (3.16)

Where Cs is sampling capacitor of the integrator.

With an oversampling ratio of OSR, the in-band KT/C noise:

And if for a full scale input amplitude, the in-band noise power must be at least 85dB below the signal power:

2

27

Ö

^C

^{S >8}

^{KT V}

^⋅_DD⁽

^SNR

^2⋅

( ^OSR

^_

^peak )

⁾ (3.19)

Ö It can be calculated that Cs> 0.163pF

The simulation result of first sapling capacitor is shown at Figure 3.11, from the figure we choose Cs1=0.5pF for safety noise margin.

Figure 3.11 Simulation result of the first sampling capacitor

The KT/C noise at the input of the second integrator is shaped by the first-order noise shaping, so that Cs2 can be scaled down since its effect of thermal noise is fewer. In this SDM system, we choose C^S2=0.2pF.

28

Chapter 4

Circuit Implementation

The proposed sigma-delta modulator has been fabricated in TSMC 0.18um single-poly six-metal CMOS process. The circuitry is operating at a supply voltage of 1 volt. The sub-blocks which including OTA, comparator, clock generator and switched capacitor circuit in SDM are described in Section 4.1. In Section 4.2, the simulation results of sub-blocks and whole SDM are presented. In Section 4.3, the final layout design of proposed SDM is then described.

4.1 Transistor Level Design

After considering the system parameters and non-idealities of proposed SDM, the following is the circuit implementation. The sub-circuit of each component in this modulator is presented including OTA, 1-bit quantizer, clock generator, switched capacitor circuit, respectively.

4.1.1 Differential OTA in loop filter

The OTA in loop filter is the analog block which consumes the most power, and it also dominant the performance of the modulator, so it is the most critical building block that we must design it seriously.

29

In previous researches, a single stage OTA must used because it doesn’t have to waste extra current in driving the compensated capacitance[4], and although the class-AB OTA is the most widely used OTA architecture when designing a low power SDM, it requires extra paths to drive the transistor of output stage[9]; Therefore, a single-stage class-A Amplifier with positive feedback to increase its gain is used in this design, as shown in Figure 4.1, We use PMOS as the input transistor because of two reasons:

(1)The input common mode voltage (ICM) is low than Vt

(2)The noise of PMOS input pair is smaller than NMOS

Figure 4.1 Single Stage Class-A OTA with positive feedback

An OTA in loop filter works at the integration period, and the settling behavior of the OTA can be divided into two parts, the slewing and the settling time. A slewing is happened when a large output change of the loop filter. When the differential input voltage is less than 2

V

_OV, the OTA enters linear settling region, with a 2MHz clock, the integration period is 250ns, so that:

30

ns T

T

_SR

+

_settling

= 250

(4.1)

A trade-off between the slewing time and linear settling time means different settling behavior of the OTA. The proposed optimization technique is to find the optimization of slewing-settling trade-off as shown in Figure 4.2, thus the total current consumption of the OTA can be minimized, and the analysis is followed.

V

OV

2

Figure 4.2 trade-off between slewing and linear settling

The slewing behavior is related to the current of output path:

SR

For a load capacitance of 2.5pf and a v=0.5, we can derive that:

31

The speed of the OTA settling is depend on its time constant, therefore , the unit gain bandwidth, therefore the input path current of the OTA, we set the linear settling

The speed of the OTA settling is depend on its time constant, therefore , the unit gain bandwidth, therefore the input path current of the OTA, we set the linear settling

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