Performance Metrics

The performance metrics is shown at Figure 2.6 with a full scale sine wave to ADC, performed a Discrete Fourier Transform (DFT) to map into Fast Fourier Transform (FFT) spectrum. Some of the performance metrics are listed below, while the unit is

“dB”.

1. SFDR: the abbreviation of “spurious free dynamic range”. Difference between the fundamental bin and the highest harmonic bin.

2. SNR: the abbreviation of “signal to noise ratio”. Fundamental power divided by the power of the bins in the FFT other than DC, fundamental and first N harmonic bins.

3. SNDR: the abbreviation of “signal to noise and distortion ratio”. Fundamental power divided by the power of the bins in the FFT other than DC and fundamental bins.

11

4. ENOB: the abbreviation of “effective number of bits”, which is defined at Equation 2.10:

1.76 ( ) 6.02

ENOB = SNDR − dB

(2.10)

5. DR: the abbreviation of “dynamic range”. Effective input range when SNR remains positive.

0 2 4 6 8 10 12 14

x 10⁴ 0

20 40 60 80 100 120 140

Frequency [Hz]

Output spectrum [dB]

Figure 2.6 Performance metrics

12

Chapter 3

System Considerations

This chapter discusses actual SDM design considerations. We begin with reviewing previous researches then consider power issues in traditional SDM design, and the system parameter considerations are discussed in Section 3.2. Several non-idealities such as gain requirement, settling of OTA and capacitor sizing are discussed in the end of the chapter.

3.1 Power Issues in SDM

There are many researches about how to reduce the power of the sigma-delta modulator for audio band applications in recent years [2-9].

A switched-OPamp technique combined with a dc level shift has been proven to allow proper operation under low VDD conditions (0.7v),thus lower the power consumption[2]; A new fully differential CMOS class AB Operational Amplifier with a charge-pump is proposed [3]; And a load-compensated OTA with rail-to- rail output swing and gain enhancement is used in a 90nm technology [4]; And a 0.6v folded-cascode OTA topology is used in a 2-2 cascade delta-sigma ADC design with a resistor-based sampling technique[5]. A switched-current SDM is used for a bio-acquisition Microsystems with 0.8v power supply. And a Digital Hearing Aid

13

chip is proposed [7]; Then a ADC is designed and optimized for a CMOS image sensor[8]; Finally, a 4^th order SDM is presented with a single stage class A OTA and positive feedback[9].

The comparisons of above researches are listed as Table 3.1:

Technology VDD Signal BW(KHz)

Table 3.1 Summary of previous SDM papers

Among these researches, a part of them adopt some special analog circuits, such as switched-Opamp technique[2], switch-current topology[6] or resistor-based sampling technique[5] to reduce the power. Moreover, because that the power consumption of a SDM is most consumed at the OTA in loop filter, therefore some of them choose adaptive OTA topology to reduce power [3][4][7][8][9].

14

From above researches, we can observe that the former have a low supply voltage, but generally they often have larger chip area due to the use of extra component.

Furthermore, using a low-power OTA in loop filter is an effective method to lower the power consumption of SDM because that the power consumption of a SDM is most consumed at the OTA in loop filter.

There are several specifications we must take care when designing an OTA (such as gain requirement, bandwidth, slew-rate, phase margin, output swing…etc) in Sigma-Delta A/D system conveniently. The specifications of the OTA in these researches are listed at Table 3.2. From the table, we can observe these specifications are followed by the “rule of thumbs” in traditional ADC design mostly. A lack of specification detail analysis is happened in these researches.

OP Architecture Fs (MHz)

Table 3.2 Specification comparison of OTA

In fact, traditional design rules are not optimized according to low-power concern, so specifications optimization is needed in low-power demand SDM design.

Therefore, we try to use a suitable OTA topology, and then we optimize the power

15

consumption by minimizing the total current consumption of OTA such as Figure 3.1 shows in this thesis. No special technology or extra analog devices is needed, thus the chip area and cost are also lower compared to previous researches.

Figure 3.1 power consumption in an OTA

3.2 System Parameter Considerations

Our design goal is to achieve a lowest power consumption SDM while the target SNR (DR) is high enough for audio band portable electric devices applications. There are many trade-offs when designing a low-power SDM, thus three steps are followed in this section to determine the system parameters of the SDM, topology decision, architecture selection and coefficient decision, respectively.

16

3.2.1 Topology Decision

The first step to design a sigma-delta modulator is to determine the system level parameters based on the modulator specifications while the power consumption can be minimized. The power consumption formula:

^{Power = × = × × I V f c} ( ^Vdd )

² (3.1)

Therefore, we must choose the supply voltage we used in this thesis. The basic principle is to reduce power, and in TSMC 0.18um technology, vtn+vtp～0.9v, so we choose supply voltage is one volt for some design.

The system-level parameters include oversampling ratio (OSR), the loop filter order (L), the number of the quantizer level (N).

First we decide N. Because the power consumption of the quantizer increases proportionally with N, and a multi-bit quantizer have more complicated DAC structure, thus will make whole circuit more complicated and consume more power, so for a low-power SDM design, the number of the quantizer should be minimized, so we choose N=1.

Second, because single-stage structure has more advantages on low-power design, for example simple analog circuit, good circuit mismatch characteristic, so single stage architecture is selected.

Therefore, for a target SNR, the oversampling ratio (OSR) can be made after deciding the loop filter order n:

17

A higher loop filler order n have more switches and integrators, lower sampling frequency, and higher order of n has more stability issue. So we have to make a trade-off between the order and the sampling frequency. If we compare different order N by simple estimation (suppose power consumption is proportional to sampling frequency), we can know that for loop filter order 2, 3, and 4, we can have similar power consumption as Table 3.3 shows.

Power Consumption (unit in uW) Loop filter

Table 3.3 Power comparison of different loop filter order

Therefore, a second order architecture, 1-bit with OSR=64 is chosen because of the simplicity of the analog circuits, thus we can use simpler circuit to achieve the same target SNR.

18

3.2.2 Architecture Selection

The most general single stage topology in the SDM design is the CIFB architecture, and it is shown at Figure 3.2:

Figure 3.2 Chain of Integrators with distributed feedback(CIFB)

The input and output relation in CIFB topology can be expressed as:

Y z ( ) = Z X Z

⁻²

( ) (1 + − Z

^{−1 2}

) E Z ( )

(3.3) Where the STF and NTF are given by

2 1 2

( ) , ( ) (1 )

STF z = Z

⁻

NTF Z = − Z

⁻ (3.4)

Where the output of integrator one and two are:

( )

1 1 1 1

1 (1 ) (1 ) ( )

y = Z

⁻

− Z

⁻

X Z − Z

⁻

− Z

⁻

E z

(3.5)

^{y 2 = Z X Z}

⁻²

( ) ^{− Z}

⁻¹

^{(1 − Z}

⁻¹

^{) ( ) E z}

(3.6)

From the equations, we can know that the output signal of the integrators are the functions of input signal x(z), so if we want to have a full scale input signal x(z), than there will be a large output swing at y1(z) and y2(z),hence the power of the OPAMP will increased .

19

If the x(z) has a smaller input signal, than the target SNR of the modulator will be degraded. So this feature make the CIFB topology have some restriction for low-power design.

Because the nature restriction of the CIFB architecture, another architecture is chosen for low-power design [1], the CIFF architecture have some advantages, and its figure is shown at Figure 3.3:

Figure 3.3 Chain of integrators with weighted feed-forward summation. (CIFF)

The input and output relation in CIFF topology can be expressed as:

)

Where the STF and NTF are given by:

2

Where the output of integrator one and two are:

( ) ^Z

20

From above equations, we observed that the output signals of two integrators y1 and y2 in CIFF structure are not contain the input signal x(z),which means that this loop filter process E(z) only, thus the output swing requirements of the loop filter will decrease ,it means that the slew-rate requirement is not critical when we design the OPAMPs in loop filter[3], so it is more suitable for low-power applications.

3.2.3 Coefficient Decision

In a general structure of CIFF sigma-delta modulator like Figure 3.4, the modulator contains five coefficients: two integrator gain (a1, a2) and three summation factor (b0, b1, b2):

Figure 3.4 Simulink model of a 2^nd-order CIFF SDM

From the Delta-Sigma Toolbox, give order=2, OSR=64, the noise transfer function (NTF) that have SNR(max):

21

Figure 3.5 a second order CIFF SDM And from calculation of the Figure 3.5,

( )

After deciding the transfer function of the SDM, we must decide which combination of (a1, a2, b1, b2, b3) we will use. Because our design target is to achieve low-power, and the most important feature of a low power SDM is that the signal swing at the loop filter output must be small.

22

Figure 3.6 A general linear model of SDM

Figure 3.6 is a general case first-order SDM, we can know that when the coefficient a1 is larger, the output swing of the loop filter is larger ,then the power consumption is larger of the whole modulator; therefore, if we want to have a smaller signal swing, the a1 coefficient must be minimized.

However, if a1 is too small, the stability of the SDM will be degraded because the signal will overload, and the SNR will decrease, so we must make a trade-off between the coefficients.

In this work, we choose a1=0.25 and b1=3,combined above requirement, capacitor matching and the signal scaling issues, the coefficients of the second-order modulator is listed at Table 3.4:

Integrator Coefficients Feed-Forward Coefficients

a1=0.25 b0=1

a2=1 b1=3 b2=1

Table 3.4 Coefficient of proposed SDM

23

Under the coefficients, the modified NTF becomes:

( )

5 . 0 25 . 1 ) 1

(

₂

2 '

+

−

= −

z z

Z z

NTF

(3.13)

It cause a slightly change of the NTF pole and it will not degrade the SNR significantly.

The ideal Output spectrum of 8192-point FFT with 8k input signal is shown at Figure 3.7, the simulation result reveals that the SFDR exceed 78dB.

Fig.3.7 Ideal 8192 point FFT of proposed SDM architecture

24

3.3 Non-idealities Considerations

The above simulations show an ideal model of the second-order sigma-delta modulator. However, there are some non-ideal effects in analog circuit design and it is unavoidable, so we must evaluate the non-ideal effect to make our designs meet the desired margin.

3.3.1 Gain requirement

The transfer function of an ideal integrator:

1

However, the gain of OTA cannot be infinite in circuit design, when a finite gain is A in an OTA, the transfer function will become:

1

Figure 3.8 a switched-capacitance circuit in SDM

25

A finite gain of OTA means that the pole of the H(Z) will depart from unit circle, and when the distance of the zero exceed about

1 1 S I

C C OSR π

⋅

, the noise attenuation of NTF begins to degrade, so the lower limit of A is about 40 dB[10].

3.3.2 Settling of the OTA

In a switched-capacitance circuit, the loop filter can be separately into two parts, namely the sampling period and the integration period, as shown at Figure 3.9:

Figure 3.9 Sampling and integration period of a loop filter

When the loop filter is at integration period, the settling behavior of the OTA can be derived as the Figure 3.10. A slewing is happened when a large output change of the loop filter. When the differential input voltage is less than

2 V

_OV, the OTA enters linear settling region. Because of the speed limitation of the OTA, settling error will occur at the end of integration period as the Figure 3.10 shown, so we must take settling error into consideration when designing OTA.

26

Figure 3.10 Settling behavior of OTA

3.3.3 Capacitor Sizing

The input-referred thermal noise of the integrator is:

s

n

C

V

² =

KT

, (3.16)

Where Cs is sampling capacitor of the integrator.

With an oversampling ratio of OSR, the in-band KT/C noise:

And if for a full scale input amplitude, the in-band noise power must be at least 85dB below the signal power:

2

27

Ö

^C

^{S >8}

^{KT V}

^⋅_DD⁽

^SNR

^2⋅

( ^OSR

^_

^peak )

⁾ (3.19)

Ö It can be calculated that Cs> 0.163pF

The simulation result of first sapling capacitor is shown at Figure 3.11, from the figure we choose Cs1=0.5pF for safety noise margin.

Figure 3.11 Simulation result of the first sampling capacitor

The KT/C noise at the input of the second integrator is shaped by the first-order noise shaping, so that Cs2 can be scaled down since its effect of thermal noise is fewer. In this SDM system, we choose C^S2=0.2pF.

28

Chapter 4

Circuit Implementation

The proposed sigma-delta modulator has been fabricated in TSMC 0.18um single-poly six-metal CMOS process. The circuitry is operating at a supply voltage of 1 volt. The sub-blocks which including OTA, comparator, clock generator and switched capacitor circuit in SDM are described in Section 4.1. In Section 4.2, the simulation results of sub-blocks and whole SDM are presented. In Section 4.3, the final layout design of proposed SDM is then described.

4.1 Transistor Level Design

After considering the system parameters and non-idealities of proposed SDM, the following is the circuit implementation. The sub-circuit of each component in this modulator is presented including OTA, 1-bit quantizer, clock generator, switched capacitor circuit, respectively.

4.1.1 Differential OTA in loop filter

The OTA in loop filter is the analog block which consumes the most power, and it also dominant the performance of the modulator, so it is the most critical building block that we must design it seriously.

29

In previous researches, a single stage OTA must used because it doesn’t have to waste extra current in driving the compensated capacitance[4], and although the class-AB OTA is the most widely used OTA architecture when designing a low power SDM, it requires extra paths to drive the transistor of output stage[9]; Therefore, a single-stage class-A Amplifier with positive feedback to increase its gain is used in this design, as shown in Figure 4.1, We use PMOS as the input transistor because of two reasons:

(1)The input common mode voltage (ICM) is low than Vt

(2)The noise of PMOS input pair is smaller than NMOS

Figure 4.1 Single Stage Class-A OTA with positive feedback

An OTA in loop filter works at the integration period, and the settling behavior of the OTA can be divided into two parts, the slewing and the settling time. A slewing is happened when a large output change of the loop filter. When the differential input voltage is less than 2

V

_OV, the OTA enters linear settling region, with a 2MHz clock, the integration period is 250ns, so that:

30

ns T

T

_SR

+

_settling

= 250

(4.1)

A trade-off between the slewing time and linear settling time means different settling behavior of the OTA. The proposed optimization technique is to find the optimization of slewing-settling trade-off as shown in Figure 4.2, thus the total current consumption of the OTA can be minimized, and the analysis is followed.

V

OV

2

Figure 4.2 trade-off between slewing and linear settling

The slewing behavior is related to the current of output path:

SR

For a load capacitance of 2.5pf and a v=0.5, we can derive that:

31

The speed of the OTA settling is depend on its time constant, therefore , the unit gain bandwidth, therefore the input path current of the OTA, we set the linear settling period is larger than 10 time constant , thus the settling error is lower than 85dB.

Therefore,

T

_linear

≥ 10 τ

(4.4)

So, the unit-gain bandwidth:

linear

From (3.16) and (3.21) we can know that the total current consumption of the OTA:

( )

32

Therefore, we can optimize the OTA to minimize the total current consumption of the OTA by plotting it as a function of the slewing time such as Figure 4.3:

Figure 4.3 Slewing time versus total current of the OTA

From this figure, we know that the minimum current occurs at T^SR=160~170ns.

However, when TSR=170 ns is used, and we can calculate that:

T uA I x

linear

in 0.78 10 ¹³ 1.3

=

= ⁻ (4.10)

uA T

I x

SR

out 4.49 10 ¹³ 2.56

=

= ⁻ (4.11)

Then the coefficient B of the OTA is about 3, which departs from our assumption, so we must decrease the TSR so that the B is close to 4, we modify the slewing time so that T^SR=130ns as Figure 4.4 plots, therefore:

T uA I x

SR

out = 4.49 10⁻¹³ =3.45 (4.12)

33

Figure 4.4 modification of the slewing time

Therefore, the current consumption of our calculation can be simplified as Figure 4.5:

Figure 4.5 Current consumption of first OTA

34

The transistor size summary of the first OTA is shown at Table 4.1:

Transistor W L M

M1,2 1 0.8 4 M3,4 0.6 0.8 1 M5,6 0.48 0.8 1 M7,8 0.6 0.8 4

M9,10 4.16 1.5 1

M11,12 4.16 1.5 3

M13 2 1.5 8 Table 4.1 Device ratio summary of first OTA

The decision of the size is based on the following principles:

(1) Tune M13 that the current of M13 as we want and the overdrive voltage= 100mv.

(2) Tune M1, M2 to meet the gm and Fu specification.

(3) Tune M3~M6 to adjust the second pole, and the positive feedback gain is 0.8 at the same time.

(4) Tune M7, M8 to meet the assumption that B=4 we used above.

(5) Tune M9~12 that the output stage has a output closed to 0.5Vdd, and the gain of the whole OP exceed 50dB.

A larger length of the transistor is used (0.8um) is because that the overdrive voltage, low current and corner consideration. In order to achieve a low-power and stable OTA, some area is trade for our requirement.

The design procedure of the second stage OTA is similar to the first one, except that B=4 we used in first OTA is adjust to B=2 in second stage due to the parasitic capacitance at the output of this OTA is smaller than the first OTA, thus the power consumption can be lowered as Figure 4.6 is shown:

35

Figure 4.6 Current consumption of second OTA

The performance summary of the first OTA is listed at Table 4.2:

Specification Result Gain 61.9dB

Unit Gain Bandwidth 22.2MHz

Phase Margin 37°

Slew Rate 3.8 v/us

Settling Time Constant 12ns

Output Swing 800mv

Power Dissipation 10.14uW

Table 4.2 Summary of first OTA simulation results

The comparison of the two OTA for a 2.5pf loading capacitance is listed at Table 4.3, and the frequency response of the first OTA is shown at Figure 4.7:

Gain(dB) GBW Total Power

OTA1 61.9dB 22.2MHz 10.14uW

OTA2 61.6dB 15.1MHz 6.67uW

Table 4.3 Performance comparison of the two OTA

36

Figure 4.7 Frequency Response of first OTA

The comparison of the OTA before and after this current optimization technique is listed at Table 4.4. It shows that the total current consumption is form 14.5uA to 10.2 uA. It means at least 30.1% current reduction in OTA.

OP Architecture

Fs (MHz)

Table 4.4 Comparison before/after current optimization

Because of the differential architecture of the OTA, so we must have a CMFB circuit, thus a dynamic CMFB circuit like Figure 4.8 is used because it is the most power-efficient. In the CMFB circuit, Vcmo is set to 0.5v and only the switch connect to CMFB use CMOS switch, other switches is PMOS switch only.

37

Figure 4.8 Dynamic CMFB circuit

The device ratio summary we used in CMFB circuit is listed at Table 4.4, and the transient response of the first OTA and CMFB circuit is shown below at Figure 4.9:

Transistor Type W/L Transistor Type W/L

PMOS 2/0.6 NMOS 1/0.3 Capacitor Value Capacitor Value

C1 0.1pf C2 0.4pf Table 4.5 CMFB circuit summary

Figure 4.9 Transient Response of first OTA output

38

4.1.2 1-bit Quantizer

The 1-bit quantizer is realized with a comparator and a SR latch, shown at Figure 4.10.

The comparator is a dynamic comparator to lower average power consumption, when CLK is high, the comparator compares the two input voltage, then the comparison result is followed by the SR latch behind the comparator.

Figure 4.10 a power-efficient 1-bit quantizer

The simulation result of the 1-bit quantizer is shown at Figure 4.11, for a 16KHz input signal and a clock of 4MHz, the quantizer compare the input signal correctly.

After the simulation result, the device ratio of the quantizer is listed at Table 4.6.

Figure 4.11 Simulation results of the 1-bit quantizer

39

Width(um) Length(um) M

M1a,b 2.5 0.5 2

M2a,b~M5a,b 0.5 0.18 1

M6a,b 0.5 0.18 5 M7a,b 0.5 0.18 1 M8a,b 0.5 0.18 5 M9a,b 0.5 0.18 1

Table 4.6 Quantizer transistor size summary

Table 4.6 Quantizer transistor size summary

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