Capacitor Sizing

The input-referred thermal noise of the integrator is:

s

n

C

V

² =

KT

, (3.16)

Where Cs is sampling capacitor of the integrator.

With an oversampling ratio of OSR, the in-band KT/C noise:

And if for a full scale input amplitude, the in-band noise power must be at least 85dB below the signal power:

2

27

Ö

^C

^{S >8}

^{KT V}

^⋅_DD⁽

^SNR

^2⋅

( ^OSR

^_

^peak )

⁾ (3.19)

Ö It can be calculated that Cs> 0.163pF

The simulation result of first sapling capacitor is shown at Figure 3.11, from the figure we choose Cs1=0.5pF for safety noise margin.

Figure 3.11 Simulation result of the first sampling capacitor

The KT/C noise at the input of the second integrator is shaped by the first-order noise shaping, so that Cs2 can be scaled down since its effect of thermal noise is fewer. In this SDM system, we choose C^S2=0.2pF.

28

Chapter 4

Circuit Implementation

The proposed sigma-delta modulator has been fabricated in TSMC 0.18um single-poly six-metal CMOS process. The circuitry is operating at a supply voltage of 1 volt. The sub-blocks which including OTA, comparator, clock generator and switched capacitor circuit in SDM are described in Section 4.1. In Section 4.2, the simulation results of sub-blocks and whole SDM are presented. In Section 4.3, the final layout design of proposed SDM is then described.

4.1 Transistor Level Design

After considering the system parameters and non-idealities of proposed SDM, the following is the circuit implementation. The sub-circuit of each component in this modulator is presented including OTA, 1-bit quantizer, clock generator, switched capacitor circuit, respectively.

4.1.1 Differential OTA in loop filter

The OTA in loop filter is the analog block which consumes the most power, and it also dominant the performance of the modulator, so it is the most critical building block that we must design it seriously.

29

In previous researches, a single stage OTA must used because it doesn’t have to waste extra current in driving the compensated capacitance[4], and although the class-AB OTA is the most widely used OTA architecture when designing a low power SDM, it requires extra paths to drive the transistor of output stage[9]; Therefore, a single-stage class-A Amplifier with positive feedback to increase its gain is used in this design, as shown in Figure 4.1, We use PMOS as the input transistor because of two reasons:

(1)The input common mode voltage (ICM) is low than Vt

(2)The noise of PMOS input pair is smaller than NMOS

Figure 4.1 Single Stage Class-A OTA with positive feedback

An OTA in loop filter works at the integration period, and the settling behavior of the OTA can be divided into two parts, the slewing and the settling time. A slewing is happened when a large output change of the loop filter. When the differential input voltage is less than 2

V

_OV, the OTA enters linear settling region, with a 2MHz clock, the integration period is 250ns, so that:

30

ns T

T

_SR

+

_settling

= 250

(4.1)

A trade-off between the slewing time and linear settling time means different settling behavior of the OTA. The proposed optimization technique is to find the optimization of slewing-settling trade-off as shown in Figure 4.2, thus the total current consumption of the OTA can be minimized, and the analysis is followed.

V

OV

2

Figure 4.2 trade-off between slewing and linear settling

The slewing behavior is related to the current of output path:

SR

For a load capacitance of 2.5pf and a v=0.5, we can derive that:

31

The speed of the OTA settling is depend on its time constant, therefore , the unit gain bandwidth, therefore the input path current of the OTA, we set the linear settling period is larger than 10 time constant , thus the settling error is lower than 85dB.

Therefore,

T

_linear

≥ 10 τ

(4.4)

So, the unit-gain bandwidth:

linear

From (3.16) and (3.21) we can know that the total current consumption of the OTA:

( )

32

Therefore, we can optimize the OTA to minimize the total current consumption of the OTA by plotting it as a function of the slewing time such as Figure 4.3:

Figure 4.3 Slewing time versus total current of the OTA

From this figure, we know that the minimum current occurs at T^SR=160~170ns.

However, when TSR=170 ns is used, and we can calculate that:

T uA I x

linear

in 0.78 10 ¹³ 1.3

=

= ⁻ (4.10)

uA T

I x

SR

out 4.49 10 ¹³ 2.56

=

= ⁻ (4.11)

Then the coefficient B of the OTA is about 3, which departs from our assumption, so we must decrease the TSR so that the B is close to 4, we modify the slewing time so that T^SR=130ns as Figure 4.4 plots, therefore:

T uA I x

SR

out = 4.49 10⁻¹³ =3.45 (4.12)

33

Figure 4.4 modification of the slewing time

Therefore, the current consumption of our calculation can be simplified as Figure 4.5:

Figure 4.5 Current consumption of first OTA

34

The transistor size summary of the first OTA is shown at Table 4.1:

Transistor W L M

M1,2 1 0.8 4 M3,4 0.6 0.8 1 M5,6 0.48 0.8 1 M7,8 0.6 0.8 4

M9,10 4.16 1.5 1

M11,12 4.16 1.5 3

M13 2 1.5 8 Table 4.1 Device ratio summary of first OTA

The decision of the size is based on the following principles:

(1) Tune M13 that the current of M13 as we want and the overdrive voltage= 100mv.

(2) Tune M1, M2 to meet the gm and Fu specification.

(3) Tune M3~M6 to adjust the second pole, and the positive feedback gain is 0.8 at the same time.

(4) Tune M7, M8 to meet the assumption that B=4 we used above.

(5) Tune M9~12 that the output stage has a output closed to 0.5Vdd, and the gain of the whole OP exceed 50dB.

A larger length of the transistor is used (0.8um) is because that the overdrive voltage, low current and corner consideration. In order to achieve a low-power and stable OTA, some area is trade for our requirement.

The design procedure of the second stage OTA is similar to the first one, except that B=4 we used in first OTA is adjust to B=2 in second stage due to the parasitic capacitance at the output of this OTA is smaller than the first OTA, thus the power consumption can be lowered as Figure 4.6 is shown:

35

Figure 4.6 Current consumption of second OTA

The performance summary of the first OTA is listed at Table 4.2:

Specification Result Gain 61.9dB

Unit Gain Bandwidth 22.2MHz

Phase Margin 37°

Slew Rate 3.8 v/us

Settling Time Constant 12ns

Output Swing 800mv

Power Dissipation 10.14uW

Table 4.2 Summary of first OTA simulation results

The comparison of the two OTA for a 2.5pf loading capacitance is listed at Table 4.3, and the frequency response of the first OTA is shown at Figure 4.7:

Gain(dB) GBW Total Power

OTA1 61.9dB 22.2MHz 10.14uW

OTA2 61.6dB 15.1MHz 6.67uW

Table 4.3 Performance comparison of the two OTA

36

Figure 4.7 Frequency Response of first OTA

The comparison of the OTA before and after this current optimization technique is listed at Table 4.4. It shows that the total current consumption is form 14.5uA to 10.2 uA. It means at least 30.1% current reduction in OTA.

OP Architecture

Fs (MHz)

Table 4.4 Comparison before/after current optimization

Because of the differential architecture of the OTA, so we must have a CMFB circuit, thus a dynamic CMFB circuit like Figure 4.8 is used because it is the most power-efficient. In the CMFB circuit, Vcmo is set to 0.5v and only the switch connect to CMFB use CMOS switch, other switches is PMOS switch only.

37

Figure 4.8 Dynamic CMFB circuit

The device ratio summary we used in CMFB circuit is listed at Table 4.4, and the transient response of the first OTA and CMFB circuit is shown below at Figure 4.9:

Transistor Type W/L Transistor Type W/L

PMOS 2/0.6 NMOS 1/0.3 Capacitor Value Capacitor Value

C1 0.1pf C2 0.4pf Table 4.5 CMFB circuit summary

Figure 4.9 Transient Response of first OTA output

38

4.1.2 1-bit Quantizer

The 1-bit quantizer is realized with a comparator and a SR latch, shown at Figure 4.10.

The comparator is a dynamic comparator to lower average power consumption, when CLK is high, the comparator compares the two input voltage, then the comparison result is followed by the SR latch behind the comparator.

Figure 4.10 a power-efficient 1-bit quantizer

The simulation result of the 1-bit quantizer is shown at Figure 4.11, for a 16KHz input signal and a clock of 4MHz, the quantizer compare the input signal correctly.

After the simulation result, the device ratio of the quantizer is listed at Table 4.6.

Figure 4.11 Simulation results of the 1-bit quantizer

39

Width(um) Length(um) M

M1a,b 2.5 0.5 2

M2a,b~M5a,b 0.5 0.18 1

M6a,b 0.5 0.18 5 M7a,b 0.5 0.18 1 M8a,b 0.5 0.18 5 M9a,b 0.5 0.18 1

Table 4.6 Quantizer transistor size summary

4.1.3 Clock Generator

The on-chip clock generator is shown as Figure 4.12, an external clock input signal is buffered and then two non-overlapping clock phases are generated. To avoid the signal dependent charge injection, two delayed clocks, i.e., C1d and C2d, are also be generated.

Figure 4.12 Clock generator circuit

40

The output of the clock generator are four different clock phases, the simulation results are shown at Figure 4.13, and Figure 4.14 shows that the phase one and two are non-overlapped each other.

Figure 4.13 Output of the clock generator

Figure 4.14 Four non-overlapping phases

41

4.1.4 Switches

The current of a MOS switch:

(

_{GS DS}

)

_DS Therefore, the turn-on resistance of the NMOS, PMOS and CMOS switches can be derived as:

It is clearly that:

(1) Use NMOS switch as much as we can due to the area consideration.

(2) When the input signal of the MOS switch is large, us CMOS switch.

(3) Large ratio of W/L can lower the turn-on resistance of the switches, but have larger area and parasitic capacitance.

42

4.2 Modulator Design and Simulation

A second-order sigma-delta modulator with CIFF topology is done as Figure 4.15:

Figure 4.15 2^nd order CIFF SDM

The Sigma-Delta modulator is implemented by fully differential input and output signal, the building blocks in this figure are done as we described in previous sections.

With a 8k input signal and a -6dB full scale input amplitude, the simulated time-domain integrator output signal and the frequency-domain output spectrum can be observed by Figure 4.16 and Figure 4.17, respectively:

43

Figure 4.16 output signal of input and two integrator outputs

Figure 4.17 8192-point output FFT of the SDM

44

The FFT shows that the SNR=69.1, SNDR=68.4 and the SFDR=77.2dB, and the dynamic range (DR) is about 72dB as Figure 4.17 and Figure 4.18 shows.

Figure 4.18 Dynamic range of the SDM

Beside this, because of the possibly process variation, we simulate the SNR results of four corners, the corner simulation results are summarized at Table 4.7.

Unit(dB) TT FF SS SF FS

SNR 69.1 60.2 63.0 58.6 61.2

SNDR 68.4 56.9 61.1 56.6 60.3

Table 4.7 Comparison of the simulation results of four corners

45

4.3 Layout Level Design

A physical design in the context of integrated circuit is referred to as layout. Effects of parasitic components and mismatching will damage the performance of the chip, so layouts must be considered heavily in design process. Several principles of layout must be obeyed to minimize cross-talk, mismatches include (a) multi-finger transistors (b) symmetry (c) dummy cell (d) common centroid.

The diagram of layouts are shown at Figure 4.20, there are twenty-two I/O pads, including a pair of differential inputs, a pair of modulator outputs, a input clock, five reference voltages and eleven VDD/GND lines. The I/O pad description is listed at Table 4.7. This circuit is fabricated in a 0.18um 1P6M 1.8V standard CMOS technology with MIM process. The chip area is 0.665

mm including ESD-protection

² I/O pads and 0.05

mm for the core area.

²

Figure 4.19 Diagram of the layout

46

The proposed chip is fabricated in a 0.18um 1P6M 1.8V standard CMOS technology with MIM process. And the package type is S/B type 24 pin, as shown in Figure 4.21 where the actual chip photograph is shown at Figure 4.22. The pin assignment is listed at Table 4.8.

Figure 4.20 Diagram of the 24 pin DIP package

Figure 4.21 Die photograph

47

Pin Name Description

1 AGND Analog circuit ground

2 vrefn Reference voltage

3 NC No connection

4 vrefp Reference voltage

5 AGNDPAD ESD PAD ground

6 DGNDPAD ESD PAD ground

7 DGRGND Digital circuit guard ring

8 Ck_out input clock signal

9 Ck Clock signal output

10 NC No connection

11 DGND Digital circuit ground

12 DVDD Digital circuit VDD

13 Vo2 Differentail output signal

14 Vo1 Differentail output signal

15 DVDDPAD ESD PAD Digital VDD

16 AVDDPAD ESD PAD Analog VDD

17 AGRVDD Analog circuit guard ring

18 AGRGND Analog circuit guard ring

19 Vcmo Reference voltage

20 Vcmi Reference voltage

21 vb Reference voltage

22 AVDD Analog circuit VDD

23 Vin1 Differential input signal

24 Vin2 Differential input signal

Table 4.8 Pin Assignments

The 8192-point FFT of the post simulation result is shown as Figure 4.23 with an input frequency of 4k and the input amplitude is -6dB of full scale. This spectrum shows the SNR is 63.4dB while the SNDR is 58.7dB, and the comparison of pre-simulation and post-simulation is listed at Table 4.9.

48

Figure 4.22 8192-point FFT of the post-simulation result

Unit(dB) Pre-Simulation

Post-Simulation

SNR 69.1 63.4 SNDR 68.4 58.7

Table 4.9 Comparisons of pre & post simulation

Finally, the performance summary of the proposed SDM is listed at Table 4.10, the simulation result shows that the peak SNR is 63.4dB for a 16 KHz signal bandwidth and sampling frequency of 2MHz. With a 0.18um technology, the average power consumption is only 18uW.

Technology 0.18um VDD 1V Signal Bandwidth 16KHz

Sampling Frequency 2MHz

Peak SNR 63.4dB

Power Consumption 18uW

Layout Core Area Size 240um x 210um

Table 4.10 Summary of the proposed SDM

49

4.4 Comparison

The comparison of this work and previous researches are listed at Table 4.11 and Figure 4.24, in order to compare the design result, we define the figure-of-merit as:

⎟ ⎠

Table 4.11 Comparison of this work

50

The FOM comparison shows that the power consumption of proposed SDM is lowest compared to other researches while the FOM is still above average. The SNR versus power comparison is shown at Figure 4.24.

Performance Comparison

Figure 4.23 SNR versus power comparison comparisons

51

Chapter 5

Testing Setup and Measurement

A testing setup for fabricated chip is presented in this chapter. And a costumed designed printed circuit board (PCB) is designed and fabricated to integrate the targeting prototype chip in order to measure the performance metrics of proposed design. Following by the setup for measurement, the experimental results is presented and discussed. And the performance summary is summarized in the end of this chapter.

5.1 Testing Environment Setup

The testing environment setup is shown as Figure 5.1. It includes a printed circuit board (PCB) including a device under test (DUT) board, a logic analyzer (Agilent 16902A), an audio signal generator (Stanford Research DS360), a power supply (E3610A), a mixed-signal oscilloscope (Agilent 54641D) and a PC to analyze the output bit stream of proposed modulator.

52

Figure5.1 experimental test chip

As shown in Figure 5.1, the input signal is generated by audio signal generator, and the digit output is fed to the logic analyzer, then load to PC for MATLAB simulation. A PCB board combines the clock generator (a crystal oscillator) and a device under test (DUT) to measure the chip. The photograph of the measurement environment is shown at Figure 5.2.

Figure 5.2 Photograph of the measurement environment

53

5.2 Measurement Result

The measurement result of proposed chip is failed. The probably reason is that the transistor size of the output buffer is too small to push the ESD PAD and the parasitic capacitance of the packages as Figure 5.3 shows.

Figure 5.3 Probably problem of output buffers

Stage1 Stage 2

1um/0.18um 4um/0.18um

Table 5.1 Output buffer device ratio summary

Due to the problem of this layout, we modify the design as Figure 5.4, and it is modified by following principles:

1. ESD protection for analog input signals while the output pad is pure pad to reduce chip area and measuring core power of proposed SDM.

2. Wider metal for power lines.

3. Independent PAD for different supply voltage: AVDD, DVDD, IOVDD to measure the power respectively.

4. A larger output buffer of six stages is used, the device ratio is listed at Table 5.2.

54

Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6

1/0.18um 3/0.18um 9/0.18um 27/0.18um 81/0.18um 243/0.18um

Table 5.2 the modified output buffer device ratio summary

Figure 5.4 modified version of layout

We also take the measurement of the core power into considerations of the modified version of layout, we use three independent supply voltage pads for analog circuits (part A), clock generator circuit (part B) and output buffer (part C), respectively. The

55

simulation results of the power consumption for three parts are listed at Table 5.3, and the post layout simulation results are shown at Figure 5.5. The simulated result of SNR and SNDR are listed at Table 5.4.

A A+B A+B+C

Power(uW) 14.3 18.0 25.4

Table 5.3 Power consumption for three parts circuits

Figure 5.5 8192-point FFT of the modified layout

Unit(dB) Pre-Simulation

Post-Simulation Modified layout

SNR 69.1 63.4

61.3

SNDR 68.4 58.7

57.9

Table 5.4 Comparison of this modified layout

56

5.3 Summary

The circuit present in this thesis is implemented by design considerations described in Chapter 3 and circuit design implementation in Chapter 4.This work emphasized the complete design flow for low-power design and the current optimization of the OTA by discussing the slewing-settling trade-off of it.

The predicted resolution of the SDM is 11.2 bits (68.4dB), and the post-simulation result is 9.6 bits (58.7dB). It can be used in the audio electrical portable devices applications.

57

Chapter 6 Conclusions

This thesis describes the design and implementation of a low-power second-order sigma-delta modulator (SDM) with CIFF structure for audio-band applications. A single stage class-A positive feedback OTA with current optimization has been presented to lower the power of SDM.

Using 0.18um CMOS technology, this modulator achieves SNR of 63.4dB with 16KHz bandwidth. With a moderate target signal-noise-ratio (SNR), it is suitable for battery-based operation system, such as mp3 players, biomedical electronic and digital hearing aid instrument applications. The simulation results show that the power consumption is 18uW. It is the lowest compared to references [2]-[9].

The future work is to integrate the modified version from the problems of proposed SDM. A low-power measurement consideration is included in the modified SDM design consideration.

After this modified layout, a high resolution sigma-delta modulator can be done using the same method of optimizing the power of the OTA.

58

References

[1] J.Silva, U.Moon, J.Steensgaard and G.C.Temes,” Wideband low-distortion delta-sigma ADC topology,” Electronics Letters, Vol. 37, pp.737-738, June 2001.

[2] J.Sauerbrey, T.Tille, D. Schmitt-Landsiedel, R.Thewes, ”A 0.7V MOSFET-Only Switched-Opamp Modulator in Standard Digital CMOS Technology”, IEEE Journal of Solid-State Circuits,” Vol. 37, No. 12, Dec 2002.

[3] Yamu Hu; Zhijun Lu; Sawan, M., “A low-voltage 38μW sigma-delta modulator dedicated to wireless signal recording applications,” Circuits and Systems, ISCAS 03, vol.1, pp.1073-1076, May 2003

[4] L.Yao, Michael S.J.Steyaert, W.Sansen, “A 1v 140uW 88dB Audio Sigma-Delta Modulator in 90nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, Nov 2004.

[5] G.Ahn, M.E.Brown , N.Ozaki, H.Yiura, K.Yamamura, K.Hamashita, K.Takasuka, G.C.Temes, “A 0.6V 82dB Delta-Sigma Audio ADC Usgin Switched-RC Integrators,” IEEE Journal of Solid-State Circuits, Vol.40 , No. 12, Dec 2005.

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[8] Mahmoodi, A.; Joseph, D, “Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors,” IMATC 2007, pp. 1-6, May 2007.

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[9] J. Roh, S.Byun, Y.Choi, H.Roh, Y.Kim, J.Kwon, “A 0.9V 60uW 1 bit Fourth-Order Delta-Sigma Modulator with 83dB Dynamic Range,” IEEE Journal of Solid-State Circuits, Vol.43, No.2, Feb 2008.

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[12] Roubik Gregorian, ”Introduction to CMOS OP-AMPS and Comparators,” John Wiley & Sons, 1999.

[13] Libin Yao; Steyaert, M.; Sansen, “0.8-V, 8-μW, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load,” Solid-State Circuits Conference, pp.297-300, Sep.

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[14] Taha, I.Y.; Ahmadi, M.; Miller, W.C,”A sigma-delta modulator for digital hearing instruments using 0.18μm CMOS technology,”System-oon-Chip for Real-Time Applications, pp.233-2369, July 2004.

[15] Yavari, M.; Shoaei, O.; Afzali-Kusha, ”A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25-μm CMOS,” Circuits and Systems,2003. ISCAS, vol. 1, pp. 1045-1048, May 2003.

[16] Carrillo, J.M.; Montecelo, M.A.; Neubauer, H.; Hauer, H.; Duque-Carrillo, J.F, ”1.8-V second-order ΣΔ modulator in 0.18-μm CMOS technology,” Circuit Theory and Design, vol. 1, pp. 197-200, Sept 2005.

[17] Ranjbar, M.; Lahiji, G.R.; Oliaei, O, “A low power third order delta-sigma

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