Chapter 4 Circuit Implementation
4.1 Transistor Level Design
4.1.1 Differential OTA in loop filter
4.1 Transistor Level Design
After considering the system parameters and non-idealities of proposed SDM, the following is the circuit implementation. The sub-circuit of each component in this modulator is presented including OTA, 1-bit quantizer, clock generator, switched capacitor circuit, respectively.
4.1.1 Differential OTA in loop filter
The OTA in loop filter is the analog block which consumes the most power, and it also dominant the performance of the modulator, so it is the most critical building block that we must design it seriously.
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In previous researches, a single stage OTA must used because it doesn’t have to waste extra current in driving the compensated capacitance[4], and although the class-AB OTA is the most widely used OTA architecture when designing a low power SDM, it requires extra paths to drive the transistor of output stage[9]; Therefore, a single-stage class-A Amplifier with positive feedback to increase its gain is used in this design, as shown in Figure 4.1, We use PMOS as the input transistor because of two reasons:
(1)The input common mode voltage (ICM) is low than Vt
(2)The noise of PMOS input pair is smaller than NMOS
Figure 4.1 Single Stage Class-A OTA with positive feedback
An OTA in loop filter works at the integration period, and the settling behavior of the OTA can be divided into two parts, the slewing and the settling time. A slewing is happened when a large output change of the loop filter. When the differential input voltage is less than 2
V
OV, the OTA enters linear settling region, with a 2MHz clock, the integration period is 250ns, so that:30
ns T
T
SR+
settling= 250
(4.1)A trade-off between the slewing time and linear settling time means different settling behavior of the OTA. The proposed optimization technique is to find the optimization of slewing-settling trade-off as shown in Figure 4.2, thus the total current consumption of the OTA can be minimized, and the analysis is followed.
V
OV2
Figure 4.2 trade-off between slewing and linear settling
The slewing behavior is related to the current of output path:
SR
For a load capacitance of 2.5pf and a v=0.5, we can derive that:
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The speed of the OTA settling is depend on its time constant, therefore , the unit gain bandwidth, therefore the input path current of the OTA, we set the linear settling period is larger than 10 time constant , thus the settling error is lower than 85dB.
Therefore,
T
linear≥ 10 τ
(4.4)So, the unit-gain bandwidth:
linear
From (3.16) and (3.21) we can know that the total current consumption of the OTA:
( )
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Therefore, we can optimize the OTA to minimize the total current consumption of the OTA by plotting it as a function of the slewing time such as Figure 4.3:
Figure 4.3 Slewing time versus total current of the OTA
From this figure, we know that the minimum current occurs at TSR=160~170ns.
However, when TSR=170 ns is used, and we can calculate that:
T uA I x
linear
in 0.78 10 13 1.3
=
= − (4.10)
uA T
I x
SR
out 4.49 10 13 2.56
=
= − (4.11)
Then the coefficient B of the OTA is about 3, which departs from our assumption, so we must decrease the TSR so that the B is close to 4, we modify the slewing time so that TSR=130ns as Figure 4.4 plots, therefore:
T uA I x
SR
out = 4.49 10−13 =3.45 (4.12)
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Figure 4.4 modification of the slewing time
Therefore, the current consumption of our calculation can be simplified as Figure 4.5:
Figure 4.5 Current consumption of first OTA
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The transistor size summary of the first OTA is shown at Table 4.1:
Transistor W L M
M1,2 1 0.8 4 M3,4 0.6 0.8 1 M5,6 0.48 0.8 1 M7,8 0.6 0.8 4
M9,10 4.16 1.5 1
M11,12 4.16 1.5 3
M13 2 1.5 8 Table 4.1 Device ratio summary of first OTA
The decision of the size is based on the following principles:
(1) Tune M13 that the current of M13 as we want and the overdrive voltage= 100mv.
(2) Tune M1, M2 to meet the gm and Fu specification.
(3) Tune M3~M6 to adjust the second pole, and the positive feedback gain is 0.8 at the same time.
(4) Tune M7, M8 to meet the assumption that B=4 we used above.
(5) Tune M9~12 that the output stage has a output closed to 0.5Vdd, and the gain of the whole OP exceed 50dB.
A larger length of the transistor is used (0.8um) is because that the overdrive voltage, low current and corner consideration. In order to achieve a low-power and stable OTA, some area is trade for our requirement.
The design procedure of the second stage OTA is similar to the first one, except that B=4 we used in first OTA is adjust to B=2 in second stage due to the parasitic capacitance at the output of this OTA is smaller than the first OTA, thus the power consumption can be lowered as Figure 4.6 is shown:
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Figure 4.6 Current consumption of second OTA
The performance summary of the first OTA is listed at Table 4.2:
Specification Result Gain 61.9dB
Unit Gain Bandwidth 22.2MHz
Phase Margin 37°
Slew Rate 3.8 v/us
Settling Time Constant 12ns
Output Swing 800mv
Power Dissipation 10.14uW
Table 4.2 Summary of first OTA simulation results
The comparison of the two OTA for a 2.5pf loading capacitance is listed at Table 4.3, and the frequency response of the first OTA is shown at Figure 4.7:
Gain(dB) GBW Total Power
OTA1 61.9dB 22.2MHz 10.14uW
OTA2 61.6dB 15.1MHz 6.67uW
Table 4.3 Performance comparison of the two OTA
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Figure 4.7 Frequency Response of first OTA
The comparison of the OTA before and after this current optimization technique is listed at Table 4.4. It shows that the total current consumption is form 14.5uA to 10.2 uA. It means at least 30.1% current reduction in OTA.
OP Architecture
Fs (MHz)
Table 4.4 Comparison before/after current optimizationBecause of the differential architecture of the OTA, so we must have a CMFB circuit, thus a dynamic CMFB circuit like Figure 4.8 is used because it is the most power-efficient. In the CMFB circuit, Vcmo is set to 0.5v and only the switch connect to CMFB use CMOS switch, other switches is PMOS switch only.
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Figure 4.8 Dynamic CMFB circuit
The device ratio summary we used in CMFB circuit is listed at Table 4.4, and the transient response of the first OTA and CMFB circuit is shown below at Figure 4.9:
Transistor Type W/L Transistor Type W/L
PMOS 2/0.6 NMOS 1/0.3 Capacitor Value Capacitor Value
C1 0.1pf C2 0.4pf Table 4.5 CMFB circuit summary
Figure 4.9 Transient Response of first OTA output
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4.1.2 1-bit Quantizer
The 1-bit quantizer is realized with a comparator and a SR latch, shown at Figure 4.10.
The comparator is a dynamic comparator to lower average power consumption, when CLK is high, the comparator compares the two input voltage, then the comparison result is followed by the SR latch behind the comparator.
Figure 4.10 a power-efficient 1-bit quantizer
The simulation result of the 1-bit quantizer is shown at Figure 4.11, for a 16KHz input signal and a clock of 4MHz, the quantizer compare the input signal correctly.
After the simulation result, the device ratio of the quantizer is listed at Table 4.6.
Figure 4.11 Simulation results of the 1-bit quantizer
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Width(um) Length(um) M
M1a,b 2.5 0.5 2
M2a,b~M5a,b 0.5 0.18 1
M6a,b 0.5 0.18 5 M7a,b 0.5 0.18 1 M8a,b 0.5 0.18 5 M9a,b 0.5 0.18 1
Table 4.6 Quantizer transistor size summary