Conclusion and Future Work

In order to reduce the difficulty in designing the corresponding LO module, another mixer with the integrated LO frequency doubler has also been proposed. The schematic of the frequency doubler is shown in Fig. A - 23. We also incorporate a constant-gm bias circuit, as shown in Fig. A - 24, to generate the biasing voltage. The chip layout of the proposed wide-IF band mixer with LO-doubler is shown in Fig. A - 25. The chip size is 1.400 × 1.100 mm² including all pads and bypass capacitances.

Fig. A - 23 Schematic of the frequency doubler

Fig. A - 24 Schematic of the constant-gm bias circuit

Fig. A - 25 Chip Layout of the proposed wide-IF band mixer with LO frequency doubler

Reference

[1] IEEE 802.15 WPAN High Rate Alternative PHY Task Group 3a.

http://www.ieee802.org/15/pub/TG3a.html.

[2] DS-UWB Physical Layer Submission to 802.15 Task Group 3a.

http://www.ieee802.org/15/pub/04/15-04-0137-01-003a-merger2-proposal-ds-uw b-update.doc

[3] Multi-band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a.

http://www.ieee802.org/15/pub/2003/Jul03/03268r2P802-15_TG3a-Multi-ban d-CFP-Document.pdf

[4] J. Crols and M. S. J. Steyaert, "A single-chip 900 MHz CMOS receiver front-end wuth a high performance low-IF topology," IEEE Journal of Solid-State Circuit, vol. 30, no. 12, pp. 1483-1492, Dec. 1995.

[5] V. Kakani, F. F. Dai, and R. C. Jaeger, "A 5 GHz low-power series-coupled BiCMOS quadrature VCO with wide tuning range," IEEE Microw. Wireless Compon. Lett., vol.

17, no. 6, pp. 457-459, Jun. 2007.

[6] H. -R. Kim, C. -Y. Cha, S. -M. Oh, M. -S, Yang, and S. -G. Lee, ”A very low power quadrature VCO with back-gate coupling,” IEEE Journal of Solid-State Circuits, vol.39 no.6, pp. 952-955, June 2004.

[7] Y. -J. Moon, Y. -S. Roh, C. -Y. Jeong, and C. Yoo, "A 4.39-5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation," IEEE Microw. Wireless Compon. Lett., vol. 19, no. 8, pp. 524-526, Aug. 2009.

[8] J. -H. Chang and C. -K, Kim, “ A symmetrical 6-GHz fully integrated cascade coupling CMOS LC quadrature VCO,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 10, pp.

670-672, Oct. 2005.

[9] J. -P. Hong, S. -J. Yun, N. -J. Oh, and S. -G. Lee, “ A 2.2-mW backgate coupled LC quadrature VCO with current reused structure,” IEEE Microw. Wireless Compon. Lett., vol. 17, no.4, pp. 298-300, Apr. 2007.

[10] N. -J. Oh, and S. Lee, “Current Reuse LC VCOs,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 11, pp.736-738, Nov. 2005.

[11] S. Yun, S. Shin, H. Choi, and S. Lee, “A 1 mW current-reuse CMOS differential LC-VCO with low phase noise,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech.

Papers, Feb. 2005, pp. 540–541.

[12] H. -R. Kim, C. -Y. Cha, S. -M. Oh, M. -S. Yang and S. -G. Lee, "A very low-power quadrature VCO with back-gate coupling," IEEE Journal of Solid-State Circuits, vol. 39, pp. 952-955, June 2004.

[13] F. Dulger and E. Sanchez-Sinencio, "Design trade-offs of a symmetric linearized CMOS LC VCO," in Proc. IEEE Int. Symp. Circuits Syst., pp. 397-400, 2005.

[14] C. -Y. Cha, H. -C. Choi, H. -T. Kim, and S. -G. Lee, "RF CMOS differential oscillation with source damping resistors," in Proc. IEEE RFIC Symp., pp. 399-402, 2005.

[15] J. J. Rael and A. A. Abidi, "Physical Processes of Phase Noise in Differential LC Oscillator," CICC, pp. 569-572, 2000.

[16] C. Hung, K. K. O, "Fully integrated 5.35-GHz CMOS VCOs and Prescalers," Trans.

MTT, vol. 49, no. 1, Jan, 2001.

[17] M. -D. Wei, S. -F. Chang and C. -S, Chen, “ A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique,” IEEE Microw.

Wireless Compon. Lett., vol. 19, no. 6, pp.398-400, June 2009.

[18] M. -D. Wei, S. -F. Chang and S. -W, Huang, “ An Amplitude-Balanced Current-Reused CMOS VCO Using Spontaneous Transconductance Match Technique,” IEEE Microw.

Wireless Compon. Lett., vol. 19, no. 6, pp.395-397, June 2009.

LC-VCO with Phase-to-Amplitude Noise Conversion, ” IEEE ISSCC 2006, Feb. 2006.

[20] H. Takauchi et al., “A CMOS multichannel 10-Gbs transceiver,” IEEE Journal of Solid-State Circuits, vol.38, No. 12, pp. 2094-2100, 2003.

[21] D. Zheng, X. Jin et al., “A quad 3.125 Gb/s/channel transceiver with analog phase rotators,”

ISSCC Dig. Tech. Papers, vol. 1, 3-7, pp. 70–446, Feb. 2002.

[22] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8 GHz CMOS LC quadrature VCO”, IEEE J. Solid-State Circuits, vol. 37, pp. 1737-1747, Dec. 2002.

[23] P. Andreani, “A low-phase-noise, low-phase-error 1.8 GHz quadrature CMOS VCO,”

IEEE ISSCC Dig. Tech. Papers, pp. 290-291, Feb. 2002.

[24] O. Casha, I. Grech, and J. Micallef, "Comparative Study of Gigahertz CMOS LC Quadrature Voltage controlled Oscillators with relevance to phase noise," Analog Integrated Circuits and Signal Processing, 2007, vol. 52, pp. 1–14.

[25] P. Andreani, “A 2 GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6 phase error,” in Proc. ESSCIRC, Sept. 2002, pp. 815–818.

[26] S. Ye and I. Galton, “Techniques for Phase Noise Suppression in Recirculating DLLs,”

IEEE J. Solid-State Circuits, vol. 39, no. 8, Aug. 2004.

[27] E. -A. -M. Klumperink, S. -L. -J. Gierkink, A. -P. van der Wel, and B. Nauta, “Reducing MOSFET 1/f Noise and Power Comsumption by Switching Biasing,” IEEE J.

Solid-State Circuits, vol. 35, no. 7, July 2000.

[28] G. Huang and B. -S. Kim, “Low Phase Noise Self-Switched Biasing CMOS LC Quadrature VCO,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 2,. Feb. 2009.

[29] D. Siprak, M. Tiebout, N. Zanolla, P. Baumgartner, and C. Fiegna., “Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias,” IEEE J.

Solid-State Circuits, vol. 44, no. 7, July 2009.

[30] B. Soltanian and P. R. Kinget, “Tail Current-Shaping to Improve Phase Noise in LC

Voltage-Controlled Oscillators” IEEE J. of Solid-State Circuits, vol. 41, no. 8, Aug. 2006.

[31] A. Hajimiri and T. H. Lee, "A General Theory of Phase Noise in Electrical Oscillators," IEEE Journal of Solid-State Circuits, vol. 33, pp. 179-194, Feb 1998.

[32] A. Hajimiri and T. H. Lee, "Phase Noise in CMOS Differential LC Oscillators," IEEE Journal of Solid-State Circuits, vol. 34, pp. 717-724, Feb 1998.

[33] A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators. Norwell, MA: Kluwer, 1999.

[34] A. Arnaud and C. Galup-Montoro, "Consistent noise models for analysis and design of CMOS circuits," IEEE Trans. Circuit Syst. I, vol. 51, no. 10, pp. 1909-1915, Oct. 2004.

[35] H. Ma, S. J. Fang, F. Lin, K. S. Tan, "A high performance GaAs MMIC upconverter with an automatic gain control amplifier," 19th Annual Gallium Arsenide Integrated Circuit Symposium, pp. 232-235, Oct. 1997.

[36] R. H. Lee, et. al., "Circuit techniques to improve the linearity of an up-conversion double balanced mixer with an active balun," 2005 Asia Pacific Microwave Conference (APMC), vol. 2, pp. 4-7, Dec. 2005.

[40] A. M. Niknejad and H. Hashemi, Mm-wave silicon technology 60GHz and beyond, New York, NY: Springer Science+Business Media, 2008.

[41] John Rogers, Calvin Plett, Foster Dai, Integrated Circuit Design for High-Speed

MA, 2006

[42] D. Park and S. Cho, "A 1.8V 900μW 4.5GHz VCO and Prescaler in 0.18μm CMOS Using Charge-Recycling Technique," IEEE Microw. Wireless Compon. Lett., vol. 19, no.

2, pp. 104-106, Feb. 2009.

[43] S. -L Jang, T. -S. Lee, C. -W. Hsue, and C. -W. Chang, "A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO," IEEE Microw. Wireless Compon. Lett., vol.

19, no. 11, pp. 722-724, Nov. 2009.