Measurement Results and Discussion

2.4.1 Measurement Consideration

The proposed QVCO are designed for on-wafer testing, and the DC voltage are supplied by two sets of six-pin probe, so that the distance between each DC pad must more than 50μm to satisfy the probe testing rules. The output buffer of each quadrature output is designed using common-source amplifier, and the drain end of each buffer is connected to the RF pad.

For measurement, we connect four bias-tee terminals to the corresponding RF pads as shown in Fig. 2 - 20.

Fig. 2 - 20 Bias-Tee Model

The phase noise, tuning range, output spectrum and output waveform are measured using signal source analyzer (Agilent E5052B) and digital signal analyzer (Agilent DSA91204A) shown in Fig. 2 - 21and Fig. 2 - 22, respectively.

Fig. 2 - 21 Signal Source Analyzer (Agilent E5052B)

Fig. 2 - 22 Digital Signal Analyzer (Agilent DSA91204A)

Fig. 2 - 23 Chip photo of the proposed modified STM-QVCO

The Chip photo of the proposed modified STM-QVCO is shown in Fig. 2 - 23. Fig. 2 - 24 and Fig. 2 - 25 shows the arrangement of DC and RF probes. The measured phase noise at 4.84GHz, output spectrum, tuning range, output waveform, and amplitude imbalance ratio was shown in Fig. 2 - 26 to Fig. 2 - 30, respectively. Table 2 - 2 summarizes the measured performance of the proposed modified STM-QVCO.

Fig. 2 - 24 Arrangement of DC and RF probes

Fig. 2 - 25 Photograph of the probe station

Fig. 2 - 26 Measured phase noise of the proposed modified STM-QVCO

Fig. 2 - 27 Measured output spectrum of the proposed modified STM-QVCO

Fig. 2 - 28 Measured tuning range of the proposed modified STM-QVCO

Fig. 2 - 30 Measured output amplitude imbalance ratio of the proposed modified STM-QVCO

Table 2 - 2 Comparison of QVCO Performance

Chapter 3

Current-Reused Low Phase Noise Quadrature VCO with Self-Switching Bias

3.1 Introduction

Quadrature signals finds application in many communication systems. For high speed clock and data recovery systems, quadrature signals are required for frequency detection, half-rate phase noise detection, and phase interpolation [19] - [21]. For RF front-ends, quadrature signals are necessary in the implementation of image rejection and direct conversion transceivers, where they are used for modulation or demodulation requirements.

As we mentioned in chapter 2, there are several methods to generate quadrature signal.

In fact, a widely-used approach for generation the quadrature signals at high operation frequencies is to cross couple two identical LC oscillator so as to take advantage of the superior performance achievable with LC resonators. In this case two oscillators can be connected in such a way that a signal from one oscillator is injected into the second oscillator and a signal from the second oscillator is injected into the first. The result is that the two oscillators become locked in frequency with quadrature outputs. LC-VCOs have good phase noise performance due to their inherent frequency selectivity that can suppress side-band noise.

Fig. 3 - 1 shows the well-known implementation of Quadrature negative G_m Oscillator with parallel cross connections, in which two LC-VCOs are cross-coupled using addition

coupling transistor (M5-M8) in parallel with the core negative-resistance transistor (M1-M4).

This technique, however, suffers from the trade-off between phase noise and accuracy. The coupling transistors connected in parallel further degrades the phase noise and the power consumption significantly. To improve the performance, the coupling transistor (M₅-M₈) can be connected in series with the negative-resistance transistors (M1-M4), such that the phase noise contribution from the coupling device can be reduced as a result of degeneration in cascode configuration. The trade-off between phase noise and phase accuracy can be relaxed.

Fig. 3 - 1 Schematic of the conventional parallel-coupled QVCO (P-QVCO)

As shown in Fig. 3 - 2, one of the methods of series coupling is referred as the Top-Series (TS) QVCO [22], [23]. Since the coupling transistor does not require an additional biasing current, power consumption is reduced in this topology. The phase error is almost independent of coupling strength αB . In fact, phase error of the TS-QVCO acts like a design constant dependent on the actual amount of mismatch between ideally identical components. When both TS-QVCO and P-QVCO are designed to have the same coupling strength, center frequency, and power consumption, it follows that the former has lower phase noise response.

Fig. 3 - 2 Schematic of the conventional top series-coupled QVCO (TS-QVCO)

Fig. 3 - 3 Schematic of the conventional bottom series-coupled QVCO (BS-QVCO)

The major problem with this architecture is that the coupling transistors have to be about five times larger than the negative resistance transistors [24], thus loading the oscillator with large parasitic capacitances that reduce the tuning range, making this solution unsuitable for high frequency and wideband application.

There is an alternative way to achieve series coupling, as shown in Fig. 3 - 3, known as the Bottom Series (BS) QVCO [25]. In this configuration the coupling transistor is placed at the bottom of the switching transistor. As for the TS-QVCO, the phase error is almost independent of coupling strength α_B. When both BS-QVCO and P-QVCO display the same phase-error and have the same center frequency and power consumption, BS-QVCO has a higher figure of merit (FOM). However, to compare with TS-QVCO, BS-QVCO has a higher FOM but also a higher phase error than TS-QVCO.

Fig. 3 - 4 Schematic of the conventional middle series-coupled QVCO (MS-QVCO)

Another alternative topology of series connection is the Middle Series (MS) QVCO [25], which is basically an improved TS-QVCO, as shown in Fig. 3 - 4. This topology has a higher Figure of Merit (FOM) than the other three topologies, but a phase error which is between that of the TS-QVCO and the BS-QVCO. It features very low phase noise especially at a low frequency offset [24].

In modern submicron CMOS processes, the flicker noise (1/f noise) is a significant noise source and is a critical issue in VCO design. As reported in [26]-[30], shown in Fig. 3 - 5, that periodically switching a MOS transistor between "on" and "off" states results in a significant reduction of the flicker noise. It was also revealed that the switching of the tail current source by applying a sine or square wave can reduce 1/f noise itself. Oscillator circuits are suitable for applying a switched biasing technique in that they can use an oscillation waveform by oscillator with switching bias has been reported to be reduced by 8 dB compared with a fixed bias. Furthermore, using switching bias can also reduce the power consumption.

Fig. 3 - 5 Varying VGS cycles a MOS transistor between "on" and "off"

Fig. 3 - 6 Schematic of the conventional self-switching biased QVCO

The circuit we proposed in this chapter using a novel low noise capacitor-coupling method to perform injection locking, and therefore quadrature signals at the output can be obtained. Moreover, this novel low noise capacitor-coupling CR-QVCO topology adopts a self-switching bias and a tail current-shaping technique to suppress the 1/f noise from a tail current source. By using these large signal sine-wave outputs to make the tail-current transistors self-switching, the advantage of lower phase noise and lower power consumption can be simultaneously achieved. The proposed QVCO has four states of oscillating behavior, and it is a novel QVCO topology in comparison with the above-mentioned QVCOs. The circuit design consideration will be discussed in next section.

3.2 Circuit Design Consideration

The schematic of the proposed self-switching biased current reused quadrature VCO (CR-QVCO) is shown in Fig. 3 - 7. In this novel CR-QVCO topology, three mechanisms are incorporated to improve the phase noise :

I. A novel low noise capacitor-coupling technique was adopted to generate quadrature signals. As highlighted in Fig. 3 - 8, the outputs are injected to the source node of the cross coupled transistors through four noiseless components, capacitors. Consequently, there were no extra noise source incorporated in order to generate quadrature signals.

Fig. 3 - 7 Schematic of the proposed self-switching biased QVCO

Fig. 3 - 8 Novel injection method of the proposed self-switching biased QVCO

II. By using the self-switching bias and tail current shaping technique, we can decrease the active time of the noise source, i.e., the tail current source, to reduce the oscillator phase noise. In addition, it also has benefit of saving power since each of the tail current transistors, which has about 50% on-off operation of duty cycle, needs only half of the dc power consumption as compare to the constant dc bias counterpart. Note that in the proposed self-switching biased CR-QVCO, only one switching transistor were used in each tail current source, rather than the dual-switching-transistor topology shown in Fig.

3 - 6. Consequently, the proposed self-switching biased current reused QVCO can further reduce the power consumption by combining the single switching-tail-current topology and the current-reused topology. Moreover, switching a MOS transistor will force the release of captured electrons or holes from a trap, and hence the tail current transistors

III. Using a novel CR-QVCO topology with the alternatively turn-on mechanism between tail current transistors and cross-coupled switching transistors. As shown from Fig. 3 - 9 to Fig. 3 - 12, the proposed CR-QVCO has four states during an oscillation period. In each state, the cross coupled transistor and tail current transistor, for example, M1 and M3, would never turn on simultaneously. There is no dc conducting path from VDD to ground and only the ac conducting path exists. Note that the conventional complementary CR-QVCO as we proposed in Chapter 2, shown in Fig. 2 - 9, has two half-period (In which, the first half-period is that all the transistors turn on ,and a dc conducting path from VDD to ground was established. The second half-period then becomes that all the transistors turn off) . Thanks to this alternatively turn-on mechanism, the noise current generated by the tail current transistors would be blocked, and high spectral-purity output can be obtained.

Fig. 3 - 13 and Fig. 3 - 14, in which the definitions of current-flow were marked in Fig. 3 - 15, shows the simulated currents in the current-limited regime and voltage-limited regime, respectively. Fig. 3 - 13 and Fig. 3 - 14 also give a clear illustration about the behavior of alternatively turn-on mechanism.

Fig. 3 - 9 State-1 of the proposed self-switching biased QVCO

Fig. 3 - 10 State-2 of the proposed self-switching biased QVCO

Fig. 3 - 11 State-3 of the proposed self-switching biased QVCO

Fig. 3 - 12 State-4 of the proposed self-switching biased QVCO

Fig. 3 - 13 Simulated currents in the current-limited regime

Fig. 3 - 14 Simulated currents in the voltage-limited regime

Fig. 3 - 15 The definitions of current-flow used in Fig. 3 - 13 and Fig. 3 - 14

3.3 Chip Layout and Simulation Results

The circuit was simulated and optimized using Agilent ADS. The design procedure can be divided in two steps. First, a small signal analysis was used to optimize the feedback and the resonator elements to find the oscillation condition at the target frequency. This condition was simulated breaking the feedback path. In the second step, a large signal analysis was performed with the harmonic balance simulator to predict the exact oscillation frequency and output power of the fundamental signal as well as the harmonic signals.

Fig. 3 - 16 shows the chip layout photograph of the proposed modified STM current reused QVCO, which is designed and implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. The chip size is 1.100 × 0.841 mm² including all pads and bypass capacitances. Each buffer of the QVCO outputs were designed as a common-source amplifier.

Fig. 3 - 16 Chip layout of the proposed self-switching biased QVCO

Fig. 3 - 17 Simulated phase noise of the proposed self-switching biased QVCO

Fig. 3 - 18 Simulated tuning range of the proposed self-switching biased QVCO

The simulated phase noise and tuning range of the proposed modified STM QVCO are shown in Fig. 3 - 17and Fig. 3 - 18,respectively. Table 3 - 1 summarizes the simulated results of the proposed modified STM QVCO in each corner. The figure of merits (FOM) for oscillators summarizes the important performance parameters, i.e., phase noise and power consumption P, to make a fair comparison is defined in [40] as

 

where the second term is to neutralize the effect of offset in L(Δω) while taking the center frequency into account. The power consumption is calculated as dBm such that the unit of FOM remains the same as that of L(Δω).

Table 3 - 1 Simulated results of the proposed modified STM-QVCO

Corner SS TT FF SF FS

Tuning Range

4.64-5.11 4.84-5.32 5.07-5.58 4.84-5.33 4.85-5.33 Phase

Noise

-126.295 -125.750 -124.371 -125.841 -125.442 Supply

3.4 Measurement Results and Discussion

3.4.1 Measurement Consideration

The proposed QVCO are designed for on-wafer testing, and the DC voltage are supplied by two sets of six-pin probe, so that the distance between each DC pad must more than 50μm to satisfy the probe testing rules. The output buffer of each quadrature output is designed using common-source amplifier, and the drain end of each buffer is connected to the RF pad.

For measurement, we connect four bias-tee terminals to the corresponding RF pads as shown in Fig. 3 - 19.

Fig. 3 - 19 Bias-Tee Model

The phase noise, tuning range, output spectrum and output waveform are measured using signal source analyzer (Agilent E5052B) and digital signal analyzer (Agilent DSA91204A) shown in Fig. 3 - 20 and Fig. 3 - 21, respectively.

Fig. 3 - 20 Signal Source Analyzer (Agilent E5052B)

Fig. 3 - 21 Digital Signal Analyzer (Agilent DSA91204A)

Fig. 3 - 22 Chip photo of the proposed self-switching biased CR-QVCO

The Chip photo of the proposed self-switching biased CR-QVCO is shown in Fig. 3 - 22.

Fig. 3 - 23 and Fig. 3 - 24 shows the arrangement of DC and RF probes. The measured phase noise at 4.83GHz, measured phase noise at 5.3GHz, output spectrum, tuning range, and output waveform was shown in Fig. 3 - 25 to Fig. 3 - 29, respectively. Table 3 - 2 summarizes the measured performance of the proposed self-switching biased CR-QVCO.

Fig. 3 - 23 Arrangement of DC and RF probes

Fig. 3 - 24 Photograph of the probe station

Fig. 3 - 25 Measured phase noise of the proposed self-switching biased QVCO at f^ｏ= 4.83GHz

Fig. 3 - 26 Measured phase noise of the proposed self-switching biased QVCO at f^ｏ= 5.29GHz

Fig. 3 - 27 Measured output spectrum of the proposed self-switching biased QVCO

Fig. 3 - 28 Measured tuning range of the proposed self-switching biased QVCO

Fig. 3 - 29 Measured output waveform of the proposed self-switching biased QVCO

Table 3 - 2 Comparison of QVCO Performance

Chapter 4

Conclusion and Future Work

4.1 Conclusion

In chapter 2, we proposed a new architectures for low phase noise current-reused QVCO : current-reused quadrature VCO with modified spontaneous transconductance match (M-STM). Adopting the M-STM technique reduce the amplitude imbalanced ratio. The measured results reveal that the tuning range is between 4.84 - 5.17 GHz, the phase noise is -117.4 dBc/Hz at 1MHz offset, and the power consumption is 5.04mW under 1.3V supply voltage.

In Chapter 3, we proposed another new architecture for low phase noise current-reused QVCO : current-reused low phase noise quadrature VCO with self-switching bias. Three mechanisms are incorporated to improve the phase noise :

1. A novel low noise capacitor-coupling technique

2. By using the self-switching bias and tail current shaping technique

3. Using a novel CR-QVCO topology with the alternatively turn-on mechanism between tail current transistors and cross-coupled switching transistors.

The measured results reveal that the tuning range is between 4.83-5.30 GHz, the phase noise is -125.8 dBc/Hz at 1MHz offset, and the power consumption is 3.64 mW under 1.3V supply voltage.

Finally, we introduce a wideband CMOS down-converting mixer for W-band receiver

application in the appendix. This mixer has the RF frequency chosen to be 8.7 - 17.4GHz, LO frequency fix at 17.5GHz, and IF frequency close to 0.1 - 8.8GHz. In order to reduce the difficulty in designing the corresponding LO module, another mixer with the integrated LO frequency doubler has also been proposed in the appendix.

4.2 Future Work

Although The main purpose of this thesis focus on the study of the low phase noise current reused quadrature VCOs, I also started the study of the PLLs, frequency synthesizers, and switching power supply. All of these analog and mixed signal circuit will be my future research topics.

Appendix A

Wideband CMOS Down-Converting Mixer for W-Band Receiver

A.1 Introduction

Mixers are key components of an RF front-end, translating the IF signal to a carrier frequency for transmission and from RF carrier back down to IF for detection. Mixer essentially modulations either the transconductance of an amplifier or the resistance of a switch to produce the mixing action through time-varying mechanism. Although there are many topologies of mixers (single-balanced、double-balanced...etc.), the double-balanced

Fig. A - 1 Conventional double balanced mixer

circuit configuration have been readily appearing in microwave and millimeter wave applications for its good isolations.

For example, as indicated in Fig. A - 1, the schematic is a typical double balanced mixer.

In order to enhance the conversion gain, it is perhaps to use large R_L. However, as R_L increasing, the voltage drop between RL will also increasing, therefore minimizing the output swing. Increasing the power supply V_DD is a solution but it will consume more power. An alternative solution is externally injecting current by using the two current sources as indicated in Fig. A - 2, However, this solution can't be applied at tens of GHz, since the current source are usually made of p-type transistor, the output impedance of the current source tend to decrease at high frequency and thus deteriorated the mixer's performance at the high frequency.

Fig. A - 2 Conventional double balanced mixer with gain-enhancement

So far, most of the mixers with normal-biased transistors, as contrast to resistors with no drain to source bias, have their wideband proclamation illustrated by shifting the LO across the intended RF bandwidth, while keeping the IF wideband comparatively small, i.e.,

wideband RF-bandwidth but narrow IF-bandwidth. With an IF bandwidth of hundreds of MHz, a large output signal voltage can be easily achieved by replacing each R_L in Fig. A - 2 with an appropriate p-type transistor as a active load, for which is capable of providing a large impedance at low frequency. However, when the IF bandwidth is extended to several GHz,

Fig. A - 3 Schematic of the wideband receiver

the rapidly decreasing impedance of this active p-type load become a liability, as it leads to a large variation of the conversion gain over the intended bandwidth: extremely high impedance at the low-end of the IF frequency range while at high-end it is mediocre or no better than that of mixers using R_L.

Fig. A - 3 is the schematic of a millimeter-wave receiver which will be used in the form of array for determination of the anisotropy of the cosmic microwave background radiation, and it demands the employment of several wide IF bandwidth mixers. The incoming signal is first fed into two cascade cryogenic amplifier modules with each has 70.90 Kelvin noise temperature and 20dB gain at 20Kelvin ambience. To ensure stability, cryogenic isolators have been incorporated into these amplifiers. The cryogenic WiseWave-FDB1001 mixer made by WiseWave Technologies (now Ducomun Technologies) is then used to down-convert, with 5.7dB conversion loss, the signal to DC - 4f_LO GHz. Of course, it is possible using a room-temperature mixer instead, but that will require the precision insertion of a hermetically-sealed millimeter-wave waveguide between the front-end cryogenic amplifier and this room-temperature mixer, and the attenuation along this long waveguide will also pronounced. Four separate bands can now be extracted by the use of amplifiers, filters, and another three mixers, each with 8.7GHz IF bandwidth and the LO frequency is fixed at 17.4GHz, 17.4GHz and 26.1GHz,respectively. The reason for not using an 8.7GHz LO for down-converting in the second band is because this LO is bordering the IF band, thus any residual LO at IF output is hard to remove; by contrast, a 17.4GHz will not have this problem.