Introduction

Modern RF receivers and transmitters require oscillators with accurate quadrature and low phase noise. Since most of the current wireless communication systems are employing quadrature modulation, there have been various research results to obtain accurate quadrature local oscillator (LO) signals with low phase noise. For quadrature signals, in-phase and quadrature-phase (I/Q) match is an important requirement while meeting the requirements of low-phase noise and low power for integrated VCOs. The quadrature characteristics can be evaluated in terms of phase error and amplitude imbalance. Quadrature LO signals can be obtained in various ways:

I. A poly-phase filter (PFF) following a VCO running at the required LO frequency [4].

Usually, the PFF for quadrature phase shift is implemented with a passive RC network, which introduces power loss and additional phase noise. If a wide frequency range is required, high order PFF has to be used and the power loss and phase noise become much large. Additional power might have to be dissipated in the LO buffer compensating the power loss in the passive PFF[5].

II. A divide-by-two frequency divider following a VCO running at double the required LO

frequency, as shown in Fig. 2 - 1 (a). This method has the drawback of very large power consumption due to the high operating frequency of VCO and frequency divider.

III. By means of Quadrature coupling the differential VCOs[6]-[9], as shown in Fig. 2 - 1 (b). The quadrature coupling method is widely used because of its better phase noise performance. Therefore, in this chapter we use the quadrature coupling method to generate the quadrature LO signals.

In order to achieve low power consumption, current-reused VCO (CR-VCO) configuration is one of the most widely used solutions. Fig. 2 - 2 shows the schematic of the conventional NMOS-based current-reused VCO (CR-VCO) by stacking switching transistors in series like a cascode [10].

Fig. 2 - 1 Examples of quadrature signal generation methods (a)frequency division (b)quadrature coupling

Fig. 2 - 2 Schematic of the conventional current-reused topology

Unfortunately, There are three drawbacks of this type CR-VCO. First, As compared to the generic VCO, the frequency tuning range of this type CR-VCO is narrower. Because the DC levels at the two sides of the varactors are different, the capacitors C_blk must be added for dc block and ac short to have the identical voltage drop across the varactors. Besides, the capacitors C_cpl and resistors R_bias should be added to biasing the transistors properly.

Therefore, the capacitance tuning range Cmax / Cmin will be smaller due to the addition of extra capacitors. Involving too large number of capacitors and hence higher capacitive load at the output node also restrict the oscillation frequency. Second, A large capacitor Cgnd, even an external one, should be added at the node X. Since the node X is pulled up when each one of the differential NMOS turns on, the frequency at the node X is twice as the frequency at the VCO output. A large capacitor C_gnd should be used to have a tight ground effect, symmetric differential output swing and suppress the high frequency noise at node X. Third, the amplitude

imbalance of the output signals is relatively larger than the conventional cross-coupled VCO due to the unsymmetric circuit structure.

Fig. 2 - 3 Schematic of another conventional current-reused topology

Another type of CR-QVCO has been reported in [11], as shown in Fig. 2 - 3. It replaces one of the NMOS transistors of a conventional differential LC-VCO with a PMOS transistor.

The biasing of this complementary current-reused VCO (CR-VCO) topology is much easier than the NMOS-based cascode current-reused VCO (CR-VCO) topology. That is, the DC levels at the two sides of the varactors are the same and no extra capacitors are needed.

Therefore, the problem of involving too large number of capacitors and hence higher capacitive load at the output node can be solved.

Although the CR-QVCO using the configuration shown in Fig. 2 - 3 has excellent low power consumption, there is an drawback that the amplitude imbalance of the output signals

is relatively larger than the conventional cross-coupled VCO due to the asymmetric circuit structure. To solve this problem, a passive degenerative resistor is added at the source node of the NMOS transistor to balance the transconductance difference between PMOS and NMOS transistors. Unfortunately, this method requires an accurate resistance value to have good imbalance suppression and the inserted resistor dissipated an extra amount of power. The VCO reported in [18] used MOS transistors biased in the triode region as a variable resistor to replace the degenerative resistor. By connecting the gate terminals to the center-tapped inductor, which was called spontaneous transconductance match (STM) technique, the VCO is able to automatically eliminate the signal imbalance such that high amplitude balance and low power consumption can be simultaneously achieved without using any accurate resistors.

The circuit we proposed in this chapter has slightly modified the so-called STM- technique by connecting the gate terminals to the another side of the output. Because of feedback mechanism, much better performance of transconductance matching than original one can be achieved. We give it a name modified spontaneous transconductance match (M-STM) technique. The circuit design consideration will be discussed in next section.

Fig. 2 - 4 Schematic of the conventional parallel-coupled QVCO (P-QVCO) topology

Fig. 2 - 5 Small signal equivalent circuit of the switching- and parallel-coupling transistor

Fig. 2 - 4 shows the conventional parallel QVCO (P-QVCO) where I and Q signals are generated by coupling two differential VCOs through coupling transistors M₅ - M₈ in parallel with switching transistors M1 - M4. Fig. 2 - 5 shows the small signal equivalent circuit of the switching and corresponding coupling transistors [6]. From Fig. 2 - 5, the coupling strength α between the two VCOs of the P-QVCO can be defined as

m,couple m5 5

m,switching m1 1

g g W

α= = =

g g W

where g_m,couple and gm,switching are the transconductance of coupling transistor and switching transistor, respectively. In P-QVCO, the coupling strength α has a strong effect on phase noise and phase error which defines the phase difference from 90^。between I and Q signals. For the VCO is used as the quadrature phase coupling element to the other pair. Consequently the four quadrature-coupling transistors in the conventional P-QVCO are not needed and their noise contribution to the oscillator vanishes. As mention above, the P-QVCO has trade-off between phase noise and phase error. However, in the back-gate-coupling QVCO, phase error can be reduced without sacrificing phase noise as the coupling involves no additional transistors. From Fig. 2 - 7, the coupling strength αB through the back-gate can given by

mb

where γ, ΦF, and VBS are the body-effect coefficient, work function, and back-gate (body) to source bias voltage, respectively. It can be seen that the coupling strength α_B is a function of VBS. Therefore, in order to increase αB, which leads to phase error reduction, the body-to-source reverse bias should be minimized. The usage of back-gates removes the

coupling transistors and therefore additional noise contributions compared to the conventional coupling transistor based topology.

Fig. 2 - 6 Schematic of the conventional back-gate coupling QVCO

Fig. 2 - 7 Small signal equivalent circuit of the back-gate-coupling transistor

The close-in phase noise spectrum of the circuit shown in Fig. 2 - 6 results from the flicker noise up-conversion of the NMOS and back-gate modulation PMOS transistor, which is expressed as [33]

where c₀ is the first Fourier coefficient of the impulse sensitivity function, representation the

wave form symmetry of oscillating signal. The term

2 corner frequency _{1/f Pb,} . The insertion of the resistor R_S at the NMOS source node reduces the transconductance by a factor of 1/(1+g_m,NR_s), which in turn reduces _{1/f N,} by the same factor due to the proportionality of _{1/f N,} to g_m,N for a short-channel MOS transistor [34].

The resistor RS also linearizes the degenerated transconductance variation over an oscillating swing period. Nevertheless, this method requires an accurate resistor R_S which must be properly designed because large RS may cease the oscillation start-up, introduce extra thermal noise and introduce an extra amount of power. As mention above, we propose the modified spontaneous transconductance match (M-STM) technique to conquer this problem.

The circuit we proposed in this chapter can achieve lower phase noise, lower amplitude imbalance ratio and lower power dissipation by combining the back-gate coupling principle, current-reused QVCO structure and modified spontaneous transconductance match (M-STM) technique. The circuit design consideration will be discussed in next section.