Thesis Organization

In this thesis, two current-reused quadrature VCO (CR-QVCO) and a wideband CMOS down-converting mixer for W-band receiver are realized in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology, another mixer with the integrated LO frequency doubler has also been proposed.

Chapter 1 discusses the motivation and challenges in low-phase-noise CMOS QVCO design, and gives a brief introduction to the oscillator and phase noise.

Chapter 2 presents a back-gate coupled current-reused quadrature VCO (CR-QVCO) which use feedback mechanism to accomplish modified spontaneous transconductance match (M-STM) technique. This method is able to eliminate the transconductance difference between NMOS and PMOS transistors so that high output amplitude balance can be achieved.

Chapter 3 will propose a novel low noise capacitor-coupling method to perform injection locking, and therefore quadrature signals at the output can be obtained. Moreover, by using these large signal sine-wave outputs to make the tail-current transistors self-switching, the advantage of lower phase noise and lower power consumption can be simultaneously achieved.

Chapter 4 gives the conclusions, summary of contributions, and future work plan.

Finally, Appendix focuses on a wideband CMOS down-converting mixer for W-band receiver application. This mixer has the RF frequency chosen to be 8.7-17.4GHz, LO frequency fix at 17.5GHz, and IF frequency close to DC~8.8GHz. In order to reduce the difficulty in designing the corresponding LO module, another mixer with the integrated LO frequency doubler has also been proposed.

Chapter 2

Current-Reused Quadrature VCO with Modified Spontaneous Transconductance Match

2.1 Introduction

Modern RF receivers and transmitters require oscillators with accurate quadrature and low phase noise. Since most of the current wireless communication systems are employing quadrature modulation, there have been various research results to obtain accurate quadrature local oscillator (LO) signals with low phase noise. For quadrature signals, in-phase and quadrature-phase (I/Q) match is an important requirement while meeting the requirements of low-phase noise and low power for integrated VCOs. The quadrature characteristics can be evaluated in terms of phase error and amplitude imbalance. Quadrature LO signals can be obtained in various ways:

I. A poly-phase filter (PFF) following a VCO running at the required LO frequency [4].

Usually, the PFF for quadrature phase shift is implemented with a passive RC network, which introduces power loss and additional phase noise. If a wide frequency range is required, high order PFF has to be used and the power loss and phase noise become much large. Additional power might have to be dissipated in the LO buffer compensating the power loss in the passive PFF[5].

II. A divide-by-two frequency divider following a VCO running at double the required LO

frequency, as shown in Fig. 2 - 1 (a). This method has the drawback of very large power consumption due to the high operating frequency of VCO and frequency divider.

III. By means of Quadrature coupling the differential VCOs[6]-[9], as shown in Fig. 2 - 1 (b). The quadrature coupling method is widely used because of its better phase noise performance. Therefore, in this chapter we use the quadrature coupling method to generate the quadrature LO signals.

In order to achieve low power consumption, current-reused VCO (CR-VCO) configuration is one of the most widely used solutions. Fig. 2 - 2 shows the schematic of the conventional NMOS-based current-reused VCO (CR-VCO) by stacking switching transistors in series like a cascode [10].

Fig. 2 - 1 Examples of quadrature signal generation methods (a)frequency division (b)quadrature coupling

Fig. 2 - 2 Schematic of the conventional current-reused topology

Unfortunately, There are three drawbacks of this type CR-VCO. First, As compared to the generic VCO, the frequency tuning range of this type CR-VCO is narrower. Because the DC levels at the two sides of the varactors are different, the capacitors C_blk must be added for dc block and ac short to have the identical voltage drop across the varactors. Besides, the capacitors C_cpl and resistors R_bias should be added to biasing the transistors properly.

Therefore, the capacitance tuning range Cmax / Cmin will be smaller due to the addition of extra capacitors. Involving too large number of capacitors and hence higher capacitive load at the output node also restrict the oscillation frequency. Second, A large capacitor Cgnd, even an external one, should be added at the node X. Since the node X is pulled up when each one of the differential NMOS turns on, the frequency at the node X is twice as the frequency at the VCO output. A large capacitor C_gnd should be used to have a tight ground effect, symmetric differential output swing and suppress the high frequency noise at node X. Third, the amplitude

imbalance of the output signals is relatively larger than the conventional cross-coupled VCO due to the unsymmetric circuit structure.

Fig. 2 - 3 Schematic of another conventional current-reused topology

Another type of CR-QVCO has been reported in [11], as shown in Fig. 2 - 3. It replaces one of the NMOS transistors of a conventional differential LC-VCO with a PMOS transistor.

The biasing of this complementary current-reused VCO (CR-VCO) topology is much easier than the NMOS-based cascode current-reused VCO (CR-VCO) topology. That is, the DC levels at the two sides of the varactors are the same and no extra capacitors are needed.

Therefore, the problem of involving too large number of capacitors and hence higher capacitive load at the output node can be solved.

Although the CR-QVCO using the configuration shown in Fig. 2 - 3 has excellent low power consumption, there is an drawback that the amplitude imbalance of the output signals

is relatively larger than the conventional cross-coupled VCO due to the asymmetric circuit structure. To solve this problem, a passive degenerative resistor is added at the source node of the NMOS transistor to balance the transconductance difference between PMOS and NMOS transistors. Unfortunately, this method requires an accurate resistance value to have good imbalance suppression and the inserted resistor dissipated an extra amount of power. The VCO reported in [18] used MOS transistors biased in the triode region as a variable resistor to replace the degenerative resistor. By connecting the gate terminals to the center-tapped inductor, which was called spontaneous transconductance match (STM) technique, the VCO is able to automatically eliminate the signal imbalance such that high amplitude balance and low power consumption can be simultaneously achieved without using any accurate resistors.

The circuit we proposed in this chapter has slightly modified the so-called STM- technique by connecting the gate terminals to the another side of the output. Because of feedback mechanism, much better performance of transconductance matching than original one can be achieved. We give it a name modified spontaneous transconductance match (M-STM) technique. The circuit design consideration will be discussed in next section.

Fig. 2 - 4 Schematic of the conventional parallel-coupled QVCO (P-QVCO) topology

Fig. 2 - 5 Small signal equivalent circuit of the switching- and parallel-coupling transistor

Fig. 2 - 4 shows the conventional parallel QVCO (P-QVCO) where I and Q signals are generated by coupling two differential VCOs through coupling transistors M₅ - M₈ in parallel with switching transistors M1 - M4. Fig. 2 - 5 shows the small signal equivalent circuit of the switching and corresponding coupling transistors [6]. From Fig. 2 - 5, the coupling strength α between the two VCOs of the P-QVCO can be defined as

m,couple m5 5

m,switching m1 1

g g W

α= = =

g g W

where g_m,couple and gm,switching are the transconductance of coupling transistor and switching transistor, respectively. In P-QVCO, the coupling strength α has a strong effect on phase noise and phase error which defines the phase difference from 90^。between I and Q signals. For the VCO is used as the quadrature phase coupling element to the other pair. Consequently the four quadrature-coupling transistors in the conventional P-QVCO are not needed and their noise contribution to the oscillator vanishes. As mention above, the P-QVCO has trade-off between phase noise and phase error. However, in the back-gate-coupling QVCO, phase error can be reduced without sacrificing phase noise as the coupling involves no additional transistors. From Fig. 2 - 7, the coupling strength αB through the back-gate can given by

mb

where γ, ΦF, and VBS are the body-effect coefficient, work function, and back-gate (body) to source bias voltage, respectively. It can be seen that the coupling strength α_B is a function of VBS. Therefore, in order to increase αB, which leads to phase error reduction, the body-to-source reverse bias should be minimized. The usage of back-gates removes the

coupling transistors and therefore additional noise contributions compared to the conventional coupling transistor based topology.

Fig. 2 - 6 Schematic of the conventional back-gate coupling QVCO

Fig. 2 - 7 Small signal equivalent circuit of the back-gate-coupling transistor

The close-in phase noise spectrum of the circuit shown in Fig. 2 - 6 results from the flicker noise up-conversion of the NMOS and back-gate modulation PMOS transistor, which is expressed as [33]

where c₀ is the first Fourier coefficient of the impulse sensitivity function, representation the

wave form symmetry of oscillating signal. The term

2 corner frequency _{1/f Pb,} . The insertion of the resistor R_S at the NMOS source node reduces the transconductance by a factor of 1/(1+g_m,NR_s), which in turn reduces _{1/f N,} by the same factor due to the proportionality of _{1/f N,} to g_m,N for a short-channel MOS transistor [34].

The resistor RS also linearizes the degenerated transconductance variation over an oscillating swing period. Nevertheless, this method requires an accurate resistor R_S which must be properly designed because large RS may cease the oscillation start-up, introduce extra thermal noise and introduce an extra amount of power. As mention above, we propose the modified spontaneous transconductance match (M-STM) technique to conquer this problem.

The circuit we proposed in this chapter can achieve lower phase noise, lower amplitude imbalance ratio and lower power dissipation by combining the back-gate coupling principle, current-reused QVCO structure and modified spontaneous transconductance match (M-STM) technique. The circuit design consideration will be discussed in next section.

2.2 Circuit Design Consideration

The schematic of the proposed modified spontaneous transconductance match (M-STM) current reused quadrature VCO (CR-QVCO) is shown in Fig. 2 - 8. The CR-QVCO is mainly composed of two current reused differential VCO cores, which replaces one of the NMOS transistors of a conventional differential LC-VCO with a PMOS transistor[11]. The negative conductances are provided by the cross-connected pairs of transistors M1, M2, and M5, M6, to compensate the losses in the LC-tank. The series stacking of NMOS transistors and PMOS transistors allows the supply current to be reduced by half compared to that of the conventional LC-VCO while providing the same negative conductance.

Fig. 2 - 8 Schematic of proposed current reused QVCO with modified STM

Fig. 2 - 9 Proposed CR-QVCO operation during each half period

To explain the operation of the proposed CR-QVCO, Fig. 2 - 9 shows the schematic and corresponding large-signal equivalent circuits during each half period of operation, that is, when the voltage at node I+ is high and low. As shown in Fig. 2 - 9, during the first half-period, the transistor M1, M3, M5, and M7 are on and the current flows from VDD to ground through the inductor. During the second half-period, the transistor, the transistors are off and the current flows in the opposite direction through the capacitors. Note that in the conventional differential QVCO, the cross-connected transistors switch alternatively, while in the proposed QVCO, the PMOS transistors and NMOS transistors switch at the same time.

Unlike a conventional VCO where the transistors switch alternatively, this QVCO does not have a common-source node because the transistors switch on and off at the same time.

Therefore, the proposed QVCO is inherently immune to phase noise degradation caused by second-harmonic terms at the common-source node. In the conventional NMOS-based or

PMOS-based differential QVCO, the phase noise can be degraded significantly by the noise near the second harmonic[15]. Utilization of PMOS transistors in the cross-connected pair can additionally help to reduce the phase noise due to lower flicker noise and hot carrier effects[16].

Fig. 2 - 10 shows the concept of the proposed modified spontaneous match (M-STM) technique. During the first half-period, the transistor M3, M4, M7, and M8 are biased in the triode region as a variable resistor to control the gate-source voltage of M1, M2, M5, and M6,respectively, which in turn determines the transconductances of M1, M2, M5, and M6. By connecting the gate terminals to the another side of the outputs, the equivalent resistance of the variable resistor can be expressed as

Fig. 2 - 10 Concept of the proposed modified STM technique

   

of the transistor. The effective transconductances of M1, M2, M5, and M6 in Fig. 2 - 10 can be expressed, respectively, as of the transistor, Vov is the overdrive voltage, IDL and IDR is the drain current of left-half VCO

and right-half VCO, respectively.

The size of M1 - M8 are selected to satisfy the symmetric oscillation waveform condition gm1ZI- = gm5ZI+ and gm2ZQ- = gm6ZQ+ where ZI-, ZI+, ZQ-, and ZQ+ denote the impedance at node I-, I+, Q-, and Q+, respectively. When the output amplitude at node I- and I+ are different, the feedback mechanism will change the gate voltage of M1 and M5 in an opposite amount. Therefore, the g_m1 and g_m5 are complementary changed by feedback mechanism to equalize the output amplitudes. By the same token, the gm2 and gm6 are also complementary changed by feedback mechanism to equalize the output amplitudes. The comparison of amplitude ratio V3 / V1 with modified STM technique and without modified STM technique is shown in Fig. 2 - 11. Over the entire frequency tuning range, the amplitude imbalance ratio of output signals with modified STM technique is less than 0.2%, while the amplitude imbalance ratio of output signals without modified STM technique is as high as 1.7%.

Fig. 2 - 11 Simulated output amplitude imbalance ratio of the proposed modified STM-QVCO

The mechanism of the proposed modified spontaneous transconductance match (M-STM) technique can be divided into five state, as shown from Fig. 2 - 12 to Fig. 2 - 16 :

I. Ideal Case - Equal Output Level : VI+(avg) = VI-(avg) = VIdeal

As shown in Fig. 2 - 12, when the gmn and gmp has been properly designed, two outputs of the CR-QVCO will exhibit perfectly equal output level, i.e., V_I+(avg) = V_I-(avg).

We give this ideal value a name VIdeal and will be used later.

Fig. 2 - 12 The M-STM mechanism to the ideal case of the proposed CR-QVCO

II. Type 1 - Case 1 : VI+(avg) > VI-(avg) = VIdeal

As shown in Fig. 2 - 13, when the NMOS process transconductance coefficient “kn” has slightly become smaller due to process variation :

1. VI+(avg) will become larger than ideal value correspondingly.

2. The larger V_I+(avg) will lead to smaller r_ds3, and , in turn, increase V_I+(avg) toward the ideal value, which is the dashed line in the zoom in window.

Consequently, VI+(avg) will have less variation thanks to the M-STM feedback compensation.

Fig. 2 - 13 The M-STM mechanism to "Type 1 - Case 1" of the proposed CR-QVCO

III. Type 1 - Case 2 : VI+(avg) < VI-(avg) = VIdeal

As shown in Fig. 2 - 14, when the NMOS process transconductance coefficient “kn” has slightly become larger due to process variation :

1. VI+(avg) will become smaller than ideal value correspondingly.

2. The smaller V_I+(avg) will lead to larger r_ds3, and , in turn, increase V_I+(avg) toward the ideal value.

Consequently, VI+(avg) will have less variation thanks to the M-STM feedback compensation.

Fig. 2 - 14 The M-STM mechanism to "Type 1 - Case 2" of the proposed CR-QVCO

IV. Type 2 - Case 1 : VI-(avg) > VI+(avg) = VIdeal

As shown in Fig. 2 - 15, when the PMOS process transconductance coefficient “kp” has slightly become smaller due to process variation :

1. VI-(avg) will become smaller (but larger negative-half amplitude) than ideal value correspondingly.

2. The smaller VI-(avg) will lead to smaller rds7, and , in turn, increase VI-(avg)

toward the ideal value.

Consequently, V_I-(avg) will have less variation thanks to the M-STM feedback compensation.

Fig. 2 - 15 The M-STM mechanism to "Type 2 - Case 1" of the proposed CR-QVCO

V. Type 2 - Case 2 : VI-(avg) < VI+(avg) = VIdeal

As shown in Fig. 2 - 16, when the PMOS process transconductance coefficient “kp” has slightly become larger due to process variation :

1. VI-(avg) will become larger (but smaller negative-half amplitude) than ideal value correspondingly.

2. The larger VI-(avg) will lead to larger rds7, and , in turn, decrease VI-(avg) toward the ideal value.

Consequently, V_I-(avg) will have less variation thanks to the M-STM feedback compensation.

Fig. 2 - 16 The M-STM mechanism to "Type 2 - Case 2" of the proposed CR-QVCO

2.3 Chip Layout and Simulation Results

The circuit was simulated and optimized using Agilent ADS. The design procedure can be divided in two steps. First, a small signal analysis was used to optimize the feedback and the resonator elements to find the oscillation condition at the target frequency. This condition was simulated breaking the feedback path. In the second step, a large signal analysis was performed with the harmonic balance simulator to predict the exact oscillation frequency and output power of the fundamental signal as well as the harmonic signals.

Fig. 2 - 17 shows the chip layout photograph of the proposed modified STM current reused QVCO, which is designed and implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. The chip size is 1.100 × 0.841 mm² including all pads and bypass capacitances. Each buffer of the QVCO outputs were designed as a common-source amplifier.

Fig. 2 - 17 Chip layout of the proposed modified STM-QVCO

Fig. 2 - 18 Simulated phase noise of the proposed modified STM-QVCO

Fig. 2 - 19 Simulated tuning range of the proposed modified STM-QVCO

The simulated phase noise and tuning range of the proposed modified STM QVCO are shown in Fig. 2 - 18 and Fig. 2 - 19,respectively. Table 2 - 1 summarizes the simulated results of the proposed modified STM QVCO in each corner. The figure of merits (FOM) for oscillators summarizes the important performance parameters, i.e., phase noise and power consumption P, to make a fair comparison is defined in [40] as

 

^{20 log 10 log( )}

where the second term is to neutralize the effect of offset in L(Δω) while taking the center frequency into account. The power consumption is calculated as dBm such that the unit of FOM remains the same as that of L(Δω).

Table 2 - 1 Simulated results of the proposed modified STM-QVCO

Corner SS TT FF SF FS

Tuning Range

4.78-5.12 4.82-5.13 4.91-5.22 4.84-5.16 4.86-5.16 Phase

Noise

-118.645 -118.322 -118.102 -118.571 -118.313 Supply

2.4 Measurement Results and Discussion

2.4.1 Measurement Consideration

The proposed QVCO are designed for on-wafer testing, and the DC voltage are supplied by two sets of six-pin probe, so that the distance between each DC pad must more than 50μm to satisfy the probe testing rules. The output buffer of each quadrature output is designed using common-source amplifier, and the drain end of each buffer is connected to the RF pad.

For measurement, we connect four bias-tee terminals to the corresponding RF pads as shown in Fig. 2 - 20.

Fig. 2 - 20 Bias-Tee Model

The phase noise, tuning range, output spectrum and output waveform are measured using signal source analyzer (Agilent E5052B) and digital signal analyzer (Agilent DSA91204A) shown in Fig. 2 - 21and Fig. 2 - 22, respectively.

Fig. 2 - 21 Signal Source Analyzer (Agilent E5052B)

Fig. 2 - 22 Digital Signal Analyzer (Agilent DSA91204A)

Fig. 2 - 23 Chip photo of the proposed modified STM-QVCO

The Chip photo of the proposed modified STM-QVCO is shown in Fig. 2 - 23. Fig. 2 - 24 and Fig. 2 - 25 shows the arrangement of DC and RF probes. The measured phase noise at 4.84GHz, output spectrum, tuning range, output waveform, and amplitude imbalance ratio was shown in Fig. 2 - 26 to Fig. 2 - 30, respectively. Table 2 - 2 summarizes the measured performance of the proposed modified STM-QVCO.

Fig. 2 - 24 Arrangement of DC and RF probes

Fig. 2 - 25 Photograph of the probe station

Fig. 2 - 26 Measured phase noise of the proposed modified STM-QVCO

Fig. 2 - 27 Measured output spectrum of the proposed modified STM-QVCO

Fig. 2 - 28 Measured tuning range of the proposed modified STM-QVCO

Fig. 2 - 30 Measured output amplitude imbalance ratio of the proposed modified STM-QVCO

Table 2 - 2 Comparison of QVCO Performance

Chapter 3

Current-Reused Low Phase Noise Quadrature VCO with Self-Switching Bias

3.1 Introduction

Quadrature signals finds application in many communication systems. For high speed clock and data recovery systems, quadrature signals are required for frequency detection, half-rate phase noise detection, and phase interpolation [19] - [21]. For RF front-ends, quadrature signals are necessary in the implementation of image rejection and direct

Quadrature signals finds application in many communication systems. For high speed clock and data recovery systems, quadrature signals are required for frequency detection, half-rate phase noise detection, and phase interpolation [19] - [21]. For RF front-ends, quadrature signals are necessary in the implementation of image rejection and direct

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