Conclusions

Ultra-thin and highly doped SDE regions are successfully formed in the NiSi SB source/drain SOI MOSFETs by implantation-to-silicide (ITS) method and low temperature post-ITS annealing processes. Owing to the engineering of energy band near at the Ni-silicide/Si-channel interface, the modified Schottky barrier (MSB) source/drain can effectively improve both the on-state and the off-state

current-voltage properties. Moreover, current transportation mechanisms of n/p-channel Schottky barrier (SB) and n/p-channel Modified Schottky barrier (MSB) MOSFETs are identified by measuring the temperature effect on current-voltage characteristics.

For the SB MOSFETs, current transportation could be dominated by thermionic emission or tunneling mechanism depends on the Schottky barrier height and the applied electric field, i.e. the gate and drain voltages. Drift-diffusion current could occur at sufficient high electric field. The current transportation of the n/p-channel MSB MOSFETs changes from tunneling mechanism to drift-diffusion mechanism as the gate voltage increases since the SDE region can effectively reduce the effective SB height and reduced the source-side injection resistance. Once the source-side injection resistance is smaller than the channel resistance, the current transportation mechanism would be dominated by the drift-diffusion model. Furthermore, the changing point is a good indicator to evaluate the efficiency of the MSB junction.

Sufficient post-ITS thermal budget is required to obtain high performance MSB MOSFET. Since the current transport mechanism depends on bias condition, the extraction of mobility should be treated carefully, especially at low gate voltage. In addition, the bias condition would affect the SB properties and modify the series resistance of MSB MOSFETs. In next chapter, a novel modified external method will be proposed to extract the bias dependent series resistance.

References

[1] J. Kedziersk, P. Xuan, E. H. Andersonf, J. Bokor, T.-J. King, C. Hu,

“Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime,” in IEDM Tech. Dig., 2000, pp.57-60.

[2] S. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L.

Kwong, “Schottky-Barrier S/D MOSFETs With High-K Gate Dielectrics and Metal-Gate Electrode,” IEEE Electron Device Lett., vol. 25, no. 5, pp. 268-270, 2004.

[3] M. Jang, Y.Kim, J. Shin, S. Lee, and K. Park, “ A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor,” App. Phys. Lett., vol. 84, no. 5, pp. 741-743, 2004.

[4] R. T. P. Lee, A. E.-J. Lim, K.-M. Tan, T.-Y. Liow, G.-Q. Lo, G. S. Samudra, D.

Z. Chi, and Y.-C. Yeo, “N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide.” IEEE Electron Device Lett., vol. 28, no. 2, pp. 164-167, 2004.

[5] J. Knoch, M. Zhang, Q. T. Zhao, St. Lenk, S. Mantl, and J. Appenzeller,

“Effective Schottky barrier lowering in silicon-on-insulator Schottky-barrier metal-oxide-semiconductor field-effect transistors using dopant segregation,”

App. Phys. Lett., vol. 87, no. 26, p. 263505, 2005.

[6] J. Knoch and J. Appenzeller, “Impact of the channel thickness on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 81, no. 16, pp. 3082-3084, 2002.

[7] H. C. Lin, M. F. Wang, F. J. Ho, J. T. Liu, Y. Li, T. Y. Huang, and S. M. Sze,

“Effects of sub-gate bias on the operation of Schottky-barrier SOI MOSFETs having nano-scale channel,” in IEEE Conf. Nanotechnology (NANO), 2002, pp.

205–208.

[8] S. Xiong, T.-J. King, and J. Bokor, “A Comparison Study of Symmetric Ultrathin-Body Double-Gate Devices With Metal Source/Drain and Doped Source/Drain,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, 2005.

[9] Bing-Yue Tsui and Chia-Pin Lin, “A novel 25 nm modified-Schottky-barrier FinFET with high performance,” IEEE Electron Device Lett., vol. 25, no.6, pp.

430-432, 2004.

[10] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida and J. Koga, “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique,” in VLSI Symp. Tech. Dig., 2004, pp. 168-169.

[11] M. Zhang, J. Knoch, Q.T. Zhao, A. Fox, St. Lenk, and S. Mantl, “Low temperature measurements of Schottky-barrier SOI-MOSFETs with dopant segregation,” Electronics Letters, vol. 41, no. 19, pp. 1085-1086, 2005.

[12] S. P. Murarka, Silicides for VLSI application, New work: Academic, 1983, p.

130.

[13] J. P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson, J. Ruan, L.

Tsung, R. Kuan, T. Grider, D. Mercer, C. Montgomery, “A novel nickel salicide process technology for CMOS devices with sub-40 nm physical gate length,” in IEDM Tech. Dig., 2002, pp. 371-374.

[14] A. Kinoshita, T. Kinoshita, Y. Nishi, K. Uchida, S. Toriyama, R. Hasumi, and J.

Koga, “Comprehensive Study on Injection Velocity Enhancement in

Dopant-Segregated Schottky MOSFETs,” in IEDM Tech. Dig., 2006,, pp. 79-82.

[15] S. M. Sze, Physics of Semiconductor Devices, 2 ed., John Wiley & Sons, 1981, pp. 263-264.

[16] S. M. Sze, Physics of Semiconductor Devices, 2 ed., John Wiley & Sons, 1981, p.

292.

Si(40nm)

Si

₃

N

₄

SiO

₂

Hard Mask Poly-Si

Buried Oxide Si(40nm)

Si

₃

N

₄

SiO

₂

Hard Mask Poly-Si

Buried Oxide

(a)

P

₃₁⁺

Ni Silicide

Buried Oxide

P

₃₁⁺

Ni Silicide

Buried Oxide

(b)

n ⁺ SDE n+ SDE

Buried Oxide

n ⁺ SDE n+ SDE

Buried Oxide

(c)

Buried Oxide Buried Oxide

(d)

Fig. 2-1 Process flow of the double-gate n-channel MSB MOSFETs.

Si(40nm)

Si

₃

N

₄

Poly-Si SiO

₂

Buried Oxide

Si(40nm)

Si

₃

N

₄

Poly-Si SiO

₂

Buried Oxide

(a)

Buried Oxide BF

₂⁺

Ni Silicide

Buried Oxide BF

₂⁺

Ni Silicide

(b)

Buried Oxide

P

⁺

SDE P

⁺

SDE

Buried Oxide

P

⁺

SDE P

⁺

SDE

(c)

Buried Oxide Buried Oxide

(d)

Fig. 2-2 Process flow of the tri-gate p-channel MSB MOSFETs.

Fig. 2-3(a) Transfer characteristics of n-channel double-gate SB MOSFET with LG=5 µm, and W_Fin=0.08 µm.

Fig. 2-3(b) Transfer characteristics of p-channel double-gate SB MOSFET with L_G=5 µm, and W =0.08 µm.

0.0 0.5 1.0 1.5 2.0

Φ Φ Φ Φ b n

Φ Φ Φ Φ b n

Fig. 2-5(a) Schematic energy band diagram of the n-channel SB MOSFETs operates at the on-state.

Φ Φ Φ Φ Φ b p

Φ Φ Φ b p

Fig. 2-5(b) Schematic energy band diagram of the n-channel SB MOSFETs operates

Source Channel Drain

Φ Φ Φ Φ b p

Source Channel Drain Source Channel Drain

Φ Φ Φ Φ b p

Fig. 2-6(a) Schematic energy band diagram of the p-channel SB MOSFETs operates at the on-state.

Source Channel Drain

Φ Φ Φ Φ _b ⁿ

Source Channel Drain Source Channel Drain

Φ Φ Φ Φ _b ⁿ

Fig. 2-6(b) Schematic energy band diagram of the p-channel SB MOSFETs operates at the off-state.

Φ Φ Φ Φ _b ⁿ

Fig. 2-7(a) Schematic energy band diagrams of the n-MSB MOSFET at on-state.

Φ Φ Φ Φ _b ^p

Fig. 2-7(b) Schematic energy band diagrams of the n-MSB MOSFET at off-state.

-2 -1 0 1 2 3

Fig. 2-8(a) Transfer characteristics of the n-channel double-gate MSB MOSFET with L_G=5 µm, and W_Fin=0.08 µm.

Drain Channel

P ⁺ P ⁺

Source Channel Drain

P ⁺ P ⁺

Source

Φ Φ Φ Φ b p

Fig. 2-9(a) Schematic energy band diagrams of the p-MSB MOSFET at on-state.

P ⁺

Drain Channel

Source P ⁺ P ⁺

Drain Channel

Source P ⁺

Φ Φ Φ Φ

b n

Fig. 2-9(b) Schematic energy band diagrams of the p-MSB MOSFET at off-state.

-3 -2 -1 0 1 2 gate length equals to 0.5 µm and fin width equals to 0.3 µm.

-2.0 -1.5 -1.0 -0.5 0.0

Fig. 2-10(b) Output characteristics of the p-channel tri-gate MSB MOSFET with gate length equals to 0.5 µm and fin width equals to 0.3 µm.

-2 -1 0 1 2 10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

I

DS

(A )

V

_GS

(V) 300K 350K 400K

V

_DS

=1.0V

V

_DS

=0.05V

Fig. 2-11 Transfer characteristics of the n-channel SB MOSFET with gate length equals to 5 µm and fin width equals to 80 nm.

-3 -2 -1 0 1 2 3

Fig. 2-12(a) Transfer characteristics of the n-channel SB MOSFET shown in Fig. 11 in linear scale with VDS=0.05 V.

Fig. 2-12(b) Transfer characteristics of the n-channel SB MOSFET shown in Fig. 11 in linear scale with V_DS=1.0 V.

-2 -1 0 1 2 10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

V

_DS

=-1.0V

V

_DS

=-0.05V

300K 350K 400K

I

DS

(A )

V

GS

(V)

Fig. 2-13 Transfer characteristics of the p-channel SB MOSFET with gate length equals to 5 µm and fin width equals to 80 nm.

-3 -2 -1 0 1 2 3

Fig. 2-14(a) Transfer characteristics of the p-channel SB MOSFET shown in Fig. 13 in linear scale with V_DS= -0.05 V.

Fig. 2-14(b) Transfer characteristics of the p-channel SB MOSFET shown in Fig. 13 in linear scale with V_DS= -1.0 V.

-2 -1 0 1 2 10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

V

_DS

=1.0V

V

_DS

=0.05V

300K 350K 400K

I

DS

(A )

V

_GS

(V)

Fig. 2-15 Transfer characteristics of the n-channel MSB MOSFET with gate length equals to 5 µm and fin width equals to 80 nm.

-2 -1 0 1 2 3

-2 -1 0 1 2 3 0.0

0.1 0.2 0.3 0.4

0.5 n-channel MSB MOSFET W/L=0.08 µ µ µ µ m/5 µ µ µ µ m

300K 350K 400K

I

DS

( µµµµ A )

V

_GS

(V) V

_DS

=0.05V

Dash Line: 600

^o

C 30sec Solid Line: 600

^o

C 30min

Intersecting Point

Fig. 2-17 Transfer characteristics of the n-channel MSB MOSFET in linear scale with VDS=0.05 V and the post-ITS annealing at 600 ºC for 30 sec or for 30 min.

-2 -1 0 1 2 10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

V

_DS

=1.0 V

V

_DS

=0.05 V

I

DS

( µµµµ A )

V

_GS

(V)

600

^o

C, 30sec 600

^o

C, 30min

n-channel MSB MOSFET W/L=0.08 µ µ µ µ m/5 µ µ µ µ m

Fig. 2-18 Transfer characteristics of the n-channel MSB MOSFET with the post-ITS annealing at 600 ºC for 30 sec or for 30 min.

-3 -2 -1 0 1 2 10

^-14

10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

V

_DS

= -1.0V

300K 350K 400K I

DS

(A )

V

_GS

(V)

V

_DS

= -0.05V

Fig. 2-19 Transfer characteristics of the p-channel MSB MOSFET with gate length equals to 0.5 µm and fin width equals to 0.3 µm.

-3 -2 -1 0 1 2

Chapter 3

Extraction of Bias-Dependent Source Injection Resistance of Modified Schottky Barrier

MOSFET

3.1 Introduction

As the CMOS device scales down, multi-gate structure has been reported as a promising candidate to replace the present planar CMOS since it exhibits significant reduction of the short channel effect and extremely well gate controllability [1-4].

Additionally, multi-gate structure, such as FinFET, not only utilizes the top channel but also uses the side-wall channel to conduct source and drain in the on-state, which can enhance current driving capability by increasing the effective channel width.

However, as scaling the device, the channel width shrinks and the series resistance outside the channel region gets much larger. The parasitic source/drain resistance (R_SD) would become a critical issue for CMOS scaling to nanometer regime [5]. Therefore, metal-silicde source/drain or the so-called Schottky barrier (SB) source/drain MOSFETs are proposed to minimize the R_SD, especially for the sheet resistance of source/drain electrodes. Moreover, SB MOSFET also shows some advantages, such as easy processing, low thermal budget, good drain-induced barrier lowing, and better short channel effect. It has been considered as one of the candidates for future

nano-scale devices [6-10]. Nevertheless, poor on/off-state properties and ambipolar characteristic are the drawbacks of SB MOSFETs due to the SB at source/drain junction.

Recently, by using implantation-to-silicide (ITS) method or dopant segregation method to place an highly-doped interfacial layer between the silicided source/drain and Si-channel region, the modified Schottky barrier (MSB) MOSFETs are realized and have been proposed to improve the driving current and reserve the advantages of SB MOSFETs such as better short channel effect and less drain-induced-barrier-lowering [3-4, 11-12]. Although the effective SB height is reduced by the MSB technology to enhance the carrier injected efficiency at source-side, some topics on the MSB junction and MSB MOSFETs are worthy for understanding. Several literatures have been devoted to evaluate the efficiency of the MSB junction. M.

Zhang et al. reported that the effective Schottky barrier height can be reduced to about 0.1 eV at high gate bias [13]. A. Kinoshita et al. reported the carrier injection velocity enhancement associated with the velocity overshoot [12]. In chapter 2, it has been also reported that the current transportation mechanism of SB and MSB MOSFETs would change from the thermionic emission to the tunneling and then to the drift-diffusion as the gate bias increases. While the source-side injection resistance is smaller than the channel resistance, the current transportation mechanism is changed from the thermionic emission or tunneling to drift diffusion. The gate bias of the changing point decreases with increasing the thermal budget of MSB junction formation.

However, the source injection resistance and its gate bias dependence have not been reported. In this chapter, a modified external loading method is proposed to successfully extract the bias dependent source/drain resistance of MSB MOSFETs.

The gate-bias dependent source injection resistance of MSB MOSFETs can be

observed no matter the integrated material of gate dielectric layer. This observation provides a good indicator to evaluate the efficiency of the MSB junction and would be useful for device and circuit simulation.

3.2 Devices Fabrication

Various n-channel multi-gate MSB MOSFETs were fabricated with different gate dielectrics layers, including HfAlO high-k dielectric and SiO2 dielectric. The n⁺ MSB source/drain junction was formed by the ITS technique. The detail process flow of MSB MOSFET has been described in the previous chapter. Therefore, we only list some important processes and structure parameters here.

For the n-channel double-gate MSB MOSFET with HfAlO gate dielectric layer, the starting material was boron-doped 6 inch’s SOI wafer with a doping concentration of around 1x10¹⁵ cm^-3. The thickness of the Si layer was thinned down to 40 nm and the buried oxide layer was 150-nm-thick. Then, a thick SiO₂ hard mask layer was deposited on the active layer so that only sidewall channel could be conducted. Before the 3-nm-thick HfAlO high-k layer was deposited by an atomic layer deposition (ALD) system, the chemical SiO2 was formed with around 1-nm-thick. Hence, the high-k gate stacks were formed. Then, 40-nm-thick poly-Si layer was deposited followed by gate pattern definition by e-beam lithography and plasma dry etching, as shown in Fig. 3-1(a). Then, a SiO2 (10nm)/Si3N4 (20nm) composite spacer was formed, as shown in Fig. 3-1(b). The source/drain region was converted into NiSi completely by a 2-step annealing silicide process. Additionally, since the thickness of poly-Si gate is similar to that of the source/drain Si layer, Ni fully-silicided (FUSI) gate structure was obtained, as shown in Fig. 3-1(c). To form the MSB source/drain

junction, P31+

ions were implanted into the nickel silicide (ITS) at 20 keV to a dose 5x10¹⁵ cm^-2 followed by a post-ITS annealing step at 600 °C for 30 min. (sample A) or 30 sec. (sample B). During this annealing step, phosphorus atoms diffused out of the silicide and piled up at the Si/silicide interface to form the MSB junction, as shown in Fig. 3-1(d) [14].

For the n-channel double-gate MSB MOSFET with SiO2 gate dielectric layer, a 3-nm-thick SiO₂ was thermally grown as the gate dielectric followed by a 150-nm-thick poly-Si film deposition. The poly-Si gate was doped by P31+

ion implantation at 40 keV to a dose 5x10¹⁵ cm^-2 followed by a rapid thermal activation at 1025 °C for 10 sec. Then, after the same aforementioned process flow for the spacer formation and Ni-salicide process, the source/drain region was converted to NiSi completely.

Additionally, polycide gate electrode was built, simultaneously. Then, n⁺ MSB junction were formed by the ITS method and followed by post-ITS annealing step at 600 °C for 30 min. (sample C) or 30 sec. (sample D). For the reference devices with 3-nm-thick SiO₂ gate dielectric layer and conventional pn source/drain junction, phosphorus ions were implanted into the source/drain region at 10 keV to a dose 5x10¹⁵ cm^-2 followed by a rapid thermal activation at 1025 °C for 20 sec. The silicide thickness is about 25 nm. Table 1 lists the important structure parameters of these five samples.

Figure 3-2(a) and Fig. 3-2(b) show the typical transfer characteristics and output characteristics of the n-channel MSB MOSFET with HfAlO gate dielectric layer and different thermal budget of post-ITS annealing, i.e. sample A and sample B. Gate length (L_G) equals to 0.2 µm and fin width (W_Fin) equals to 5 µm. Due to the successful work from the thin and high concentration source/drain extension layer, the features of the SB MOSFET such as ambipolar and sub-linear current-voltage

characteristics are completely annihilated. Sample A with larger thermal budget of the post-ITS annealing shows better on/off current ratio and larger driving current, indicating more dopants pile-up at the silicide/si interface and modified the SB more strongly. Moreover, Fig. 3-3(a) and Fig. 3-3(b) show the typical transfer characteristics and output characteristics of the n-channel MSB MOSFET with SiO₂ gate dielectric layer and different thermal budget of post-ITS annealing, i.e. sample C and sample D. Gate length (LG) and fin width (WFin) equal to 0.08 µm and 5 µm, respectively.

在文檔中 具多閘極之修正蕭基位障電晶體及氮化鈦奈米晶粒記憶體之研究 (頁 59-90)