Bias-Dependent Source Injection Resistance of MSB MOSFETs

According to the above observations, the complete bias-dependent source injection of MSB MOSFET can be obtained from the small gate bias, i.e. slightly larger than VTH, to the high gate bias by applying modified ELM and choosing suitable external loads. Figure 3-14 presents the -R_L0 versus 1/(V_GS-V_TH-0.5V_DS) plot of sample C at VDS = 0.05 V to 0.3 V. These curves imply that the resistance of MSB junction varies as the gate voltage increases to reduce the effective SB height. Figures 3-15 (a) and (b) display the extracted series resistance of sample C as a function of 1/(VGS-VTH-0.5VDS) in linear scale and log scale, respectively. When biasing at (VGS -VTH-0.5VDS) = 0.035 V and VDS = 0.05 V, the RT is 79k Ω. Then, as the (VGS-VTH -0.5V_DS) increases, the R_T reduces dramatically and decays exponentially till to (V_GS

-VTH-0.5VDS) around 0.5 V. Moreover, this resistance reduction saturates at higher (V_GS-V_TH-0.5V_DS) bias and the R_T is close to that of the conventional MOSFET.

Similar behaviors are also observed in the sample D which has less thermal budget.

Figure 3-16 (a) and (b) display the extracted series resistance of sample D as a function of 1/(V_GS-V_TH-0.5V_DS) in linear scale and log scale, respectively. Although some fluctuations due to the non-ideal probe contact with the NiSi pads, clear trend of the resistance reduction can be obtained. Therefore, from the aforecited observations, the modified SB still not low and thin enough while the gate bias is only slightly larger than the threshold voltage and the extracted series resistance is mainly came from the source-side modified SB, indicating that the carrier transportation mechanisms would be affected by these modified SB in this situation. As the gate bias increases, the source-side SB gets thinner and lower. Moreover, while the gate bias is large enough, the modified SB at source-side can be seen as transparent for the carrier transportation. Hence, the extracted series resistance is constant and mainly comes from the resistance outside the MSB source/drain junction, which is similar to that of the conventional MOSFET.

3.4 Conclusions

In this chapter, a modified external load resistance method was proposed to extract the bias dependent source injection resistance of the MSB MOSFET no matter what dielectrics are used as the gate dielectric layer. To use this method to extract source injection resistance at small gate bias condition, which is slightly larger than the threshold voltage, moderate larger RL must be selected. The bias dependent source injection resistance is observed. The source injection resistance is exponentially

proportional to (VGS-VTH-0.5VDS) and saturates at moderate high gate voltage, which the source/drain resistance of MSB MOSFET would be close to that of the conventional MOSFET at that gate bias. This observation indicates that the modified SB still dominate the carrier transportation at small gate bias but it would be vanished and became transparent for the current flow at moderate high gate bias condition.

Additionally, without sufficient post-ITS thermal budget, the source injection resistance can not be suppressed effectively at reasonable VGS. Moreover, the proposed modified external loading method provides a good method to evaluate the efficiency of the MSB junction directly.

References

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Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, “FinFET scaling to 10 nm gate length,” in IEDM Tech. Dig., 2002, pp. 251-254.

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Bokor, and C. Hu,“Sub-60-nm Quasi-Planar FinFETs Fabricated Using a Simplified Process,” IEEE Electron Devices Lett., vol. 22, no. 10, pp. 487-489, 2001.

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Kinoshita, J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi, Y. Tsunashima, “High-Performance FinFET with Dopant-Segregated Schottky Source/Drain,” in IEDM Tech. Dig., 2006, pp. 893-896.

[5] S. D. Kim, C. M. Park, and J. C. S. Woo, “Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime-Part : Quantitative Analysis,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 467-472, 2002.

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1420, 1995.

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MOSFETs by Using Schottky Source/Drain Contacts,” Jpn. J. Appl. Phys., vol.

37, pp. 1295-1299, 1998.

[9] C. Wang, J. P. Synder, and J. R. Tucker, “Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors,” Appl. Phys.

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[10] W. Saitoh, S. Yamagami, A. Itoh, and M. Asada, ” 35 nm metal gate p-type metal-oxide- semiconductor field-effect-transistor with PtSi Schottky source/drain on separation by implanted oxygen substrate,” Jpn. J. Appl. Phys., vol.38, pp. 629-631, 1999.

[11] A. Kinoshita, Y. Tsuchiya, A. Yagishita*, K. Uchida and J. Koga, “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique,” in VLSI Symp. Tech. Dig., 2004, pp. 168-169.

[12] A. Kinoshita, T. Kinoshita, Y. Nishi, K. Uchida, S. Toriyama, R. Hasumi, and J.

Koga, “Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs,” in IEDM Tech. Dig., 2006, pp. 79-82.

[13] M. Zhang, J. Knoch, Q.T. Zhao, A. Fox, St. Lenk, and S. Mantl, “Low temperature measurements of Schottky-barrier SOI-MOSFETs with dopant segregation,” Electronics Letters, vol. 41, no. 19, pp. 1085-1086, 2005.

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Length and Series Resistance of LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. 34, no.12, pp. 2469-2475, 2005.

Table 3.1: The important structure parameters of samples A-E.

Gate Electrode

Gate Dielectric

Layer

Source/Drain junction type

S/D Activation Condition

A FUSI

HfAlO/SiO

x

= 3 nm/1 nm

n

⁺

MSB 600

^o

C, 30 min.

B FUSI

HfAlO/SiO

x

= 3 nm/1 nm

n

⁺

MSB 600

^o

C, 30 sec.

C Polycide SiO

2

= 3 nm n

⁺

MSB 600

^o

C, 30 min.

D Polycide SiO

₂

= 3 nm n

⁺

MSB 600

^o

C, 30 sec.

E Polycide SiO

2

= 3 nm Conventional 1025

^o

C, 20 sec.

(a)

(b)

(c)

(d)

Fig. 3-1 Main Process flow of n-channel double-gate MSB MOSFET with HfAlO gate dielectric layer.

-2 -1 0 1 2

Fig. 3-2(a) Transfer characteristics of the n-channel MSB MOSFET with HfAlO gate dielectric layer and two different post-ITS annealing.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Fig. 3-2(b) Output characteristics of the n-channel MSB MOSFET with HfAlO gate dielectric layer and two different post-ITS annealing.

-2 -1 0 1 2

Fig. 3-3(a) Transfer characteristics of the n-channel MSB MOSFET with SiO₂ gate dielectric layer and two different post-ITS annealing.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Fig. 3-4 The Effective circuit diagram of the external loading method. An external load resistor with suitable range of impendence is connected to the source terminal.

-2000 -1000 0 1000 2000 0.0

0.2 0.4 0.6

V

_GS

-V

_TH

= 0.6V~1.0V V

_GS

-V

_TH

=0.4V

I

DS

-1

( µµµµ A )

-1

R

_L

( Ω Ω Ω Ω )

V

_GS

-V

_TH

=0.2V Conv. S/D MOSFET

(sample E)

Fig. 3-5 The 1/I_DS versus R_L plot of the conventional pn source/drain MOSFET with SiO₂ gate dielectric layer (sample E).

0 1 2 3 4 5 6 7 0

5 10 15 20

-R

L0

( k Ω - µ m )

(V

_GS

-V

_TH

-0.5V

_DS

)

^-1

(V

^-1

) R

_T

=1.13 k Ω− Ω−µ Ω− Ω− m

Conv. S/D MOSFET

Fig. 3-6 The -R_L0 versus 1/(V_GS-V_TH-0.5V_DS) plot of sample E. The inset displays the illustration of device structure.

-800 -400 0 400 800

0 1 2 3 4 5 6 0

25 50 75

R

_T

~20k

^Ω

- µ µ µ µ m R

_T

~8k

Ω

- µ µ µ µ m

-R

L0

( k Ω − µ m )

(V

_GS

-V

_TH

-0.5V

_DS

)

^-1

(V

^-1

)

R

_T

~0k

Ω

- µ µ µ µ m

MSB MOSFET

Fig. 3-8 The -R_L0 versus 1/(V_GS-V_TH-0.5V_DS) plot of sample C. The inset displays the illustration of device structure.

0.0 0.1 0.2 0.3 0.4 0.5 10

⁰

10

¹

10

²

MSB @ 600

^o

C 30 sec.

MSB @ 600

^o

C 30 min.

R

T

( k Ω − µ m )

(V

_GS

-V

_TH

-0.5V

_DS

) (V) R

_T

@ V

_DS

=0.05V

Fig. 3-9 Extracted R_T as a function of (V_GS-V_TH-0.5V_DS) of the MSB MOSFET SiO2

gate dielectric layer and two different post-ITS annealing (sample C and sample D).

0 2 4 6 8 10 12

0.0 0.1 0.2 0.3 0.4 0.5 10

⁰

10

¹

10

²

10

³

MSB @ 600

^o

C, 30sec.

R

T

( k Ω − µ m )

V

_GS

-V

_TH

-0.5V

_DS

(V) MSB @ 600

^o

C, 30min.

V

DS

= 0.1 V

Fig. 3-11 Extracted RT as a function of (VGS-VTH-0.5VDS) of the MSB MOSFET with HfAlO gate dielectric layer and two different post-ITS annealing (sample A and sample B).

0 2 4 6 8 10 0.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

R

_L

(k Ω Ω Ω Ω )

I

DS

-1

( µµµµ A )

-1

MSB MOSFET (sample A)

V

_GS

-V

_TH

=0.2~0.4 V

Fig. 3-12 The 1/IDS versus RL plot of MSB source/drain MOSFET with HfAlO gate dielectric layer (sample A). Smaller loads are used to extract the R_T.

0 10 20 30 40 50 60 70 80 90 100 0.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

R

L

(k Ω Ω Ω Ω )

I

DS

-1

( µµµµ A )

-1

MSB MOSFET (sample A)

V

_GS

-V

_TH

=0.2~0.4 V

Fig. 3-13 The 1/I_DS versus R_L plot of MSB source/drain MOSFET with HfAlO gate dielectric layer (sample A). Larger loads are used to extract the RT.

0 10 20 30 40 50 0

20 40 60 80

100 (sample C)

V

_TH

=0.8V

(V

GS

-V

TH

-0.5V

DS

)

^-1

(V

^-1

)

Vd=0.05V Vd=0.1V Vd=0.15V Vd=0.2V Vd=0.25V Vd=0.3V

MSB @ 600

^o

C 30min

-R

L0

(k ΩΩΩΩ − µ − µ − µ − µ m )

Fig. 3-14 The -RL0 versus 1/(VGS-VTH-0.5VDS) plot of MSB MOSFET with SiO2 gate dielectric layer (sample C) at VDS = 0.05 V to 0.3 V.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig. 3-15(a) Extracted series resistance of sample C as a function of (VGS-VTH-0.5VDS) in the linear scale.

Fig. 3-15(b) Extracted series resistance of sample C as a function of (VGS-VTH-0.5VDS) in the log scale.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig. 3-16(a) Extracted series resistance of sample D as a function of (V_GS-V_TH-0.5V_DS) in the linear scale.

Fig. 3-16(b) Extracted series resistance of sample D as a function of (VGS-VTH-0.5VDS) in the log scale.

Chapter 4

Nano-scale Multi-gate TiN Metal Nanocrystal Memory

4.1 Introduction

Integrating multi-gate structure into the CMOS device provides lots of advantages and helps for the further scaling of CMOS technology. In the previous two chapters, we focus on the modified Schottky barrier MOSFET with multi-gate structure. In fact, the nonvolatile memory has also been considered to change its planar structure to the three-dimensional structure. In addition, some inevitable issues would rise as scaling nonvolatile memory, which is mainly originated from the storage material and it is suspected to use another applicable material as the new storage node. In this chapter, we propose a novel flash memory which integrates with the multi-gate structure.

Since 1967, D. Kahng and S. M Sze has invented the first floating gate nonvolatile memory (NVM) at Bell Lab [1], the industry of nonvolatile memory developed extremely fast in the past four decades and the floating gate (FG) devices are widely applied in present NVM for data storage. Floating gate NVM has the following advantages: large memory window, high program/erase (P/E) speed, and good reliability for commercial applications. In recent years, flash memory becomes

one of the fastest growing semiconductor technologies and provides hundreds of portable electronic products. However, the International Technology Roadmap for Semiconductors (ITRS) forecasts that several critical challenges would limit the conventional FG memory scaling around 25 nm node [2]. The main issue is un-scalable tunneling oxide thickness for maintaining acceptable retention performance.

Therefore, a high operation voltage is required and the thickness of tunneling oxide layer is predicted to keep at 6-7 nm [2]. Additionally, an increased floating gate coupling effect is another issue for the continually closing floating gate memory cells.

Therefore, NAND technology is projected to migrate to the charge trapping devices with discrete traps for charge storage, such as silicon/ oxide/ nitride/ oxide/ silicon (SONOS) and nanocrystal structures [2].

SONOS-type memories which store charges in the discrete trap node of theirs silicon nitride layer exhibit improved retention performance so that the tunneling oxide thickness can be reduced to increase the P/E speed and decrease operation voltage [3-8]. Besides, some advanced SONOS memories such as bandgap engineered SONOS (BE-SONOS) and TaN/ Al₂O₃/ nitride/ oxide/ silicon (TANOS) have demonstrated high P/E speed and have attracted much attention for applying in the future NVM [9-10]. Unfortunately, all SONOS-type memories exhibit erase saturation phenomenon [11] and unwanted migration of stored charges in the nitride layer [12].

Some storage electrons still leak to control gate or channel if they are trapped at the shallow levels in the silicon nitride layer. Hence, nanocrystal memories which use various materials as the storage node such as Si, Ge, HfO2, Pt, Ag, Au, Ni and TiN have been proposed and have become another possible solution for the future NVM applications [13-26]. Nanocrystal memories may have better charge storage ability than SONOS-type memory since each nanocrystal is theoretically isolated by the

surrounding dielectric. Therefore, a thinner tunneling oxide can be used to improve P/E speed and reduced P/E operation voltage without degrading retention performance. In addition, metal nanocrystals have better work function engineering ability and higher density of state around the Fermi level than semiconductor nanocrystals [17-24]. However, nanocrystal memories still have some challenges, such as how to formation nanocrystals with high density, constant size and uniform distribution [23-26].

Recently, multi-gate field effect transistors (MuGFETs) were predicted as one of the most potential solution for the NAND Flash beyond 22 nm node, and various SONOS-type and nanocrystal memories have been fabricated with multi-gate structure [2]. It has been reported that the multi-gate memory cell can achieve excellent short channel effect controllability, higher driving current, lower leakage current, better gate coupling ratio, better programming inhibition, and more numbers of nanocrystals in one cell [3-6, 13, 19]. Furthermore, the potential of floating fin-type body is modulated in the multi-gate structure which is different than that in the single gate structure and exhibits longer charge retention time [13, 30]. Moreover, TiN nanocrystal memories with a high density of TiN nanocrystals can be formed in the surrounding Al₂O₃ dielectric and these memories can exhibit larger hysteresis memory window which has potential to be used in the multilevel operation [21, 23].

In this chapter, n-channel multi-gate metal nanocrystal memory using TiN nanocrystals, an Al₂O₃ high-k blocking dielectric layer, and a P⁺ poly-Si gate electrode was fabricated on a silicon-on-insulator (SOI) wafer. The work function of TiN is extracted around 4.6 eV [21, 27]; it is expected to provide a level 0.6 eV deeper than that of Si nanocrystal to improve the retention performance. The high-k dielectric, Al2O3, has an energy bandgap similar to SiO2 but has higher gate to

channel coupling efficiency. Therefore, using Al2O3 as blocking dielectric layer can lower P/E operation voltage. In addition, using high work function gate electrode can enhance the erase characteristic by suppressing the unwanted back-side injection effect [6]. Moreover, the nanocrystal size effects on memory window, P/E speed, and retention property would also been discussed.

4.2 Devices Fabrication

Figure 4-1 shows the main process flow of the n-channel multi-gate TiN nanocrystal memory cell. The starting material is a 6 inches separation-by-implanted-oxygen (SIMOX) SOI wafer with 40-nm-thick SOI layer and a 150-nm-thick buried oxide layer. The SOI layer is lightly boron-doped and the doping concentration is around 1x10¹⁵ cm^-3. The Si fins in the <110> direction were patterned by e-beam lithography and plasma dry etching. Next, a very thin 3.6-nm-thick tunneling oxide layer was thermally grown using a furnace system at 800 °C. Then, in order to provide a material for forming nanocrystals and its surrounding material, a TiN wetting layer with thickness equals to 0.5 or 0.7 nm and an Al₂O₃ layer with thickness equals to 1 nm were sequentially deposited with seven periods in a plasma enhanced atomic layer deposition/ atomic layer deposition (PEALD/ALD) clustered system and a 15- or 20-nm-thick Al₂O₃ layer was deposited consecutively as the blocking dielectric layer in the same ALD system followed by a 150-nm-thick amorphous Si deposition at 545 °C as the gate electrode. The TiN layers were deposited with TiCl4

as a precursor at 350 °C in N₂/H₂ gas ambient and the Al₂O₃ layers were deposited with trimethylamine (TMA) and H2O as precursors at 300 °C. Next, post deposition annealing (PDA) was performed at 900 °C for 10 sec or 40 sec in nitrogen gas

ambient to provide sufficient surface mobility to transform the TiN wetting layer into nanocrystals [17-18].

In order to estimate the effect of charge trapping layer engineering, a set of devices with various TiN wetting layer thicknesses, blocking dielectric thicknesses, and PDA times were fabricated. The sample ID and process parameters are listed in Table 4-1. The TiN wetting layer thickness of sample A (0.7 nm) is thicker than that of the other samples (0.5 nm). Sample B has the longest PDA time (40 sec) among all the samples. Moreover, sample D has the thinnest blocking dielectric thickness (15 nm). The poly-Si gate was doped by BF2+

ion implantation at 40 keV to a dose of 5x10¹⁵ cm^-3 followed by activation at 900 °C for 20 sec in nitrogen gas ambient.

Before gate definition by e-beam lithography and dry etching, a thick TEOS oxide layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 695 °C as a hard mask to avoid the anti-doping of poly-Si gate during the n⁺ source/drain (S/D) dopants implantation. The device structure in this process step is shown in Fig.

4-1(a).

Next, a SiO_x (10 nm)/SiN_x (40 nm) stack layers were deposited by plasma-enhanced chemical vapor deposition (PECVD) at 300 °C and dry-etched to form a composite spacer as shown in Fig. 4-1(b). Then, P₃₁⁺ ions were implanted in S/D areas at 20 keV to a dose of 5x10¹⁵ cm^-3 and rapid thermal annealing (RTA) at 900 °C for 20 sec was performed to activate the S/D dopants. Then, a TEOS hard mask and a native oxide were selectively etched using HF solution and a 25-nm-thick Ni layer was deposited by e-gun evaporation followed by a two-step self-aligned Ni-silicide process to obtained better controllability of Ni silicide lateral formation. The first silicidation step was vacuum annealing at 300 °C for 45 min and the Ni silicide was formed in the Ni2Si phase. After removing the unreacted Ni film by H2SO4:H2O2 (3:1)

solution at 75 °C, the second silicidation step was performed at 600 °C for 30 sec to transform the NiSi₂ phase to the NiSi phase. The S/D region was converted into a full NiSi structure, as shown in Fig.4-1(c). The gate electrode became a polycide structure after the silicidation.

All the measured cells have the same device dimensions with gate length equals to 80 nm and fin width equals to 50 nm, as shown in Fig. 4-2. The cross-sectional transmission electron microscopy (TEM) images of the fabricated tri-gate nanocrystal memory (sample B) with a gate length of 80 nm and a fin width of 50 nm are shown in the Figs. 4-2(a) and (b), respectively. Moreover, Ni silicides are formed in the S/D region and the top of the gate electrode. Figure 4-3(a) and (b) show high resolution TEM images of samples A and B to magnify the charge trapping layer. The tunneling oxide thickness is around 3.6 nm and TiN nanocrystals embedded in Al2O3 are observed. Note that the diameter of TiN nanocrystal in sample A is around 3 nm, which is larger than that in sample B of about 1-2 nm because sample A has a thicker TiN wetting layer which provides more source material to form larger TiN nanocrystals than that of sample B. In the next section, we will show that nanocrystal size has a marked effect on memory performance as previously reported in literature [20, 28].

4.3 Results and Discussion

在文檔中 具多閘極之修正蕭基位障電晶體及氮化鈦奈米晶粒記憶體之研究 (頁 95-123)