There have several topics and suggestions which are worthy for the further research and mention below,
1. For the MOSFETs with surrounding gate structure, in order to further increase the gate controllability, the nano-wire structure is suggested to apply. In this structure, the Si channel is fully surrounded by the gate oxide and gate electrode, which is the extreme case for the achievement of multi-gate structure. Moreover, MSB source/drain junction and high-k gate dielectric layer are both recommended to integrate into this structure for obtaining higher driving capability and better immunity of the short channel effect.
2. In chapter 2 and chapter 3, while applying the MSB S/D junction on the multi-gate SOI devices, since different magnitude of the fringe field from multi-gate electrode, the location of the interface of Ni-silicide/Si channel is a critical parameter to influence the current-voltage performance, current transportation mechanism, and the extracted RT. Therefore, in order to achieve the optimization of MSB junction, it is quiet important to optimize the two step Ni-silicidation process and further well control the concentration and length of source/drain extension regions.
3. In chapter 2 and chapter 3, to observe the simple influence of the MSB junction on the current transportation mechanisms and source-injection resistance, we extract these effects and parameter on the long channel devices with MSB junction but the short channel device, since velocity enhancement effect would be incorporated in the carrier transportation. However, till now, the carrier injection velocity enhancement effect on the short channel device with the MSB junction which is fabricated by the ITS method is still lack. Therefore, it is also worthy to investigate the transportation mechanism and the temperature effect on the nano-scale MSB MOSFETs.
4. In chapter 2 and chapter 3, although we proposed that the temperature effect and the extraction of the bias-dependent source injection resistance are both good indicators to evaluate the efficiency of the MSB junction, the real doping concentration of the MSB junction is still lack. Moreover, each of the spacer length, the dose of ITS, the lateral encroachment length of silicide, and the post-ITS thermal budget would affect the modulation of SB height and thickness.
Hence, it will very helpful to obtain the length and doping concentration of MSB junction. Nevertheless, until now, it is still short of the analysis technology or
equipment to directly measure this ultra-thin and highly doped SDE. Therefore, new technology is required.
5. In chapter 4, the NCM uses the tiny TiN nanorcrystal as the storage node, indicating the main degradation of the memory characteristics is considered as the Coulomb blockage effect. However, there still have some factors to influence the capture and escape of carriers. Different bias conditions and variant structure parameters are required to be considered to affect the property at program, erasing, or read state. Hence, further detail analysis on the carrier behavior at P/E, read states can be achieved by the help of the TCAD simulation.
6. In chapter 4, since too small TiN nanocrystals would degrade the memory performance, some modification would enhance the properties. Therefore, it is suspected that thicker TiN nano-laminated can be used for forming larger TiN nanocrystals, which may help for increasing the P/E speeds, enlarging memory window and enhancing the retention performance. Moreover, the Al2O3 blocking layer is crystallized to induce the degradation of retention property, which is required to be avoided or replaced by the new high-k material with higher crystallization temperature and moderate large energy band gap. Moreover, since the thickness of gate stacks are too thick, the gate electrode does not fully cover the sidewall of Si-fin, especially in the bottom corner, as shown in Fig. 4-2(b).
Hence, by inserting a process to recessing the buried oxide can effective improve and modify the structure of cell. Furthermore, other materials which exhibit higher work function may be used to enhance the retention performance since TiN is a kind of material which has mid-gap work function around 4.5 ~ 4.6 eV.
7. In chapter 5, the supposed switching model is mainly attributed by the formation and rupture of the conducting filaments in the local charge trapping layer. This
hypothesis is based on the RRAM-like switching mechanism. However, although lots amount of specialists are devoted to the research and development of the RRAM, the real cause of the conducting filament is required to further understanding. Therefore, it is waiting for the new method to actual observe the supposed conducting filaments in the NCM.
Publication List
Journal Paper:
1. B.-Y. Tsui and C.-P. Lu, “Method for Extracting Gate-Voltage- Dependent Source Injection Resistance of Modified Schottky Barrier (MSB) MOSFETs,”
IEEE Electron Device Lett., vol. 29, no. 9, pp.1053-1055, 2008.
2. C.-P. Lu, B.-Y. Tsui, C.-K. Luo, C.-H. Lin, P.-J. Tzeng, C.-C. Wang, and M.–J.
Tsai, “Tri-gate TiN Nanocrystal Memory with High-k Blocking Dielectric Layer and High Work Function Gate Electrode,” Electrochemical and Solid-state Letter, vol. 12, H70, 2009.
3. C.-P. Lu, C.-K. Luo, B.-Y. Tsui, C.-H. Lin, P.-J. Tzeng, C.-C. Wang, and M.–J.
Tsai, “Nano-scale Multi-gate TiN Metal Nano-crystal Memory using High-k Blocking Dielectric and the High Work Function Gate Electrode Integrated on SOI Substrate,” Japanese Journal of Applied Physics, vol. 48, 04C059, 2009.
Conference Paper
1. B.-Y. Tsui and C.-P. Lu, “Current Transport Mechanisms of Schottky Barrier and Modified Schottky Barrier MOSFETs,” in Proc. of the 37th European Solid State Device Research Conference, pp.307-310, 2007.
2. C.-P. Lu, B.-Y. Tsui, C.-P. Lin and Y.-J. Lee, “Current Transport Mechanisms of p-channel Schottky Barrier and Modified Schottky Barrier MOSFETs,” in 15th Symposium on Nano Device Technology, 2007.
3. B.-Y. Tsui and C.-P. Lu, and Hsiao-Han Liu, “Bias-Dependent Source Injection Resistance of Modified Schottky Barrier MOSFET,” in Proc. of the 2008 IEEE Silicon Nanoelectronics Workshop, pp. p1_1-2, 2008.
4. C.-P. Lu, C. K. Luo, B. Y. Tsui, C. H. Lin P. J. Tzeng, C. C. Wang, H. Y. Lee, D.
Y. Wu, and M. -J. Tasi, “High Endurance Multi-gate TiN Nanocrystal Memory Devices with High-k Blocking Dielectric and high Work Function Gate Electrode,” in IEEE VLSI-TSA 2008, pp.62-63. 2008
5. C.-P. Lu, C.-K. Luo, B.-Y. Tsui, C.-H. Lin, P.-J. Tzeng, C.-C. Wang, and M.–J.
Tsai, “Multi-Gate Metal Nano-crystal Memories with TiN Nano-crystals, High-k Blocking Dielectric and High Work Function Gate Electrode,” in the 2008 Int.
Conf. on Solid State Devices and Material, pp.824-825, 2008.
6. B.-Y. Tsui, S.-H. Liu, and C.-P. Lu, “Evolution of Schottky Barrier MOSFETs,”
in Proc. of the 16th Symposium on Nano Device Technology, 2009.
7. M. Schimidt, C.-P. Lu, H. D. B. Gottlob, and H. Kurz, “Metal gate electrode for rare earth oxide high-k dielectrics,” in 2009 IEEE International Conf. on Signals, Circuits and Systems (SCS’09), pp.1-5, 2009.
8. B.-Y. Tsui, C.-C. Yen, P.-H. Li, C.-P. Lu, J.-Y. Lai, “Extreme Ultra-Violate Exposure Induced Damages on Non-Volatile Memories,” in the Proc. of the 2010 IEEE Silicon Nanoelectronics Workshop, pp.143-144, 2010.
9. C.-P. Lu, H. D. B. Gottlob, M. Schimidt, and H. Kurz, “Integration of ALD AlN Work Function Tunning Layers,” in IEEE VLSI-TSA 2010, pp.92-93, 2010.