Endurance and Disturbance Performance

Figure 4-11 shows the endurance characteristics of samples A and B with P/E at

± 8 V, 0.1 sec and P/E at ± 12 V, 0.1 sec, respectively. Because the FN tunneling mechanism was used for P/E operations, the injected electrons and holes have a uniform distribution. The distribution mismatch is negligible and neither electrons nor holes would be hard to erase after the P/E cycles [9, 31-32]. Therefore, an invisible shift in the programmed and erased states can be observed and the memory window is kept at about 93% for sample A and at 97% for sample B after 10⁴ P/E cycles. Good endurance performance can also be observed. Figure 4-11(a) and (b) shows the transfer characteristics of sample A and B after the first and 10⁴ P/E cycle operations.

In Fig. 4-11(a), a small deterioration of the subthreshold swing and driving current after 10⁴ P/E cycles means that a small amount of interface state was generated during the P/E cycles. For the multi-gate device structure, charges stored in each nanocrystal may not be identical. For example, for the nanocrystals located near the top corner of the active layer, more charges can be injected owing to a stronger electric field. This phenomenon may also result in the deterioration of the subthreshold swing. In Fig. 4-11(b), no apparent degradation after 10⁴ P/E cycles can be observed.

Gate disturbance occurs when the neighboring cells, which share the same word line, are biased by programming or erasing pulses. Therefore, the gate disturbance characteristics of sample A under four situations for 10³ sec are shown in Fig. 4-12. It can be observed that after stressing at VG= ±10 V for 10³ sec, the device in the erase state has a negligible V_TH shift, which is due to the decreased electric field in the multi-gate structure on the SOI wafer. In the multi-gate structure, the body, source and drain terminal potentials are all floating. Therefore, we suspect that the electric field between the trapping nodes and the Si body is reduced to suppress unwanted

carrier migration or charge loss. However, after VG= ±10 V for 10³ s stressing in the programmed state, the device with an erased bias has a more pronounced V_TH shift than that with a programmed bias because the repulsive force and the floating body can block the extra injected electrons in the programmed state but some stored electrons are de-trapped by higher negative erased voltage. Note these disturbance properties both saturate after 10-20 sec and are not critical issue. Figure 4-13 shows the read disturbance of sample A in the erase state for 10³ sec stressing bias. A very small variation can be observed, indicating insignificant carrier migrations, injection or de-trapping during read operations.

4.4 Conclusions

As the NAND technology continually scales down, the combination of discrete traps storage and MuGFETs structure is one of the most potential candidates for the future application. In this chapter, we successfully combine multi-gate as the noplanar cell structure and the metal nanocrystal as the storage node together. An n-channel tri-gate metal nanocrystal memory using TiN nanocrystals, a high-k blocking dielectric layer and a p⁺ poly-Si gate was fabricated. The effects of charge trapping layer thickness and post deposition annealing time have been investigated. It is observed that the memory window is determined by the size of nanocrystals.

Although a longer annealing time could help the growth of TiN nanocrystals and slightly enhance the memory window, an adequate mass of the source material is the key factor for forming larger TiN nanocrystals and obtaining larger memory window.

The device with thicker TiN nano-laminates (0.7 nm) has much larger memory window, 5.2 V than the devices with thinner TiN nano-laminates (0.5 nm). Moreover,

phenomenon of the turn-down memory window as FN bias increases is observed and explained by the back-side injection effect.

In addition, the charge loss rates of samples with different nanocrystal sizes are similar when the devices are programmed and erased at the maximum initial memory window. Retention performance was mainly affected by the coulomb repulsive force but not by the quantum confinement effect. This observation implies that the quantum confinement effect in the metal nanocrystal is not as critical as that in the semiconductor nanocrystal. Furthermore, in these TiN nanocrystal memories, holes can inject into nanocrystals to shift the threshold voltage more negative than fresh threshold voltage during erase operation. Hence, by selecting the suitable initial P/E states, better retention performance would achieve. Finally, the FN tunneling mechanism has a uniform injection profile to avoid unwanted charge migration, and the multi-gate structure on an SOI wafer with a floating body can reduce inner electric field to suppress trapped charge migration. Therefore, good endurance and disturbance performance can be obtained in these nano scale multi-gate nanocrystal memories.

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Table 4-1: Gate stacks conditions of sample A-D.

Tunneling Layer

Trapping Layer

Blocking Layer Sample

SiO2 (nm)

TiN/ Al2O3 x 7 periods

(nm/nm)

Al2O3 (nm)

PDA @ 900

^o

C

(sec)

A 3.6 0.7 /1 20 10

B 3.6 0.5 /1 20 40

C 3.6 0.5 /1 20 10

D 3.6 0.5 /1 15 10

Fig. 4-1 Process flow of n-channel MuGFET TiN nanocrystal NVM on SOI substrate.

(a)

(b)

(c)

L

^G

= 80 n m L

^G

= 80 n m

Fig. 4-2(a) High-resolution X-TEM images of the fabricated MuGFET TiN nanocrystal memory with gate length of 80 nm.

W

_f

=50nm

T

_Si

=40nm Poly Si Gate

Si

Fig. 4-2(b) High-resolution X-TEM images of the fabricated MuGFET TiN nanocrystal memory with fin width of 50 nm.

5 nm Si

(a)

T _OX = 3.6 nm

5 nm Si

(a)

5 nm Si

5 nm Si

(a)

T _OX = 3.6 nm

Fig. 4-3(a) High-resolution X-TEM images of sample A. Nanocrystals with diameter around 3 nm were embedded by Al2O3.

T _OX = 3.6 nm

5 nm Si

(b)

T _OX = 3.6 nm

5 nm Si

(b)

Fig. 4-3(b) High-resolution X-TEM images of sample B. Nanocrystals with diameter around 1-2 nm were embedded by Al O .

-3 -2 -1 0 1 2 3 4 5 6 7 10

^-13

10

^-11

10

^-9

10

^-7

10

^-5

10

^-3

Sample A

I

D

(A )

V

_G

(V)

Fresh P/E at

±

± ±

± 6 V

± ± ±

± 8 V

±

± ±

± 10 V

∆

∆

∆

∆ V~5.2V

Fig. 4-4 Transfer characteristics of sample A after various P/E bias for 0.1 sec.

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

6 8 10 12 14 0

1 2 3 4 5

M e m or y W indow (V )

|FN Bias| (V)

sample A sample B sample C sample D

Fig. 4-6 The memory window of sample A-D after various P/E bias for 0.1 sec. The P/E operations utilized Fowler-Nordheim tunneling, and both source and drain terminals were grounded during the biasing pulse.

10^-3 10^-2 10^-1 10⁰

Fig. 4-7(b) Erasing speeds of sample A with various pulse biases and pulse widths.

10

⁰

10

¹

10

²

10

³

10

⁴

-1

0 1 2 3 4 5

V

TH

( V )

Retention Time (s) Solid: 25

^O

C

Open: 85

^O

C

Star: sample A (full window) Square: sample A

Triangle: sample B

Fig. 4-8 Retention characteristics of trigate TiN nanocrystal memory devices of samples A-B at room temperature (T = 25 °C) and high temperature (T = 85 °C).

10

^-2

10

^-1

10

⁰

10

¹

10

²

10

³

10

⁴

-0.5

0.0 0.5 1.0 1.5 2.0

2.5 Prog./Erase State:

With Moderate P/E Bias

-20%

V

th

( V )

Time (sec.)

Prog./Erase State:

With Stronger Erasing Bias

-38%

Sample B Fresh

Vth

Fig. 4-9 Retention properties of sample C in two different P/E conditions but similar initial memory window.

Fig. 4-10 Simple energy band diagrams in the retention condition after (a) moderate erasing bias or (b) stronger erasing bias.

.

Fig. 4-11 Endurance characteristics of samples A and B. The P/E bias conditions are ±9 V, 0.1 sec for sample A and ±12 V, 0.1 sec for sample B.

10

^-1

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

-2

-1 0 1 2 3 4 5 6

~1.35V

~1.36V

~3.85V

V

TH

( V )

P/E Cycles

Sample A Sample B

~4.12V

-3 -2 -1 0 1 2 3 4 5

Fig. 4-12(a) Transfer characteristics after the first and the 10^4th P/E cycle operations of sample A.

Fig. 4-12(b) Transfer characteristics after the first and the 10^4th P/E cycle operations of sample B.

10

⁰

10

¹

10

²

10

³

-1

0 1 2 3

V

D

& V

S

floating

V

GS

= 10V in Prog. State V

GS

= -10V in Prog. State V

GS

= 10V in Erase. State V

GS

= -10V in Erase. State

Gate Disturb Time (s) Sample A

V

TH

( V )

Fig. 4-13 Gate disturbance characteristics of sample A in four different states.

10

⁰

10

¹

10

²

10

³

-0.2

-0.1 0.0 0.1 0.2

Read Disturb Time (s) V

TH

S h if t ( V )

Stress at

V

_GS

=2.4V, V

_DS

=1V V

_GS

=1.2V, V

_DS

=1V Sample A

Fig. 4-14 Read disturbance of sample A in erase state for 10³ sec stressing bias.

Chapter 5

Abnormal Current Modulation in the Turn-off State of 1-T Nano-Scale Multi-Gate Nanocrystal

Memory

5.1 Introduction

The international technology roadmap for semiconductors (ITRS) recently forecasted that the scaling of conventional floating gate non-volatile memory is becoming increasingly difficult. For floating gate (FG) flash memories, no scalability of tunnel dielectric or inter-poly dielectric in the 22 nm node was predicted [1].

Nanocrystal memories, which utilize a thinner tunneling layer to improve memory characteristics without degrading retention performance because each nanocrystal is theoretically isolated by the surrounding dielectric is one possible replacement for the floating gate memories [2-4]. Meanwhile, several non-volatile memory architectures, such as magnetoresistive memories (MRAM) [5], phase change memories (PCM) [6], and resistance random access memories (RRAM) [7-13] have been widely investigated with a view to their future application in the non-volatile memory. On the other hand, to increase data storage density, both multi-bit operation and hybrid memory scheme are both possible strategies for the further scaling. It is well known that the flash memory can be manipulated by the injections of channel hot electrons

(CHE) and band-to-band hot holes (BTBHH) for programming and erasing, respectively. Moreover, for SONOS-type memory, since discrete charges are stored in the local nitride region near to the drain-side, dual-bit operation is proposed by utilizing the injections of CHE and BTBHH with selectable bit at read status [14].

Furthermore, dual bit operation is also presented by sensing the off-state gate induced drain leakage (GIDL) current and the on-state current in a SONOS-type memory [15].

In addition, BTBHHs are utilized to passivate the trapped electrons and suppress the off-state GIDL current to avoid mis-idenfication [16]. In the previous chapter, by using the Fowler-Nordheim (FN) tunneling for P/E operations, the memory characteristics in the turn-on state of a one-transistor (1-T) nano-scale silicon-Al2O3 -metal TiN nanocrystal-SiO₂-silicon (SAMOS)-type multi-gate nanocrystal memory have been investigated. The charge trapping layer is composed of many TiN nanocrystals and the surrounding Al₂O₃ dielectric. In this chapter, this nanocrystal memory is attempted to operate by the injections of CHE and BTBHH first. However, no significant effect in the on-state is observed but an abnormal current modulation in the off-state at reverse read status is exhibited after biasing at the status of BTBHH.

Moreover, this current modulation can be recovered by the bias at the status of CHE.

This resistively switchable behavior and their off-state current in such a device are observed with excellent retention performance. Detail analyses indicate the conductance of the charge trapping layer close to drain-side would induce the current modulation. Possible mechanism will be proposed and discussed. Furthermore, this switchable behavior can be operated individually without affecting the memory state in the on-state. Therefore, possible dual-bit operation is demonstrated. However, some critical issues let this dual-bit operation is hard for practical application.

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