In this dissertation, we mainly focus on the some possible solutions for the multi-gate MOSFET and multi-multi-gate flash memory. In the first part, the influence by the existed Schottky barriers on a multi-gate MOSFET and a novel extraction method of the series resistance in MSB S/D MOSFET are also described. In the second part, a nano-scale multi-gate nanocrystal memory has been demonstrated as a promising candidate for the NAND flash memory application.
In the first chapter of this dissertation, some overviews of the CMOS revolution and its challenges will be mentioned. Non-planar device structure, such as multi-gate structure, is highly considered for the future application on the logic CMOS transistors and the Flash memory. The advantage and the shortcoming for using multi-gate are also described. For CMOS devices, multi-multi-gate structure and metal S/D are forecasted for the further scaling. Modified Schottky barrier S/D junction is one possible solution for the future S/D engineering. For flash memory, multi-gate
structure is also a candidate. Moreover, the possible enhancement of the charge storage element and its revolution are also reviewed.
In chapter 2, current transport mechanisms of SB S/D MOSFETs and MSB S/D MOSFETs are investigated by measuring the temperature effect on current-voltage characteristics. The current transport mechanism varied while different gate voltage was biased. Moreover, the SB height would impact the transport mechanism largely in different gate bias conditions.
In chapter 3, we provide a novel method for extracting gate voltage dependent source injection resistance of MSB MOSFETs. The relationship between the injection resistance and the gate bias will be discussed. Furthermore, this method provides a good indicator to evaluate the efficiency of the MSB junction directly.
In chapter 4, the fabrication and the electrical characteristics of a nano-scale n-channel tri-gate TiN nanocrystal non-volatile memory has been demonstrated. The Al2O3 high-k blocking layer and the P+ high work function gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing the TiN/Al2O3 nano-laminates which were deposited by an atomic layer deposition system. Moreover, the charge-trapping layer has engineered with different TiN wetting layer thickness, post deposition annealing time, and blocking oxide thickness. The size of the nanocrystal affects the performance largely. Moreover, the memory characteristics and the reliability performance of these samples have been demonstrated.
In chapter 5, we demonstrate an interesting resistive switching phenomenon in the turn-off state in the naon-scale multi-gate TiN nanocrystal memory. This electric-bias-induced reproducible change of reverse read current are observed after pulsing at the conditions of CHE and BTBHH, normally utilizing for the NOR flash operations.
This abnormal leakage current will be investigated and possible mechanism will be discussed.
Finally, in chapter 6, we will give some important conclusions. Moreover, some further works which are worthy for further study will be suggested.
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(a)
Si Substrate
Gate
Source Drain
(b)
Si Substrate
Gate
Buried Oxide
Source Drain
Channel
Fig. 1-1 Schematic cross-section views of (a) planar MOSFET, and (b) planar UTB SOI FET.
(a)
(b)
Fig. 1-2 Schematic structures of the FinFETs on SOI substrate, (a) double-gate FinFETs, and (b) tri-gate FinFETs.
Buried Oxide Si
Gate
Buried Oxide Si
Gate
(a)
Si Substrate
Tunneling Oxide Control Gate
Source Drain
Floating Gate Blocking Oxide
(b)
Si Substrate
Tunneling Oxide Control Gate
Source Drain
Nitride Blocking Oxide ONO
stack {
(c)
Si Substrate
Tunneling Oxide Control Gate
Source Drain
Blocking Oxide
nanocrystals
Fig. 1-3 Basic structure of (a) FG flash memory device, (b) SONOS flash memory device, and (c) nanocrystal flash memory device.
Chapter 2
Current Transportation Mechanisms of Schottky Barrier (SB) MOSFETs and Modified
Schottky Barrier (MSB) MOSFETs
2.1 Introduction
From the prediction of ITRS Roadmap, it mentions that the metal gate electrode, high dielectric constant gate dielectric layer, and metal source/drain would be utilized to enhance the device performance and promote further scaling. The metal source/drain is normally achieved by using metal silicide which is easily formed by the thermal reaction of the metal and the Si layers at source/drain regions and thus the Schottky barriers (SB) were created at the interface between silicide and Si-channel.
Hence, metal source/drain MOSFETs are usually called SB source/drain MOSFETs.
Recently, SB source/drain MOSFETs have been proposed for future nano-scale devices because of easy processing, low thermal budget, small external resistance of source/drain, good drain-induced barrier lowing and better short channel effect. [1-4].
However, the SB MOSFETs still have some drawbacks. The first drawback of the SB MOSFETs is the smaller on-state driving current (Ion) than that of the conventional pn junction MOSFETs due to the existed SB between the silicide and the inverted channel. The existed SB not only affects the driving capability but also degrades the