Chapter 1: Introduction
1.3 Dissertation Organization
The organization of this dissertation is briefly described below. Chapter 2 studies the basic characteristics and reliability discussion of strain effect by CESL. The fast trap behavior is discussed under strain effect. Chapter3 discusses the electron trapping and de-trapping behavior under positive bias temperature instability (PBTI) and dynamic PBTI stress. The electron trapping/de-trapping model and the meaning of the parameters by fitting are discussed. The fast trap in nMOSFETs is discussed under various temperatures. Chapter 4 discusses the hole trapping and de-trapping behavior under constant voltage stress (CVS) and recovery. The hole trapping/de-trapping model and the meaning of the parameters by fitting are discussed. The basic characteristics and negative bias temperature instability discussion of fluorine effect are discussed. The fast trap in pMOSFETs is discussed under various temperatures and fluorine effect.
References
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Chan, D. L. Kwong, “Negative U Traps in HfO2 Gate Dielectrics and Frequency Dependence of Dynamic BTI in MOSFETs,” IEDM 04, pp. 733-736
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Appl. Phys. 79 (8), 15 April 1996
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[15] Ronald E. Paulsen, and Marvin H. White, “Theory and application of charge pumping for the characterizationof Si-SiO2 interface and near-interface oxide traps,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 7, JULY 1994
(a) High-Performance Logic: Jg,limit versus simulated gate leakage current density for SiON gate dielectric. (b) LSTP: Jg,lim
Fig.1-1
it versus simulated gate leakage current density for SiON gate dielectric. [1]
Table 1-1 terial and electrical properties of various selected high-k gate dielectrics [2].
Summarized ma
Fig 1-2 Bandgap and band alignment of various high-k gate dielectrics with respect to silicon. The dashed line represents 1 eV above/below the conduction/valence bands, which indicate the minimum barrier height to suppress the gate leakage current [3].
Chapter 2
Contact etchant stopping layer in nMOSFETs with HfO
2/SiO
2High-k Gate Stacks
2.1 Introduction
As conventional SiO2-based ultrathin oxides are scaling down, the rapidly-increasing tunneling gate leakage current has been a major challenge. In order to retard the downscaling of Si based CMOS device, mobility enhancement is one of the most useful methods. Mobility enhancement techniques represents an effective and essential way to reduce Vdd and resulting power consumption without losing the circuit performance, relieving the burden of gate dielectric scaling. There are many methods of mobility enhancement: a) channel-strain engineering, b) substrate and channel orientations ((100) or (110)), and c) new channel materials (SiGe, Ge and III-V). The channel-strain engineering comprises biaxial and uniaxial strain (tensile or compressive). The biaxial tensile strain uses the technique of the so-called SiGe-relaxed buffer or virtual substrate [1]-[3]. Recently, this technique has also been successfully implemented on SOI wafers [4]. In contrast, it is difficult to fabricate a biaxial compressive strain in silicon; it’s very beneficial effect to holes has been demonstrated with SiGe channels in [5]. The uniaxial tensile strain in the channel can be produced with SiC epitaxial source–drain regions and with the contact-etch-stop-layer (CESL) nitride layer. The uniaxial compressive strain can be obtained with SiGe epitaxial source–drain regions [6], with a SiGe stressor located under the channel region [7], and with CESL. The contact-etch stop layer nitride layer can induce both tensile strain for nMOSFETs and compressive strain for pMOSFETs, so that dual stress liner with SiN capping is one of the most popular
techniques of mobility enhancement.
In this chapter, the high-k nMOSFETs with the contact-etch-stop-layers that induce tensile strain in the channel are introduced. The strain effect can be realized by basic characteristics in section 2.3. In section 2.4, the difference of the charge trapping between the stained and unstrained devices will be studied during the positive bias stress. Finally, the transient charge carriers in stain effect will be analyzed by pulsed I-V techniques in section 2.5.
2.2 Device Fabrication
nMOSFET devices with the poly-Si/HfO2/SiON high-k gate stacks were fabricated using the standard CMOS process technology. The interfacial oxide (～1.0 nm) was formed by oxide rapid thermal anneal (RTA) at 800℃ in N2O ambient with 30s, followed by the deposition of the HfO2 (～3.0 nm) high-k gate dielectric using atomic layer deposition (ALD) technique. The 200 nm poly-Si was deposited by low pressure chemical vapor deposition (LPCVD). After gate definition, spacer formation, and S/D implantation, the tensile strain induced by SiN capping layer was deposited by plasma chemical vapor deposition (PECVD). The capping nitride layers were divided into three kinds of thickness such as 200 nm, 300 nm and without SiN. The equivalent oxide thickness of above mentioned high-k gate stack was extracted to be 2.0～2.5 nm by using C-V measurement. The structure of the devices are shown in Fig. 2-1
2.3 Basic Characteristic
Fig. 2-2 (a) (b) show Id-Vg and Gm-Vg curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers. From
Id-Vg curves, as the thickness of capping nitride layer was thicker, drain current would be larger. In Gm-Vg curve, the same phenomenon would also be occurred. Turn-on current which varies with gate voltage also represented larger in thicker nitride layer in Fig. 2-3. The reason of improvement of the stained devices is mobility enhancement as a result of electron effective mass. The channel stressed by capping nitride layer would induce the electrons of 2-fold valley with lighter transport effective mass to increase. As the inverted electrons with lighter effective mass increase, the mobility of the strained devices will enhance. Fig. 2-4 shows Icp-Vbase curves by charge pumping method of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers. From Icpmax of Icp-Vbase curves, the interface trap density could be obtained. Moreover, the interface trap density of the strained devices was smaller than that of the unstrained device because of hydrogen passivation by capping nitride layers of PECVD. From Fig. 2-5, the Gm,max enhancement could decrease with gate length increasing because of CESL belonged to local strain [8].
2.4 Positive Bias Temperature Instability (PBTI) stress
Threshold voltage instability induced by charge trapping has been recognized as one of the critical reliability issues in high-k gate dielectrics, especially for nMOSFETs under substrate electron injection conditions [9]. Fig. 2-6 shows threshold voltage shift of nMOSFETs as a function of the stress time in difference thickness of capping nitride layers. The Vt shift of strained devices showed more serious than that of unstrained devices. Moreover, thicker capping nitride layers would increase more Vt shift. The physical mechanism or the modeling of the fitting lines in Fig. 2-6 will be discussed in chapter 3. In order to confirm the reason of the more Vt shift of the strained devices, the comparing of trapped energy level by Frenkel-Poole (F-P) fitting and the barrier height
for electrons from Si substrate by Fowler-Nordheim (F-N) tunneling fitting between the unstrained and the strained devices should be extracted. Fig. 2-7 shows ln(JG/Eeff) as a function of Eeff1/2
in the (a) unstrained and (b) strained devices. The curves of the two plots followed Frenkel–Poole emission as indicated by a good linear fit to the experimental data. Then, the trapped energy levels could be obtained from the y-axis intercept (Eq. (2.1)). It could be found that almost the same trapped energy levels of the unstrained and strained devices. Fig. 2-8 shows the ln(JG/Eeff) as a function of 1/Eeff in unstrained and strained devices. The slops of the lines fit to the experiment data could be obtained the barrier height (Eq. (2.2)). The similar slope represented the similar barrier height in unstrained and strained devices. Thus, the trapped energy level and the barrier height for electrons from Si substrate are not change by strain. It can be assumed that the more Vt with increasing capping nitride layer is due to the generated bulk traps of HfO2 by stain. Moreover, the thicker capping nitride layer represents the more generated bulk traps of HfO2.
Frenkel-Poole emission:
2
Fig. 2-9 shows the drain current degradation of nMOSFETs as a function of the stress/recovery time with a fixed stress/recovery voltage +2.0V/0V in difference thickness of capping nitride layers. From every single line in Fig. 2-9, the charge trapping and de-trapping behavior changed since the trapped charge had not been completely removed at weak recovery voltages during previous recovery cycles.
Moreover, the trapped electrons and the residual electrons during stress/recovery time of strained device would induce more drain current degradation than that of unstrained device.
2.5 Pulsed I-V Techniques and Fast Trap Behaviors
Fig. 2-10 shows Id-Vd curves of (a) unstrained (b) SiN = 200nm (c) SiN = 300nm devices by two measurement methods: DC ramp and pulsed I-V. The measurement time of the conventional DC ramp measurement is about several milliseconds to seconds.
The pulse width of the pulsed I-V measurement we used is 100ns and raising/falling time is 20ns. Thus, the different of Id,sat by two methods could be the charge loss with the capture time ranging from 100ns to several milliseconds. The charge loss decreased in thinner capping nitride layer device and increased in thicker capping nitride layer device. The behavior of these fast traps would be a little different from that of the slow traps by PBTI measurement. It can be assumed that the hydrogen passivation is dominant in thinner capping nitride layer device and the trap generation is dominant as the capping nitride layer is thicker. Fig. 2-11 shows Id,sat as a function of stress time ranging several nanoseconds to100ns by single pulse measurement. The detected traps would be more close to the interface of Si/SiON. Thus, the result are almost the same with the interface state by charge pumping measurement and the reason of the result can be also assumed the hydrogen passivation.
2.6 Summary
The contact-etch-stop-layer (CESL) is one of mobility enhancement methods and it can induce tensile strain to improve mobility for nMOSFETs. In our data, the strained devices could improve the electrical characteristics of NMOS, but they would induce more threshold voltage shift in high-k material. By F-P and F-N tunneling fitting, the trapped energy levels and the barrier heights of stained and unstrained devices are almost the same. Thus, we conclude that the strain effect induces bulk traps generated in HfO2. Form the transient effect by pulsed I-V, the competition of hydrogen passivation and trap generated by strain can be found. The charge loss detected by single pulsed ranging several nanoseconds of strained and unstrained devices represents the interface states improvement due to hydrogen passivation.
References
[1] J. Welser, J. L. Hoyt, and J. F. Gibbons, “Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors," IEEE Electron Device Lett., vol. 15, no. 3, pp. 100–102, Mar. 1994.
[2] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained silicon MOSFET technology,” in IEDM Tech. Dig., Dec.
2002, pp. 23–26.
[3] M. Jurczak, T. Skotnicki, G. Ricci, Y. Campidelli, C. Hernandez, and D. Bensahel,
“Study on enhanced performance in NMOSFETs on strained silicon,” in Proc.
ESSDERC, 1999, pp. 304–307.
[4] C. Mazure, “Advanced substrate engineering for the nanotechnology era,” in Proc.
Int. Symp. VLSI Technol., Syst., Appl., 2006, pp. 78–79.
[5] M. L. Lee and E. A. Fitzgerald, “Optimized strained Si/strained Ge dualchannel heterostructures for high mobility P-and N-MOSFETs,” in IEDM Tech. Dig., Dec.
2003, pp. 429–432.
[6] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K.
Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M.
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Orain, F. Leverd, D. Delille, B. Duriez, A. Souifi, D. Dutartre, and T. Skotnicki,
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[8] Thomas Skotnicki, Claire Fenouillet-Beranger, Claire Gallon, Frederic Boeuf, Stephane Monfray, Fabrice Payet, Arnaud Pouydebasque, Melanie Szczap, Alexis
Farcy, Franck Arnaud, Sylvain Clerc, Augustin Cathignol, Jean-Pierre Schoellkopf, Ernesto Perea, Richard Ferrant, and Hervé Mingam, “Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1, JANUARY 2008.
[9] K. Onishi et al. “Bias-temperature instabilities of polysilicon gate HfO2 MOSFETs,”
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 6, JUNE 2003.
Fig. 2-1 The structure of the devices in strained and unstrained samples.
HfO2 high-k gate stack in different capping nitride layers.
VG - VT = 1.0 V
Fig. 2-3 Id-Vd curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers.
HfO2
Fig. 2-4 Icp-Vbase curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers.
HfO2
Gate Length (μm)
1 1 0
Gm
max0 200 400 600 800 1000 1200
w/o SiN SiN = 200nm SiN = 300nm
Fig. 2-5 Gm,max-Lgate curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers.
HfO2
VG-VT = 1.0V W/L = 10/0.7μm
Stress Time (sec)
10
-110
010
110
210
310
4Δ V
T(m V ) 50
10 100
w/o SiN γ=0.36 SiN = 200nm γ=0.38 SiN = 300nm γ=0.38
Fig. 2-6 Threshold voltage shift of nMOSFETs as a function of the stress time in difference thickness of capping nitride layers.
HfO2 w/o SiN
E
eff1/2(V/cm)
1/22200 2400 2600 2800 3000 3200 3400
ln (J /E
eff)
2200 2400 2600 2800 3000 3200 3400
ln(J/E eff)
The trapped energy levels can be obtained by y-axis intercept.
HfO2
1/E (cm/MV)
0.055 0.060 0.065 0.070 0.075 0.080 0.085
ln (J /E )
-37 -36 -35 -34 -33 -32 -31
w/o SiN SiN = 200nm SiN = 300nm fit curve
Fig. 2-8 ln(JG/Eeff) as a function of Eeff1/2 in the unstrained and strained devices. The barrier heights can be obtained by the slopes.
HfO2
W/L = 10/0.4μm
VG - VT = 1.0V ; VR = 0V
Stress/Recovery Time (sec)
0 2000 4000 6000 8000 10000
I
dD e gr e da ti on ( % )
0 20 40
60
w/o SiNSiN = 300nmFig. 2-9 The drain current degradation of nMOSFETs as a function of the stress/recovery time with a fixed stress/recovery voltage +2.0V/0V in difference thickness of capping nitride layers.
Fig. 2-10 Id-Vd curves of (a) unstrained (b) SiN = 200nm (c) SiN = 300nm devices by two measurement methods: DC ramp and pulsed I-V and (d) the distribution of drain current degradation under different conditions.
HfO2
W/L = 10/0.6μm
Stress Time (ns)
20 30 40 50 60 70 80 90
I
d,satD eg rad at io n (% )
0 1 2 3 4
w/o SiN SiN = 200nm SiN = 300nm
Fig. 2-11 Id,sat as a function of stress time ranging several nanoseconds to 100ns by single pulse measurement.
Chapter 3
Bias Temperature Instability in nMOSFETs with HfO
2/SiON High-k Gate Stacks
3.1 Introduction
Threshold voltage instability in Hf-based high-k gate dielectrics has been recognized as one of the most critical reliability issues that need to be solved urgently, especially for the nMOSFETs under substrate electron injection conditions (positive bias stress) [1]. The electrons in channel are injected into the pre-existing bulk traps of the HfO2
high-k gate dielectric by tunneling through the thin interfacial oxide. The pre-existing traps of the HfO2 high-k gate dielectric are positioned above the Si conduction band edge in energy and in the HfO2 bulk layer in space. These pre-existing bulk traps are distributed in a wide range of space and energy [2], thus making the charge trapping model different from that of conventional SiO2 or SiON. Furthermore, the high-k dielectrics are reversible by charge trapping and de-trapping. Thus, it is found that the trapped charge carriers could recover to the pre-stress condition after prolonged recovery time. According to results of the threshold voltage shift and the drain current degradation with stress/recovery time, the model could be built to fit the data with reasonable physical mechanism. However, since the charge carriers could be trapped/de-trapped quickly and easily by applying a forward/reverse bias voltage, the degradation may be underestimated due to the switching and measuring delays in the stress/measure cycles [3]. These so-called fast traps would be detected by transient measurement solving the underestimate of charge trapping in high-k gate dielectrics.
In this chapter, the charge trapping behavior under various voltages, temperature and
geometrics will be studied in detail to comprehend the physical model in section 3.3. In section 3.4, the charge de-trapping behavior under various stress voltages and recovery voltages will be investigated to build the physical model according to the charge trapping model. Finally, the transient charge trapping behavior will be analyzed by pulsed I-V measurement.
3.2 Device Fabrication
nMOSFET devices with the poly-Si/HfO2/SiON high-k gate stacks were fabricated using the conventional CMOS process technology. The interfacial oxide (～1.0 nm) was formed by oxide rapid thermal anneal (RTA) at 800℃ in N2O ambient with 30s, followed by the deposition of the HfO2 (～3.0 nm) high-k gate dielectric using atomic layer deposition (ALD) technique. The 200 nm poly-Si was deposited by low pressure chemical vapor deposition (LPCVD). After gate definition, spacer formation, and S/D implantation, the capping layer was deposited by plasma chemical vapor deposition (PECVD). The equivalent oxide thickness of above mentioned high-k gate stack was extracted to be 2.0～2.5 nm by using C-V measurement.
3.3 Electron trapping behaviors during stress in high-k gate dielectric Fig. 3-1 shows (a) the gate leakage current density and (b) the subthreshold slop as a function of stress time for nMOSFETs under static stress at various gate bias voltages.
The gate leakage current density increases with stress voltage. The symbols in Fig. 3-1 (a) are the measurement data and the solid lines are power law fits to the results. Since Jg is observed to decrease with stress time, it implies that no new traps in the bulk are created during stressing. The subthreshold slope remains constant with stress time
regardless of stress voltage. Since interfacial trap density can be detected by subthreshold slope, it is concluded that no new interfacial traps are created during stressing. Therefore, creation of additional new traps during stressing is assumed to be negligible. Thus, it implies that the electron trapping and de-trapping behaviors are occurred in the pre-existing traps of the HfO2 gate dielectric.
Fig. 3-2 shows the threshold voltage shift as a function of stress time for nMOSFETs under static stress at various gate bias voltages. The threshold voltage shift in this study is determined from the static Id-Vg characteristics. The symbols in Fig.3-2 are measurement data and the solid lines are the fits to the results using the physical model
Fig. 3-2 shows the threshold voltage shift as a function of stress time for nMOSFETs under static stress at various gate bias voltages. The threshold voltage shift in this study is determined from the static Id-Vg characteristics. The symbols in Fig.3-2 are measurement data and the solid lines are the fits to the results using the physical model