Fast Electron Trapping Behavior in High-k Gate Dielectric

Fig. 3-18 shows Id-Vd curves under (a) 25℃ (b) 50℃ (c) 75℃ (d) 125℃ by two measurement methods: DC ramp and pulsed I-V. The measurement time of the conventional DC ramp measurement is about several milliseconds to seconds. The pulse width of the pulsed I-V measurement we used is 100ns and raising/falling time is 20ns.

Thus, the different of Id,sat by two methods could be the charge loss with the capture time ranging from 100ns to several milliseconds. In Fig. 3-18 (a), the charge loss would be more serious with increasing gate voltage. Moreover, the charge loss would be retarded with increasing the measurement temperature because of the de-trapping mechanism dominant. These results are consistent with the results of the slow traps.

3.6 Summary

In this chapter, electron trapping and de-trapping characteristics are investigated in the pre-existing traps of the HfO2 high-k gate dielectric. During the PBTI stress, Vt shift and Id,sat degradation continue to grow and eventually become saturated, whereas the gate leakage decays with stress time and the subthreshold swing remains unchanged.

According to the fitting results with the model proposed by Zafar et al., the total density of traps is not a fixed value but dependent on stress voltage and the distribution factor of capture time is dependent on not only high-k materials but also stress voltages.

Moreover, the fitting results can build the distribution of the trapped charge density with capture time. The temperature effect and the geometric effect under stressing are discussed. Then, the recovery model can be built base on the charge trapping model.

Our recovery model can well fit the measurement data. According to the fitting results with our model, the maximum density of de-trapped electrons is not a fixed value but dependent on stress voltage and the distribution factor of emission time is dependent on stress voltages. Moreover, the fitting results can also build the distribution of the de-trapped charge density with emission time. The fast traps can be detected by pulsed I-V measurement and the results are similar to those of slow traps.

References

[1] K. Onishi et al. “Bias-temperature instabilities of polysilicon gate HfO2 MOSFETs,”

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 6, JUNE 2003.

[2] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G.

Groeseneken, Senior Member, U. Schwalke, “Characterization of the Vt-instability un SiO2 HFO2 gate dielectrics,” International Reliability Physics Symposium, Dallas, Texas, 2003

[3] C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, F.

Martinl, “Characterization and modeling of hysteresis phenomena in high K dielectrics,” IEDM 04-737

[4] T. H. Ning, “High-Field capture of electrons by Coulomb-attractive centers in silicon dioxide,”J. Appl. Phys. 49, 5997 (1978).

[5] Sriram Kalpat, Hsing-Huang Tseng, Michael Ramon, Mohamed Moosa, Daniel Tekleab, Philip J. Tobin, David C. Gilmer, Rama I. Hegde, C. Capasso, Clarence Tracy, and Bruce E. White, Jr., “BTI characteristics and mechanisms of metal gated HfO2 films with enhanced interface/bulk process treatments,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO.

1, MARCH 2005.

[6] A. Plonka, “Dispersive Kinetics in Condensed Phases,” Springer-Verlag, Berlin Heidelberg, (1986)

stress voltage Parameters

VG = 1.5V VG = 2.0V VG = 2.5V VG = 3.0V

∆Vmax (V) 0.037 0.075 0.163 0.296

τc0 (sec) 297.5 159.9 12.8 5.5

γ 0.41 0.36 0.28 0.24

Table 3-1 The three parameters, ΔVmax, τc0, and γ, extracted by fitting under various stress voltages.

HfO2

Fig. 3-1 (a) the gate leakage current density and (b) the subthreshold slop as a function of stress time for nMOSFETs under static stress at various gate bias voltages.

HfO₂

W/L = 10/0.7μm

Stress Time (sec)

10^-1 10⁰ 10¹ 10² 10³ 10⁴ ΔV T (mV)

1 10 100 1000

V_G = 1.5V γ=0.41 V_G = 2.0V γ=0.36 V_G = 2.5V γ=0.28 V_G = 3.0V γ=0.24

fit curve

Fig. 3-2 The threshold voltage shift as a function of stress time for nMOSFETs under static stress at various gate bias voltages.

T = 25C HfO₂

Stress Voltage (V)

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

τ c0 (s)

10

⁰

10

¹

10

²

10

³

Fig. 3-3 The characteristic capture time constant under various gate bias voltages.

log(τ

_c

/τ

_c0

)

Fig. 3-4 The trapped charge density distribution versus capture time under different stress voltages.

Fig. 3-4 The trapped charge density distribution versus capture time under different stress voltages.

HfO₂

W/L = 10/0.7μm early traps : 0~1s later traps : 1~1000s

Gate Voltage

1.5V 2.0V 2.5V 3.0V

ΔV T,early / ΔV T,later (%)

Fig. 3-5 The ratio of early traps to fast traps under various gate bias voltages.

Fig. 3-5 The ratio of early traps to fast traps under various gate bias voltages.

HfO₂

W/L = 10/0.4μm

Stress Time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

Δ I

Dsat

/I

D0sat

( % ) De g ra d a ti o n 10

⁰

10

¹

10

²

V_G = 1.5V γ=0.47 V_G = 2.0V γ=0.43 V_G = 2.2V γ=0.40 V_G = 2.5V γ=0.32 fit curve

Fig. 3-6 The drain current degradation as a function of stress time for nMOSFETs under static stress at various gate bias voltages.

HfAlO_x

W/L = 10/0.8μm

Stress Time (sec)

10

^-1

10

⁰

10

¹

10

²

10

³

10

⁴

V T (V)

0.01 0.1

V_G = 1.5V γ=0.29 V_G = 2.0V γ=0.23 V_G = 2.5V γ=0.22 fit curve

T = 25C HfAlO_x

Stress Voltage (V)

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 τ c0 (s)

500

100 1000

Fig. 3-7 (a) The threshold voltage shift as a function of stress time for HfAlO high-k gate dielectric under static stress at various gate bias voltages. (b) The characteristic capture time constant under various gate bias voltages.

HfO₂

Fig. 3-8 The threshold voltage shift as a function of stress time for nMOSFETs under static stress at various temperatures.

HfO₂

Fig. 3-9 The charge pumping current as a function of base voltage of fresh and stressed conditions under various stress temperatures.

HfO₂

Fig. 3-10 The threshold voltage shift as a function of stress time for nMOSFETs under static stress at various dimensions.

HfO₂

W/L = 10/0.7μm

ΔV

_T

(mV)

0 20 40 60 80

Δ I

Dsat

/I

D0sat

( % ) Degr ada ti o n -20

0 20 40 60

V_G = 1.5V V_G = 1.6V V_G = 1.75V V_G = 1.9V V_G = 2.0V Fit curve

Fig. 3-11 The drain current degradation (ΔId,sat/ Id0,sat) can be linearly transformed with the threshold voltage shift (ΔVT).

HfO₂

W/L = 10/0.4μm V_G,stress = 2.0V

Stress Time (sec)

0 500 1000 1500 2000 2500 Δ I

Dsat

/I

D0sat

( % )

0 10 20 30 40

50

_V

recovery = -1.4V Vrecovery = -0.7V Vrecovery = 0V Vrecovery = 0.7V Vrecovery = 1.4V

Fig. 3-12 The drain current degradation for nMOSFETs under static stress/recovery time with a fixed stress voltage Vg=+2.0V and various recovery voltages Vg =+1.4

～-1.4V.

HfO₂

Δ I

Dsat

/I

D0sat

( % ) Degradati o n 10

Fig. 3-13 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under recovery at various recovery voltages. (b) The characteristic emission time constant under various recovery voltages.

log(τ

_c

/τ

_c0

) ρ( τ

c

)τ

^c

/ ρ( τ

c0

)τ

^c0

0.2 0.4 0.6 0.8 1.0 1.2

1.4 γ = 0.26 (V_recovery =-1.4V) γ = 0.46 (V_G,stress = 2.5V) γ = 0.62(V_recovery = 1.4V) γ = 0.49 (V_G,stress = 1.5V)

10^-4 10^-3 10^-2 10^-1 10⁰ 10¹ 10² 10³

Fig. 3-14 The trapped charge density distribution versus capture time under different stress voltages.

HfO₂

W/L = 10/0.4μm V_r = 0V

Stress/Recovery Time (sec)

0 500 1000 1500 2000

Δ I

Dsat

/I

D0sat

( % )

0.0 0.2 0.4 0.6 0.8 1.0 1.2

V_G = 1.5V V_G = 2.0V V_G = 2.2V V_G = 2.5V

Fig. 3-15 The drain current degradation for nMOSFETs under static stress/recovery time with various voltages Vg=+1.5～2.5V and a fixed recovery voltage Vg =0V.

HfO₂

W/L = 10/0.4μm V_r = 0V

Recovery Time (sec)

10⁰ 10¹ 10² 10³ 10⁴

Δ I

Dsat

/I

D0sat

( % ) Degradati o n

0.01 0.1 1

V_G = 1.5V γ=0.494 V_G = 2.0V γ=0.475 V_G = 2.2V γ=0.469 V_G = 2.5V γ=0.467 fit curve

HfO₂

W/L = 10/0.4μm V_recovery = 0V

Stress Voltage(V)

1.4 1.6 1.8 2.0 2.2 2.4 2.6 τ e0 (sec)

10¹ 10² 10³

fit curve

Fig. 3-16 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under recovery at various stress voltages. (b) The characteristic emission time constant under various stress voltages.

HfO₂

W/L = 10/0.4μm V_G,Stress = 2.0 V

Stress/Recovery Time (sec)

0 2000 4000 6000 8000 10000 12000

I

d

D e gr e da ti on ( % )

0 10 20 30 40 50

Vr = -2.0V Vr = -0.7V Vr = 0V Vr = 0.7V

Fig. 3-17 The drain current degradation for nMOSFETs under static stress/recovery time with a fixed stress voltage Vg=+2.0V and various recovery voltages Vg =+0.7

～-2.0V.

Fig. 3-18 Id-Vd curves under (a) 25℃ (b) 50℃ (c) 75℃ (d) 125℃ by two measurement methods: DC ramp and pulsed I-V.

Chapter 4

Constant Voltage Stress and Negative Bias

Temperature Insatiability Stress in pMOSFETs with HfO

₂

/SiON High-k Gate Stacks and the Effects of

Fluorine incorporation

4.1 Introduction

Compared to nMOSFETs, limited works have focused on the physics of negative bias temperature instability (NBTI) in high-k pMOSFETs [1]-[3]. The model proposed by Zafar et al. the creation of positive oxide charge carriers to de-passivation of Si/SiO2

interface [1]. As Si-H bonds break, hydrogen diffuses away and reacts with the oxide, thereby generating positive charge carriers in the interface and in the oxide. On the other hand, Houssa et al. presented the impact of forming gas annealing and of Hf content on NBTI [2], [3]. According to their study, the responsible defects are hydrogen-induced overcoordinated oxygen centers induced by the transport and trapping of H⁺ in the gate dielectric stacks. Therefore, it is complicated that there are two mechanisms causing threshold voltage shift in high-k gate dielectrics under NBTI:

(1) the de-passivation of Si-H bonds and (2) the charge trapping for pMOSFETs with high-k gate dielectric. Thus, the constant voltage stress (CVS) method that induces less degradation of Si/SiO2 interface can be used to analyze the charge trapping and de-trapping mechanisms. The hole trapping is attributed to filling of pre-existing traps in the high-k dielectrics without the creation of additional traps. In order to suppress the degradation of pMOSFETs under NBT stress, fluorine incorporation used to retard the

degradation on the constant voltage stress and negative bias stress of pMOSFETs has been reported [4].

In this chapter, the charge trapping behavior under constant voltage stress and NBT stress will be studied in detail to realize the physical model in section 4.3. In section 4.4, the charge de-trapping behavior under various stress voltages and recovery voltages will be investigated by the charge de-trapping model proposed in chapter 3. The effect of fluorine incorporation will be investigate in section 4.5. Finally, the transient charge trapping behavior will be analyzed by pulsed I-V measurement.

4.2 Device Fabrication

pMOSFET devices with the poly-Si/HfO2/SiON high-k gate stacks were fabricated using the conventional CMOS process technology. After conventional LOCOS isolation, some samples received fluorine ion implantations (F: 5E13 cm^-2 and 5E14 cm^-2). Then, the interfacial oxide (～1.0 nm) was formed by oxide rapid thermal anneal (RTA) at 800℃ in N2O ambient with 30s, followed by the deposition of the HfO2 (～3.0 nm) high-k gate dielectric using atomic layer deposition (ALD) technique. The 200 nm poly-Si was deposited by low pressure chemical vapor deposition (LPCVD). After gate definition, spacer formation, and S/D implantation, the capping layer was deposited by plasma chemical vapor deposition (PECVD). The equivalent oxide thickness of above mentioned high-k gate stack was extracted to be 2.5 ～ 3.0 nm by using C-V measurement.

4.3 Hole Trapping Behaviors during Stress in High-k Gate Dielectric Fig. 4-1 shows the charge pumping current as a function of top voltage of fresh and

stressed conditions. Under constant voltage stress, the interface states by charge pumping measurement seemed unchanged. Because of that, creation of additional new traps during stressing is assumed to be negligible. Thus, it implies that the hole trapping and de-trapping behaviors are occurred in the pre-existing traps of the HfO2 gate dielectric under constant voltage stress.

Fig. 4-2 shows the threshold voltage shift as a function of stress time for pMOSFETs under static stress at various gate bias voltages. The threshold voltage shift in this study is determined from the static Id-Vg characteristics. The symbols in Fig.4-2 are measurement data and the solid lines are the fits to the results using the physical model discussed in chapter 3. By Eq. 4.1, the three parameters (ΔVmax, γ, and τc0) that can well describe the behavior of charge trapping would be obtained in by fitting the symbols of Fig. 4-2 (a). The fitting results: ΔVmax increased, γ decreased , and τc0 decreased with increasing stress voltage. The trends of the three parameters are the same with those of nMOSFETs in chapter 3. Thus, we can know that the hole trapping behavior is similar to the electron trapping behavior in slow traps. Compared to nMOSFETs, the values of smaller maximum threshold voltage shift, the wider distribution of capture time, and the longer characteristic time constant (Fig. 4-2 (b)) could be found in pMOSFETs. These differences can be assumed due to the intrinsic characteristics between electron and hole.

Fig. 4-3 shows the threshold voltage shift as a function of stress time for pMOSFETs under static stress at various temperatures. In the first stage, the Vt shift decreased with increasing stress temperature. The reason can be suggested that the de-trapping

mechanism is dominant under higher stress temperature. Then, the Vt shift under higher stress temperature increasingly exceeded that under lower stress temperature because the generated traps became dominant. Moreover, the interface trap density measured by CP degraded more serious under higher stress temperature in Fig. 4-4.

4.4 Hole De-trapping Behavior during the Stress/Recovery Cycles in High-k Gate Dielectric

Fig. 4-5 shows the threshold voltage shift for pMOSFETs under static stress/recovery time with a fixed stress voltage Vg=-2.0V and various recovery voltages Vg =0～1.0V.

Under strong recovery voltage such as Vg=1.0V, almost all the trapped holes in the HfO2

traps could be de-trapped. As the recovery voltage was weaker, the residual holes that couldn’t be de-trapped become more. Fig. 4-6 (a) shows the recovery region of Fig. 4-5.

The symbols are measurement data and the solid lines are the fits to the results using the physical model that is built in chapter 3.

⎥⎦ describe the behavior of charge de-trapping are obtained by fitting the symbols of Fig.

4-6 (a). The fitting results: ΔVde,MAX increased, ΔVresidue decreased, γ decreased, and τe0

decreased (Fig. 4-6 (b)) with stronger recovery voltage. The trends of the four parameters are the same with those of nMOSFETs in chapter 3. Thus, we can know that the hole de-trapping behavior is similar to the electron de-trapping behavior under various recovery voltages in slow traps. However, the holes could be de-trapped only under reverse voltage but the electrons could be de-trapped under the recovery voltage

which is just smaller than stress voltage. Moreover, the electron trapping would happen as the recovery voltage is stronger in pMOSFETs.

Fig. 4-7 shows the threshold voltage shift for pMOSFETs under static stress/recovery time with various recovery voltages Vg=-2.0～-3.0V and a fixed stress voltage Vg =1.0V.

The fitting results: ΔVde,MAX increased, ΔVresidue increased, γ decreased, and τe0

decreased with increasing stress voltage in Fig. 4-8 (a) (b). The trends of the four parameters are the same with those of nMOSFETs in chapter 3. Thus, the hole de-trapping behavior is similar to the electron de-trapping behavior under various stress voltages in slow traps.

4.5 Fluorine Incorporation

Fig. 4-9 (a) (b) show Id-Vg and Gm-Vg curves of pMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with fluorine and without fluorine. From Id-Vg curves, drain current would be larger in the device with fluorine. In Gm-Vg curve, the same phenomenon would also be occurred. Turn-on current which varies with gate voltage also represented larger in the device with fluorine in Fig. 4-10. Fig. 4-11 shows Icp-Vtop curves by charge pumping method of pMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with and without fluorine. From Icpmax of Icp-Vtop curves, the interface trap density could be obtained. The interface state of with fluorine devices could be improved slightly.

Fig. 4-12 shows the threshold voltage shift as a function of stress time for pMOSFETs under NBT stress in the devices with and without fluorine. The result showed that fluorine incorporation could suppress the Vt shift under NBT stress.

However, the improvement mechanisms of fluorine could be interface trap density of Si/SiON or the bulk traps of HfO2. First, the interface state could be passivated by

fluorine. Thus, Si-H bonds could be replaced by Si-F bonds and the Si-F bonds would be stronger than the Si-H bonds. The Si-F couldn’t so easy be broken that the fluorine passivation would suppress the Vt shift. Second, the bulk traps of HfO2 could be passivated by fluorine and the Vt shift would be suppressed. Fig. 4-13 shows the charge pumping current under fresh and stressed conditions in the devices with and without fluorine. The interface states couldn’t be protected under NBT stress by fluorine incorporation. Fig. 4-14 shows the normalized density from the two-frequency CP method in the devices with and without fluorine. The two-frequency CP method can be used to characterize high-k trap generation [5]. The high-k trap density is obtained from the difference between CP results at two frequencies.

⎥⎦

The result of Fig. 4-14 can prove that the fluorine incorporation can suppress the bulk traps generation under NBT stress.

4.6 Fast Hole Trapping Behavior in High-k Gate Dielectric

Fig. 4-15 shows Id-Vd curves under (a) 25℃ (b) 50℃ (c) 75℃ (d) 125℃ by two measurement methods: DC ramp and pulsed I-V. In Fig. 4-15 (a), the charge loss would be more serious with increasing gate voltage. Moreover, the charge loss would be retarded with increasing the measurement temperature because the de-trapping mechanism is dominant. Compared to nMOSFETs, the temperature effect inducing the de-trapping mechanism is less obvious in pMOSFETs. Fig. 4-16 shows Id-Vd curves in the devices (a) without and (b) with fluorine by DC ramp and pulsed I-V measurement.

The less charge loss could be showed in the device with fluorine. Moreover, Fig. 4-16 shows Id-Vd curves in the device (c) without fluorine and (d) with fluorine after stress by DC ramp and pulsed I-V measurement. The less increasing of the generation trap density could be detected in the device of fluorine. The behavior of the fast traps is similar to that of the slow traps in temperature effect and condition effect (with/without fluorine).

4.7 Summary

Hole trapping and de-trapping characteristics are investigated in the pre-existing traps of the HfO2 high-k gate dielectric. During the constant voltage stress/recovery, Vt shift continues to grow/decay and eventually become saturated, whereas the interface trap density remains unchanged. According to the fitting results with the model discussed in chapter 3, we can find that the trends of the results are similar to that of nMOSFETs.

Thus, we can know that the hole trapping and de-trapping behaviors are similar to the electron trapping and de-trapping behaviors in slow traps. The difference is just the intrinsic characteristics between electron and hole. From the temperature effect, the de-trapping mechanism is dominant in the first stage of the stress time and the mechanism of generation traps is dominant as the stress time is prolonged.

Fluorine incorporation can suppress the Vt shift due to many reasons. We can confirm that the improvement is due to the passivation in bulk traps of HfO2 by our data. The fast traps can be detected by pulsed I-V measurement and the results are similar to those of slow traps in temperature effect and condition effect.

References

[1] Sufi Zafar, Byoung H. Lee, James Stathis, Allesandro Callegari and Tak Ning “A Model for Negative Bias Temperature Instability in Oxide and High-K pFETs,”

VLSI Tech. Dig. pp. 208-209, 2004

[2] M. Houssa, S. De Gendt, J.L. Autran(+), G. Groeseneken, and M.M. Heyns,

“Detrimental Impact of Hydrogen on Negative Bias Temperature Instabilities in Hf02-Based pMOSFETs,” VLSI Tech. Dig. pp. 212-213, 2004.

[3] M. Houssa, M. Aoulaiche, S. Van Elshocht, S. De Gendt, G. Groeseneken, and M. M.

Heyns “Impact of Hf content on negative bias temperature instabilities in HfSiON-based gate stacks,” APPLIED PHYSICS LETTERS 86, 173509 (2005).

[4] Wen-Tai Lu, Chao-Hsin Chiein, Wen-Ting Lan, Tsung-Chieh Lee, Peer Lehnen, and Tiao-Yuan Huang, “Improved reliability of HfO2/SiON gate stack by fluorine incorporation,” IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006.

[5] R. Degraeve, A. Kerber, Ph. Roussel, E. Cartier, T. Kauerauf, L. Pantisand, G.

Groeseneken, “Effect of bulk trap density on HfO2 reliability and yield,” IEDM 03-935

HfO₂

W/L = 10/4mm

Top Voltage (V)

-0.5 0.0 0.5 1.0 1.5

- I

cp

(n A )

0 2 4 6 8 10 12 14

fresh after CVS

V_G = -3.0V,5000s

Fig. 4-1 The charge pumping current as a function of top voltage of fresh and stressed conditions.

HfO2

W/L = 10/1.5μm

Stress Time (sec)

1 10 100 1000

-Δ

V T (V)

0.01 0.1

V_G = -2.2V γ=0.15 V_G = -2.5V γ=0.11 V_G = -3.0V γ=0.10 fit curve

T = 25C HfO₂

Stress Voltage (V)

-3.2 -3.0 -2.8 -2.6 -2.4 -2.2 -2.0

τ c0 (s)

10

^-2

10

^-1

10

⁰

10

¹

10

²

Fig. 4-2 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under static stress at various gate bias voltages. (b) The characteristic capture time constant under various gate bias voltages.

HfO₂

Fig. 4-3 The threshold voltage shift as a function of stress time for pMOSFETs under static stress at various temperatures.

HfO₂

Fig. 4-4 The charge pumping current as a function of top voltage of fresh and stressed conditions under various stress temperatures.

HfO₂

W/L = 10/2μm V_G,stress = -2.0V

Stress/Recovery Time (sec)

0 500 1000 1500 2000

−Δ V

T

(m V )

-4 -2 0 2 4 6 8 10 12 14

Vr = 0V Vr = 0.7V Vr = 1.0V

Fig. 4-5 The threshold voltage shift for pMOSFETs under static stress/recovery time with a fixed stress voltage Vg=-2.0V and various recovery voltages Vg =0～

1.0V.

HfO₂

Fig. 4-6 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under recovery at various recovery voltages. (b) The characteristic emission time constant under various recovery voltages.

HfO₂

W/L = 10/1μm Vr = 1.0V

Stress/Recovery Time (sec)

0 500 1000 1500 2000

−Δ V

T

(m V ) 0 10 20 30 40

V_G = -2.0V V_G = -2.5V V_G = -3.0V

Fig. 4-7 The threshold voltage shift for pMOSFETs under static stress/recovery time with various recovery voltages Vg=-2.0～-3.0V and a fixed stress voltage Vg

=1.0V.

HfO₂

W/L = 10/1μm Vr = 1.0V

Recovery Time (sec)

10

⁰

10

¹

10

²

10

³

−ΔV T(mV)

40

10

^VG = -2.0V γ=0.18 V_G = -2.5V γ=0.15 V_G = -3.5V γ=0.10 fit curve

HfO₂

W/L = 10/1μm V_recovery = 1.0V

Stress Voltage (V)

-3.6 -3.4 -3.2 -3.0 -2.8 -2.6 -2.4 -2.2 -2.0 -1.8

τ e0 (sec)

10

³

10

⁴

10

⁵

Fig. 4-8 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under recovery at various stress voltages. (b) The characteristic emission time constant under various stress voltages.

HfO₂ high-k gate stack in the devices with fluorine and without fluorine.

Drain Voltage (V)

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

Drain Current (μA)

0

Fig. 4-10 Id-Vd curves of pMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with and without fluorine.

pMOSFET

Fig. 4-11 Icp-Vtop curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with and without fluorine.

HfO₂

W/L = 10/5μm

V_G - V_T = -2.0V,150C

Stress Time (sec)

10

^-1

10

⁰

10

¹

10

²

10

³

10

⁴

-Δ

V

T

(m V )

10 100

w/o F

F : 5E-13 (cm^-2) F : 5E-14 (cm^-2)

Fig. 4-12 The threshold voltage shift as a function of stress time for pMOSFETs under NBT stress in the devices with and without fluorine.

在文檔中 在二氧化鉿為基底之高介電係數閘極介電層中的載子捕捉與逃逸的電性行為 (頁 52-0)