Electron trapping behaviors during stress in high-k gate dielectric

function of stress time for nMOSFETs under static stress at various gate bias voltages.

The gate leakage current density increases with stress voltage. The symbols in Fig. 3-1 (a) are the measurement data and the solid lines are power law fits to the results. Since Jg is observed to decrease with stress time, it implies that no new traps in the bulk are created during stressing. The subthreshold slope remains constant with stress time

regardless of stress voltage. Since interfacial trap density can be detected by subthreshold slope, it is concluded that no new interfacial traps are created during stressing. Therefore, creation of additional new traps during stressing is assumed to be negligible. Thus, it implies that the electron trapping and de-trapping behaviors are occurred in the pre-existing traps of the HfO2 gate dielectric.

Fig. 3-2 shows the threshold voltage shift as a function of stress time for nMOSFETs under static stress at various gate bias voltages. The threshold voltage shift in this study is determined from the static Id-Vg characteristics. The symbols in Fig.3-2 are measurement data and the solid lines are the fits to the results using the physical model proposed by Zafar et al. The model assumes that the injected charge carriers are captured with dispersive capture time constant in the pre-existing bulk traps of the high-k gate dielectrics without additional new traps generated during the static stress.

The operation process of the model that is a little different from that by Zafar et al. is showed as followings:

c

However, the modeling equation (3.3) of the model is the same with that of Zafar’s model.

Where nT is the trapped charge density, ρ(τc) is the trapped charge density per second with continuous capture time constant, Ntot is the total density of traps of the HfO2 gate

dielectric, τc/τc0 is the capture time constant/characteristic capture time constant, t is the stress time, γ is the distribution factor of ρ(τc) versus capture time constant, ΔVmax is the maximum threshold voltage shift, q is the magnitude of electronic charge, xeff is the centroid of trapped charge, area is the gate area, and ε is the permittivity of the dielectric.

By Eq. 3.3, the three parameters (ΔVmax, γ, and τc0) that well describe the behavior of charge trapping would be obtained by fitting the symbols of Fig. 3-2. These parameters would be dependent on stress voltage with trends in Table 3-1. First, the maximum Vt

shift dependent on Ntot, and xeff (q, ε, and area are fixed values) increased with increasing stress voltage. However, Ntot had been assumed a fixed value in the original of the model used in SiO2 [4]. Then, the ratio of ΔVmax of 3.0V to ΔVmax of 1.5V 8:1 would be equal to the ratio of xeff of 3.0V to xeff of 1.5V. This is inconsistent with physical principle because the maximum ratio of total thickness of the gate dielectrics to the thickness of SiON is smaller than 8:1. Thus, it could be assumed that the total density of traps (Ntot) would be a function of stress voltage and Ntot increased with increasing stress voltage. The total density of traps truly represents the maximum density of traps that can be filled by charge carriers under specific stress voltage. Next, it is inconsistent with Zafar’s previous work in the γ factor which is only dependent on high-k materials. However, the decreasing γ factor with increasing stress voltage that is consistent with our results has been reported by using power law fitting method in [5].

Therefore it is probable that the γ factor is dependent not only on high-k materials but also on stress voltage. The smaller γ factor under higher stress voltage represents the wider distribution of the capture time. According to above mentions of Ntot and γ, the trapped charge density distribution versus capture time under different stress voltages could be predicted and roughly plotted in Fig. 3-4 [6]. In the first stage of the each curve in Fig. 3-4, the increasing charge density along increasing capture time would be due to

the capture time increasing with stress time. Then, the each curve of Fig. 3-4 would reach the maximum value and become decay with capture time because the trapped electrons could build an energy barrier that induced the electrons injecting to high-k gate dielectric harder. Finally, the maximum trap density would be fully filled by electrons and the Vt shift would reach a constant. At last, the characteristic capture time constant would decrease with increasing stress voltage in Fig. 3-3due to the increasing injected charge carriers. Thus, the “early trapped” (0～1s) charge carriers would increase with increasing stress voltage demonstrated in Fig. 3-5.

The same fitting model could be used in the drain current degradation under various stress voltages in Fig. 3-6 and the trends of the parameters would be the same with the results of threshold voltage shift. Moreover, Fig. 3-7 (a) shows the threshold voltage shift as a function of stress time for HfAlO high-k gate dielectric under static stress at various gate bias voltages. Fig. 3-7 (b) shows the characteristic capture time constant under various gate bias voltages. The results showed the same trends in the three parameters with the HfO2 high-k gate dielectric and could be fitted by the same model.

Comparing with the γ factor of the HfO2 gate dielectric under the same voltage, γ varies with different high-k materials and that is consistent with the Zafar’s previous work.

Fig. 3-8 shows the threshold voltage shift as a function of stress time for nMOSFETs under static stress at various temperatures. The Vt shift decreased with increasing stress temperature. The reason can be suggested that the de-trapping mechanism is dominant under higher stress temperature. Although the Vt shift seemed to slow down under higher stress temperature, the generated interface trap density measured by CP degraded more serious in Fig. 3-9. Fig. 3-10 shows the threshold voltage shift as a function of stress time for nMOSFETs under static stress at various dimensions. The Vt shift with stress time would be dependent on gate length, but independent on gate width.

Moreover, the increasing gate length increased the Vt shift. The phenomenon can be

suggested that larger gate length with smaller source/drain overlap ratio induces more Vt

shift because the electric field in the S/D overlap region smaller than that in the channel under the positive stress voltage.

3.4 Electron De-trapping Behavior during the Stress/Recovery Cycles