Chapter 4: Constant Voltage Stress and Negative Bias
4.5 Fluorine Incorporation
Fig. 4-9 (a) (b) show Id-Vg and Gm-Vg curves of pMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with fluorine and without fluorine. From Id-Vg curves, drain current would be larger in the device with fluorine. In Gm-Vg curve, the same phenomenon would also be occurred. Turn-on current which varies with gate voltage also represented larger in the device with fluorine in Fig. 4-10. Fig. 4-11 shows Icp-Vtop curves by charge pumping method of pMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with and without fluorine. From Icpmax of Icp-Vtop curves, the interface trap density could be obtained. The interface state of with fluorine devices could be improved slightly.
Fig. 4-12 shows the threshold voltage shift as a function of stress time for pMOSFETs under NBT stress in the devices with and without fluorine. The result showed that fluorine incorporation could suppress the Vt shift under NBT stress.
However, the improvement mechanisms of fluorine could be interface trap density of Si/SiON or the bulk traps of HfO2. First, the interface state could be passivated by
fluorine. Thus, Si-H bonds could be replaced by Si-F bonds and the Si-F bonds would be stronger than the Si-H bonds. The Si-F couldn’t so easy be broken that the fluorine passivation would suppress the Vt shift. Second, the bulk traps of HfO2 could be passivated by fluorine and the Vt shift would be suppressed. Fig. 4-13 shows the charge pumping current under fresh and stressed conditions in the devices with and without fluorine. The interface states couldn’t be protected under NBT stress by fluorine incorporation. Fig. 4-14 shows the normalized density from the two-frequency CP method in the devices with and without fluorine. The two-frequency CP method can be used to characterize high-k trap generation [5]. The high-k trap density is obtained from the difference between CP results at two frequencies.
⎥⎦
The result of Fig. 4-14 can prove that the fluorine incorporation can suppress the bulk traps generation under NBT stress.
4.6 Fast Hole Trapping Behavior in High-k Gate Dielectric
Fig. 4-15 shows Id-Vd curves under (a) 25℃ (b) 50℃ (c) 75℃ (d) 125℃ by two measurement methods: DC ramp and pulsed I-V. In Fig. 4-15 (a), the charge loss would be more serious with increasing gate voltage. Moreover, the charge loss would be retarded with increasing the measurement temperature because the de-trapping mechanism is dominant. Compared to nMOSFETs, the temperature effect inducing the de-trapping mechanism is less obvious in pMOSFETs. Fig. 4-16 shows Id-Vd curves in the devices (a) without and (b) with fluorine by DC ramp and pulsed I-V measurement.
The less charge loss could be showed in the device with fluorine. Moreover, Fig. 4-16 shows Id-Vd curves in the device (c) without fluorine and (d) with fluorine after stress by DC ramp and pulsed I-V measurement. The less increasing of the generation trap density could be detected in the device of fluorine. The behavior of the fast traps is similar to that of the slow traps in temperature effect and condition effect (with/without fluorine).
4.7 Summary
Hole trapping and de-trapping characteristics are investigated in the pre-existing traps of the HfO2 high-k gate dielectric. During the constant voltage stress/recovery, Vt shift continues to grow/decay and eventually become saturated, whereas the interface trap density remains unchanged. According to the fitting results with the model discussed in chapter 3, we can find that the trends of the results are similar to that of nMOSFETs.
Thus, we can know that the hole trapping and de-trapping behaviors are similar to the electron trapping and de-trapping behaviors in slow traps. The difference is just the intrinsic characteristics between electron and hole. From the temperature effect, the de-trapping mechanism is dominant in the first stage of the stress time and the mechanism of generation traps is dominant as the stress time is prolonged.
Fluorine incorporation can suppress the Vt shift due to many reasons. We can confirm that the improvement is due to the passivation in bulk traps of HfO2 by our data. The fast traps can be detected by pulsed I-V measurement and the results are similar to those of slow traps in temperature effect and condition effect.
References
[1] Sufi Zafar, Byoung H. Lee, James Stathis, Allesandro Callegari and Tak Ning “A Model for Negative Bias Temperature Instability in Oxide and High-K pFETs,”
VLSI Tech. Dig. pp. 208-209, 2004
[2] M. Houssa, S. De Gendt, J.L. Autran(+), G. Groeseneken, and M.M. Heyns,
“Detrimental Impact of Hydrogen on Negative Bias Temperature Instabilities in Hf02-Based pMOSFETs,” VLSI Tech. Dig. pp. 212-213, 2004.
[3] M. Houssa, M. Aoulaiche, S. Van Elshocht, S. De Gendt, G. Groeseneken, and M. M.
Heyns “Impact of Hf content on negative bias temperature instabilities in HfSiON-based gate stacks,” APPLIED PHYSICS LETTERS 86, 173509 (2005).
[4] Wen-Tai Lu, Chao-Hsin Chiein, Wen-Ting Lan, Tsung-Chieh Lee, Peer Lehnen, and Tiao-Yuan Huang, “Improved reliability of HfO2/SiON gate stack by fluorine incorporation,” IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006.
[5] R. Degraeve, A. Kerber, Ph. Roussel, E. Cartier, T. Kauerauf, L. Pantisand, G.
Groeseneken, “Effect of bulk trap density on HfO2 reliability and yield,” IEDM 03-935
HfO2
W/L = 10/4mm
Top Voltage (V)
-0.5 0.0 0.5 1.0 1.5
- I
cp(n A )
0 2 4 6 8 10 12 14
fresh after CVS
VG = -3.0V,5000s
Fig. 4-1 The charge pumping current as a function of top voltage of fresh and stressed conditions.
HfO2
W/L = 10/1.5μm
Stress Time (sec)
1 10 100 1000
-Δ
V T (V)
0.01 0.1
VG = -2.2V γ=0.15 VG = -2.5V γ=0.11 VG = -3.0V γ=0.10 fit curve
T = 25C HfO2
Stress Voltage (V)
-3.2 -3.0 -2.8 -2.6 -2.4 -2.2 -2.0
τ c0 (s)10
-210
-110
010
110
2Fig. 4-2 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under static stress at various gate bias voltages. (b) The characteristic capture time constant under various gate bias voltages.
HfO2
Fig. 4-3 The threshold voltage shift as a function of stress time for pMOSFETs under static stress at various temperatures.
HfO2
Fig. 4-4 The charge pumping current as a function of top voltage of fresh and stressed conditions under various stress temperatures.
HfO2
W/L = 10/2μm VG,stress = -2.0V
Stress/Recovery Time (sec)
0 500 1000 1500 2000
−Δ V
T(m V )
-4 -2 0 2 4 6 8 10 12 14
Vr = 0V Vr = 0.7V Vr = 1.0V
Fig. 4-5 The threshold voltage shift for pMOSFETs under static stress/recovery time with a fixed stress voltage Vg=-2.0V and various recovery voltages Vg =0～
1.0V.
HfO2
Fig. 4-6 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under recovery at various recovery voltages. (b) The characteristic emission time constant under various recovery voltages.
HfO2
W/L = 10/1μm Vr = 1.0V
Stress/Recovery Time (sec)
0 500 1000 1500 2000
−Δ V
T(m V ) 0 10 20 30 40
VG = -2.0V VG = -2.5V VG = -3.0V
Fig. 4-7 The threshold voltage shift for pMOSFETs under static stress/recovery time with various recovery voltages Vg=-2.0～-3.0V and a fixed stress voltage Vg
=1.0V.
HfO2
W/L = 10/1μm Vr = 1.0V
Recovery Time (sec)
10
010
110
210
3−ΔV T(mV)
40
10
VG = -2.0V γ=0.18 VG = -2.5V γ=0.15 VG = -3.5V γ=0.10 fit curveHfO2
W/L = 10/1μm Vrecovery = 1.0V
Stress Voltage (V)
-3.6 -3.4 -3.2 -3.0 -2.8 -2.6 -2.4 -2.2 -2.0 -1.8
τ e0 (sec)10
310
410
5Fig. 4-8 (a) The threshold voltage shift as a function of stress time for HfO2 high-k gate dielectric under recovery at various stress voltages. (b) The characteristic emission time constant under various stress voltages.
HfO2 high-k gate stack in the devices with fluorine and without fluorine.
Drain Voltage (V)
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
Drain Current (μA)
0
Fig. 4-10 Id-Vd curves of pMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with and without fluorine.
pMOSFET
Fig. 4-11 Icp-Vtop curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in the devices with and without fluorine.
HfO2
W/L = 10/5μm
VG - VT = -2.0V,150C
Stress Time (sec)
10
-110
010
110
210
310
4-Δ
V
T(m V )
10 100
w/o F
F : 5E-13 (cm-2) F : 5E-14 (cm-2)
Fig. 4-12 The threshold voltage shift as a function of stress time for pMOSFETs under NBT stress in the devices with and without fluorine.
F:5E14(cm-2) ΔNit/Nit = 35.3%
Top Voltage (V)
-0.4 0.0 0.4 0.8 1.2 1.6 -0.4 0.0 0.4 0.8 1.2 1.6 -0.4 0.0 0.4 0.8
Icp (nA)
0 10 20
fresh after stress
F:5E13(cm-2) ΔNit/Nit = 32.3%
w/o F
ΔNit/Nit = 25.8%
Fig. 4-13 The charge pumping current under fresh and stressed conditions in the devices with and without fluorine.
HfO2
W/L = 10/4μm
Frequency (Hz)
10
410
510
6N o m a liz e d H ig h -k tr a p D e n s it y N
HK(s tr essed )/ N
HK(f resh)
1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
w/o F
F : 5E13cm-2
traps close to the interface traps into
high-k bulk
Fig. 4-14 Nonalized high-k trap density (NHK(stressed)/ NHK(fresh)) as a function of frequency in the devices with and without fluorine.
Fig. 4-15 Id-Vd curves under (a) 25℃ (b) 50℃ (c) 75℃ (d) 125℃ by two measurement methods: DC ramp and pulsed I-V.
Fig. 4-16 Id-Vd curves in the devices (a) without and (b) with fluorine by DC ramp and pulsed I-V measurement. Id-Vd curves in the device (c) without fluorine and (d) with fluorine after stress by DC ramp and pulsed I-V measurement.
Chapter 5
Conclusions and Suggestions for Future Work
5.1 Conclusions
In this thesis, the fundamental characteristics and the physical mechanisms of charge trapping and de-trapping in the pre-existing traps in Hf-based high-k gate dielectrics have been studied. The basic electrical characteristics and the charge trapping behaviors of the strain effect in NMOS and the fluorine effect in PMOS also have been discussed completely.
In chapter 2, the strained devices could improve the electrical characteristics of NMOS, but they would induce more threshold voltage shift in high-k material. By F-P and F-N tunneling fitting, we conclude that the strain effect induces bulk traps generated in HfO2. In chapter 3, according to the fitting results with the model proposed by Zafar et al., we can find that the total density of traps is not a fixed value but dependent on stress voltage and the distribution factor of capture time is dependent on not only high-k materials but also stress voltages. Moreover, the fitting results can build the distribution of the trapped charge density with capture time. The recovery model can be built base on the charge trapping model and the recovery model can well fit the measurement data.
In chapter 4, According to the fitting results with the model discussed in chapter 3, we can know that the hole trapping and de-trapping behaviors are similar to the electron trapping and de-trapping behaviors in slow traps. The difference is just the intrinsic characteristics between electron and hole. Moreover, we can confirm that the improvement of the fluorine incorporation is due to the passivation in bulk traps of HfO2 by our data.
5.2 Suggestions for Future Work
There are some works valuable for future researches:
1. The hydrogen passivation of the strain effect could be found in the electrical characteristics. Thus, we can research in the physical analysis to assist our inference from the electrical analysis.
2. The physical model could apply to our data suitably. However, the threshold voltage shift and the drain current degradation would be underestimated because the so-called fast traps couldn’t be detected by conventional DC I-V measurement. Thus, the combination of the stress mode and the pulsed I-V measurement is necessary to obtain the actual data.
3. The fluorine passivation of the fluorine incorporation effect could be found in the electrical characteristics. Thus, we can research in the physical analysis to assist our inference from the electrical analysis.
4. The strain effect in PMOS and the fluorine effect in NMOS can also be investigated.