Summary

The contact-etch-stop-layer (CESL) is one of mobility enhancement methods and it can induce tensile strain to improve mobility for nMOSFETs. In our data, the strained devices could improve the electrical characteristics of NMOS, but they would induce more threshold voltage shift in high-k material. By F-P and F-N tunneling fitting, the trapped energy levels and the barrier heights of stained and unstrained devices are almost the same. Thus, we conclude that the strain effect induces bulk traps generated in HfO2. Form the transient effect by pulsed I-V, the competition of hydrogen passivation and trap generated by strain can be found. The charge loss detected by single pulsed ranging several nanoseconds of strained and unstrained devices represents the interface states improvement due to hydrogen passivation.

References

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Fig. 2-1 The structure of the devices in strained and unstrained samples.

HfO2 high-k gate stack in different capping nitride layers.

VG - VT = 1.0 V

Fig. 2-3 I_d-V_d curves of nMOSFETs with dual-layer HfO₂/SiON high-k gate stack in different thickness of capping nitride layers.

HfO₂

Fig. 2-4 Icp-Vbase curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers.

HfO2

Gate Length (μm)

1 1 0

Gm

0 200 400 600 800 1000 1200

w/o SiN SiN = 200nm SiN = 300nm

Fig. 2-5 Gm,max-Lgate curves of nMOSFETs with dual-layer HfO2/SiON high-k gate stack in different thickness of capping nitride layers.

HfO₂

V_G-V_T = 1.0V W/L = 10/0.7μm

Stress Time (sec)

10

10

10

10

10

10

Δ V

(m V ) 50

10 100

w/o SiN γ=0.36 SiN = 200nm γ=0.38 SiN = 300nm γ=0.38

Fig. 2-6 Threshold voltage shift of nMOSFETs as a function of the stress time in difference thickness of capping nitride layers.

HfO₂ w/o SiN

E

(V/cm)

2200 2400 2600 2800 3000 3200 3400

ln (J /E

)

2200 2400 2600 2800 3000 3200 3400

ln(J/E eff)

The trapped energy levels can be obtained by y-axis intercept.

HfO₂

1/E (cm/MV)

0.055 0.060 0.065 0.070 0.075 0.080 0.085

ln (J /E )

-37 -36 -35 -34 -33 -32 -31

w/o SiN SiN = 200nm SiN = 300nm fit curve

Fig. 2-8 ln(J_G/E_eff) as a function of E_eff^1/2 in the unstrained and strained devices. The barrier heights can be obtained by the slopes.

HfO₂

W/L = 10/0.4μm

V_G - V_T = 1.0V ; V_R = 0V

Stress/Recovery Time (sec)

0 2000 4000 6000 8000 10000

I

D e gr e da ti on ( % )

0 20 40

60

Fig. 2-9 The drain current degradation of nMOSFETs as a function of the stress/recovery time with a fixed stress/recovery voltage +2.0V/0V in difference thickness of capping nitride layers.

Fig. 2-10 Id-Vd curves of (a) unstrained (b) SiN = 200nm (c) SiN = 300nm devices by two measurement methods: DC ramp and pulsed I-V and (d) the distribution of drain current degradation under different conditions.

HfO₂

W/L = 10/0.6μm

Stress Time (ns)

20 30 40 50 60 70 80 90

I

D eg rad at io n (% )

0 1 2 3 4

w/o SiN SiN = 200nm SiN = 300nm

Fig. 2-11 Id,sat as a function of stress time ranging several nanoseconds to 100ns by single pulse measurement.

Chapter 3

Bias Temperature Instability in nMOSFETs with HfO

/SiON High-k Gate Stacks

3.1 Introduction

Threshold voltage instability in Hf-based high-k gate dielectrics has been recognized as one of the most critical reliability issues that need to be solved urgently, especially for the nMOSFETs under substrate electron injection conditions (positive bias stress) [1]. The electrons in channel are injected into the pre-existing bulk traps of the HfO2

high-k gate dielectric by tunneling through the thin interfacial oxide. The pre-existing traps of the HfO2 high-k gate dielectric are positioned above the Si conduction band edge in energy and in the HfO2 bulk layer in space. These pre-existing bulk traps are distributed in a wide range of space and energy [2], thus making the charge trapping model different from that of conventional SiO2 or SiON. Furthermore, the high-k dielectrics are reversible by charge trapping and de-trapping. Thus, it is found that the trapped charge carriers could recover to the pre-stress condition after prolonged recovery time. According to results of the threshold voltage shift and the drain current degradation with stress/recovery time, the model could be built to fit the data with reasonable physical mechanism. However, since the charge carriers could be trapped/de-trapped quickly and easily by applying a forward/reverse bias voltage, the degradation may be underestimated due to the switching and measuring delays in the stress/measure cycles [3]. These so-called fast traps would be detected by transient measurement solving the underestimate of charge trapping in high-k gate dielectrics.

In this chapter, the charge trapping behavior under various voltages, temperature and

geometrics will be studied in detail to comprehend the physical model in section 3.3. In section 3.4, the charge de-trapping behavior under various stress voltages and recovery voltages will be investigated to build the physical model according to the charge trapping model. Finally, the transient charge trapping behavior will be analyzed by pulsed I-V measurement.

3.2 Device Fabrication

nMOSFET devices with the poly-Si/HfO2/SiON high-k gate stacks were fabricated using the conventional CMOS process technology. The interfacial oxide (～1.0 nm) was formed by oxide rapid thermal anneal (RTA) at 800℃ in N2O ambient with 30s, followed by the deposition of the HfO2 (～3.0 nm) high-k gate dielectric using atomic layer deposition (ALD) technique. The 200 nm poly-Si was deposited by low pressure chemical vapor deposition (LPCVD). After gate definition, spacer formation, and S/D implantation, the capping layer was deposited by plasma chemical vapor deposition (PECVD). The equivalent oxide thickness of above mentioned high-k gate stack was extracted to be 2.0～2.5 nm by using C-V measurement.

3.3 Electron trapping behaviors during stress in high-k gate dielectric