CHAPTER 1. INTRODUCTION
1.3 Dissertation Outline
This dissertation is composed of five chapters. The content of each chapter is briefly de-scribed as follows:
Chapter 1 introduces the background regarding the present power factor correction tech-niques and line current harmonics standard. It then lists the research motivations and objec-tives.
Chapter 2 offers a review for proposed techniques for the single-stage AC-DC converters and discusses various issues, trend and challenges.
Chapter 3 first introduces the mechanism of the proposed ICS technique. Then, a new flyback converter employing the proposed ICS scheme is presented. The content in this chap-ter contains circuit description, operation principle, circuit design procedure, and prototype experiment results. In addition, an extended circuit based on topology refinement is proposed for specific applications.
Chapter 4 deals with the problem regarding high bulk capacitor voltage stress at light load. A new flyback-forward converter with the modified ICS scheme proposed in Chapter 3 is presented. The mechanism and performance of the proposed approach for suppressing bulk capacitor voltage stress are discussed in detail. The content also covers several segments which are the same as in Chapter 3.
Chapter 5 summarizes the conclusions of this work and presents suggestions for further work in related research directions.
CHAPTER 2
REVIEW OF EXISTING SINGLE-STAGE AC-DC CONVERTERS
In the last decade, the heat wave of studying single-stage ICS AC-DC converters has re-sulted in hundreds of published papers. For single-stage AC-DC converters, the performance measures, such as efficiency, component count and circuit complexity, component voltage and current stresses, input current quality, etc., are largely dependent on the circuit topology. Thus, the main objective of this chapter is to present a topological study of the representative S2ICS converters and find a topological relationship among various converters. This study can be used to topologically explain the main drawbacks of current S2ICS converters and pursue po-tential topology variations to overcome the barriers that limit the application of S2ICS con-verters.
2.1 Familiar Single-Stage Input Current Shaping (S2ICS) Converters
The concept for S2ICS AC-DC converters can be traced back to some early work pre-sented in 1991 [18], [19]. In article [18], Kherulawa et al. proposed a single power stage with dual outputs, including the desired DC output and a boosting supply in series with the input, as shown in Fig. 2.1. Without active control of the boost supply, a reasonably good input cur-rent shape can be obtained due to the natural characteristics of the boost resonant circuit. This circuit is original but the component count is high. Takahashi et al. proposed another way to realize S2ICS AC-DC converters, which cascades a boost ICS circuit with a DC-DC converter using one switch [19]. As shown in Fig. 2.2(a), a high frequency “dither source” is inserted between the input boost inductor L and the bulk energy-storage capacitor C . Since the dither
source introduces high-frequency pulsating voltage on Lb during one line cycle, the rectifier diode can conduct current even while the instantaneous input line voltage is much lower than the capacitor voltage Vb, as shown in Fig. 2.2(b). As a result, the input current conduction an-gle is significantly enlarged and the input current harmonics are reduced. This circuit presents an early form of the single-stage PFC method that integrates a boost PFC rectifier with a DC-DC converter in a cascade fashion.
So far, many papers have been presented about integrated single-stage AC-DC conver-sion techniques. In order to systematically understand the basic structure and specific per-formance of various converters, it is necessary to categorize the representative circuits pub-lished in recent years. Our survey will focus on the single-stage designs with boost-type ICS cells. From several points of view, including power flow paths, topology structures, and input current shapes, these circuits can be divided into the following categories as introduced in subsections 2.1.1–2.1.4.
Fig. 2.1 Isolated S2ICS technique using a two-output dual-control converter [18].
(a)
(b)
Fig. 2.2 General structure of “dither-rectifier” and its waveforms [19]:
(a) Circuit diagram, (b) conceptual waveforms.
2.1.1 S2ICS Converters with Cascade or Parallel Power Processing Structure
Conventional single-stage AC-DC converters were derived from two-stage scheme and thus synthesized with a cascade method [15]. As shown in Fig. 2.3(a), the single-stage AC-DC converters have the dominant configuration integrating two circuit parts. The first
is a DC-DC circuit with a bulk capacitor Cb placed between this circuit and the ICS cell. The downstream DC-DC cell is used to realize fine output regulation, isolation, and fast dynamic response. In terms of power transfer, the AC input power in such a design must first be trans-ferred into the intermediate bulk capacitor Cb; this process is completed by the ICS cell. Then the power stored on the bulk capacitor Cb is processed again by the DC-DC cell to reach final output. The block diagram for explaining power transfer is shown in Fig. 2.3(b). This double power processing results in low conversion efficiency, which is the product of the efficiency of each functional cell.
(a)
(b)
Fig. 2.3 S2ICS converter with cascade power processing structure: (a) example circuit [15]
and (b) power transfer block diagram.
In order to improve conversion efficiency, some new power transfer approaches have been proposed in [22]–[28] which allow a part of the input power to be processed only once and let the remaining input power to be processed twice while still achieving both high PF and tight output regulation. Those power transfer approaches provide a new way to achieve more efficient and higher power rating S2ICS converters than the conventional double power
processing approach shown in Fig. 2.3. An example circuit of the direct power transfer ap-proach is shown in Fig. 2.4(a) and its power transfer block diagram is shown in Fig. 2.4(b).
(a)
(b)
Fig. 2.4 S2ICS converter with parallel power processing structure: (a) example circuit [25]
and (b) power transfer block diagram.
2.1.2 S2ICS Converters with Two-Terminal or Three-Terminal ICS Cells
With the consideration of ICS realization mechanism, the ICS circuits can be symbolized as two- or three-terminal cells [16], [17]. Each ICS cell contains a boost inductor Lb and two branches, as shown in the dotted rectangle in Fig. 2.5. The charging path Pch is used to charge the boost inductor when the switch S is on. The discharging path Pdis is used to discharge the boost inductor and transfer the energy from the boost inductor to bulk capacitor or output when the switch S is off. The two paths are usually composed of diodes, capacitors, inductors, and extra windings of the transformer or their combinations.
In the implementation of the two-terminal ICS cell, the charging and discharging paths of
Lb are connected in parallel and inserted between the full-bridge rectifier Dr and the bulk ca-pacitor Cb, as shown in Fig. 2.5(a). Notice that one winding coupled to the transformer of a DC-DC converter is contained in the charging path. The polarity arrangement of the addi-tional winding intends the voltage across it being in opposition to the bulk capacitor voltage Vb during the duty-on time of switch S. Therefore, when the switch is on, the voltage across the winding can cancel the capacitor voltage Vb, so that the charging voltage of the boost in-ductor only includes the input voltage. The well-known magnetic-switch (MS) topology pro-posed in [20] is an example circuit, as shown in Fig. 2.6(a). In this converter, the charging and discharging paths use the same branch, namely, MS winding. Contrarily, in the example cir-cuit shown in Fig. 2.6(b), the charging and discharging paths use the different branches [29].
(a)
Tr
RL
+ Vo
-S Lb
vac
Pch
Np Ns Dr
Cb
+ Vb
-X
Flyback or forward
output
Pdis Y
Z
(b)
Fig. 2.5 Single-stage AC-DC converters with ICS cell of (a) two-terminal and (b) three-terminal.
(a)
(b)
Fig. 2.6 Example circuits of S2ICS converter with two-terminal ICS cell: (a) the charging and discharging paths use the same branch [20] and (b) the charging and discharging paths use the different branches [29].
In the implementation of the three-terminal ICS cell, the boost inductor Lb is connected to the full-bridge rectifier Dr; the discharging path is connected to the bulk capacitor Cb; and the charging path is connected to switch S, as shown in Fig. 2.5(b). Therefore, the circuit con-figuration is named three-terminal. Similar to the two-terminal ICS cell, the boost inductor is charged by the input voltage when the switch is on, and discharged through the discharging path. The converter shown in Fig. 2.3(a) is an example circuit.
It is found that the two S2ICS families are functionally equivalent and exhibit very simi-lar performance although they are topologically different [16], [17]. For example, the con-verter shown in Fig. 2.6(b) is functionally equivalent to the one shown in Fig. 2.3(a) when the turns ratio of winding N1 is the same as that of winding Np.
2.1.3 S2ICS Converters with DCM or CCM ICS Cells
In most of the existing S2ICS converters, the ICS cells are operated in DCM to auto-matically achieve input PFC function. The mechanism is explained as follows. Since instan-taneous AC input power always varies, a bulky capacitor is needed to buffer the instaninstan-taneous difference between the varying input power and a constant output power such that the output voltage is regulated tightly and free of line frequency ripple. Because the bulk capacitor is sufficiently large, the bulk capacitor voltage Vb can keep in the condition with small ripple.
Thus, the switch duty cycle is almost constant during one line cycle in the steady-state, and the line current can automatically track the line voltage by operating the boost inductor in DCM, as shown in Fig. 2.7(a).
Although the concept of the basic DCM S2ICS is very simple, it will introduce higher input inductor current ripple and more power loss due to the relatively high current stress. To reduce EMI filter size and improve conversion efficiency, several new CCM ICS techniques have been proposed in resent years [36]-[41]. Most of these methods are implemented by in-creasing the boost inductance or adding extra passive components to the DCM ICS cell. The corresponding input current waveforms are shown in Fig. 2.7(b). Although the line current generated by the CCM ICS cell is slightly deformed as compared to sinusoid, it has low har-monic components and can meet IEC 61000-3-2 Class D requirements.
i
Lb|i
ac|
t
(a) (b) Fig. 2.7 Boost inductor current and its corresponding line current waveforms generated by
(a) DCM ICS cell and (b) CCM ICS cell.
2.1.4 S2ICS Converters with Current-Source or Voltage-Source ICS Cells
To achieve CCM boost inductor current, several CCM S2ICS techniques have already been proposed in recent years [38]-[41]. Among them, there are two typical CCM S2ICS techniques. Fig. 2.8 shows one type of CCM S2ICS technique that incorporates an additional high-frequency inductor L1. Fig. 2.9 shows another CCM S2ICS technique with an additional high-frequency capacitor C1. Since the inductor L1 is comparable to a high-frequency current source, the circuits in Fig. 2.8 are named as current-source S2ICS (CS-S2ICS) converters.
Similarly, since the capacitor C1 is comparable to a high-frequency voltage source, the circuits in Fig. 2.9 are named as the voltage-source S2ICS (VS-S2ICS) converters. As shown in Figs.
2.8 and 2.9, each circuit utilizes an additional passive component, L1 or C1, on the original DCM S2ICS to get continuous inductor current.
Tr Fig. 2.8 Current-source S2ICS Converters with ICS cell of (a) two-terminal and (b)
three-terminal. Fig. 2.9 Voltage-source S2ICS Converters with ICS cell of (a) two-terminal and (b)
three-terminal.
2.2 Main Issues of Single-Stage AC-DC Scheme
The underlining strategy of the single-stage AC-DC scheme is to design the converter that allows its PFC and DC-DC conversion circuits to share the same power switch with the same controller. From the above existing research efforts, we found that this kind of arrange-ment results in several main issues.
The first issue is the high current stress on the power switch since it handles current from both the AC mains and the bulk capacitor synchronously. Moreover, the ICS cell in a S2ICS AC-DC converter normally operates in DCM to utilize its inherent current shaping capability;
therefore, this issue becomes more deteriorated. Obviously, when compared with the conven-tional two-stage schemes, S2ICS AC-DC converters have relatively high switch current stress.
High current stress not only causes low conversion efficiency and high temperature rise, but also brings about annoying EMI issues.
The second issue is that the bulk capacitor voltage stress is critical since it is no longer regulated and increases while the input line voltage increases or load current decreases. This is because only a single control loop for the output voltage regulation, and the bulk capacitor voltage is determined by the input to output average power balance [33]. The high bulk ca-pacitor voltage stress generally exists for most of S2ICS converters, and this issue is more se-vere under high line and light load condition [49]. Thus, it is difficult to use S2ICS converters for the applications that require a universal input voltage of 90–260 Vrms. Moreover, a high bulk capacitor voltage means high component rating, high cost and low conversion efficiency.
For the commercial consideration, the maximum bulk capacitor voltage must be held below 450 V, so that a commercially available 450 V-rated electrolytic capacitor can be used safely.
2.3 Several Familiar Schemes to Alleviate Bulk Capacitor Voltage Stress Many off-line power supplies must be able to have a universal-line input, which means
the power converter may be operated with the international utility voltage. For example, in the United States, the single-phase input voltage is in the 90–135 Vrms range, while the input voltage is in the 180–260 Vrms range in Europe. A wide line voltage range may pose an enormous challenge to designing S2ICS converters, especially in alleviating bulk capacitor voltage stress. To suppress high bulk capacitor voltage stress, numerous methods have been presented [50]. In this section, four representative schemes to suppress bus capacitor voltage stress are analyzed and discussed. Through understanding the approaches of alleviating bus capacitor voltage stress, it is helpful to derive and develop new topologies of S2ICS convert-ers.
2.3.1 Variable-Frequency Control
The variable-frequency control was proposed in [49]. Since the voltage gain of the CCM DC-DC cell depends only on the duty ratio, and the voltage gain of the DCM boost-type ICS cell depends on the switching frequency rather than the duty ratio, it is possible to regulate the bulk capacitor voltage by a variable-frequency control. Clearly speaking, for the ICS cell op-erating in DCM with a constant duty ratio, the average input power is inversely proportional to the switching frequency, and the unbalanced power between the input and output decreases with the increase of switching frequency. The drawback of this approach is that large load variation range results in large range of variation in switching frequency. For a load change from 10% to full load, the switching frequency has to be 10 times that of the full load to re-main the same bulk capacitor voltage. Such wide switching frequency variation has problems such as low conversion efficiency and difficulty in the optimal design of transformers and in-ductors.
2.3.2 Bulk Capacitor Voltage Feedback Concept
Fig 2.10 shows the modified BIFRED (Boost Integrated with Flyback Rectifier/Energy Storage/DC-DC converter) converter with the bulk capacitor voltage feedback [33]. In the modified scheme, an additional transformer winding N1 is inserted in series with the boost inductor. The winding can feedback the bulk capacitor voltage when the boost inductor is charged, and the feedback depth depends on the bulk capacitor voltage level. The feedback depth will increase when the bulk capacitor voltage has an increasing trend. Thus, the input power can be automatically reduced to guarantee the balance between input and output aver-age power. As a result, the bulk capacitor voltaver-age is limited within a proper range.
Fig. 2.10 BIFRED converter with bulk capacitor voltage feedback [33].
2.3.3 Parallel Power Processing
To reduce extra bulk capacitor voltage stress and extra switch current stress, a parallel power factor correction (PPFC) approach has been proposed [22]-[28]. The main advantage of this type of design is the clamped or slightly boosted bulk capacitor voltage since partial input power is processed only once and directly delivered to the output load rather than stored in Cb. The configuration shown in Fig. 2.11 is an example circuit [24], in which the additional fly-back transformer Tr1 is used to replace most functions of the boost inductor in a conventional S2ICS AC-DC scheme and provide a path for direct power transfer. This scheme can be ap-plicable to converters with wide input voltage and load ranges. However, the two transformers (Tr1 and Tr2) with similar size and complex circuit structure make this topology less attractive
in low power applications, for which cost and size are often the dominant concerns.
Fig. 2.11 Example circuit with parallel power processing [24].
2.3.4 Both Functional Blocks Operate in the Same Mode
As discussed in subsection 1.1.2, power imbalance between the input and the output in the operation combination of DCM ICS + CCM DC-DC will cause high voltage stress on the intermediate bulk capacitor. However, there is no high bulk capacitor voltage stress problem in the combinations with the same operating mode, either in DCM or in CCM for the two cells [33]. Taking the example of DCM ICS + DCM DC-DC, the duty ratio will automatically decrease while the load becomes light, as shown in Fig. 2.12. As a result, the average input power also decreases due to the decrease of duty ratio. The excess input energy reduces ac-cordingly and the bulk capacitor voltage can be suppressed [51].
The technique of operating both functional blocks in the same mode is a practical and useful solution. However, the combination of DCM ICS + DCM DC-DC causes a low effi-ciency because of higher conduction loss and turn-off switching loss; the combination of CCM ICS + CCM DC-DC has relatively lower PF and higher distortion in input current as well as the larger boost inductor.
Fig. 2.12 Relationship between the average input power, average output power, and duty ratio for DCM ICS + DCM DC-DC [33].
2.4 Trend and Challenges
For AC-DC conversion, although unity PF is the ideal objective, it is not necessary to meet today’s regulations with unity PF. For example, both IEC 555 and IEC 61000-3-2 allow the presence of harmonics in the line current [1]-[4]. This fact opens the door for the com-promise techniques between quality and cost, which are capable of overcoming the above is-sues. Thus, to sum up briefly, the design optimization of a S2ICS circuit needs to meet the following objectives:
(1) The input current harmonics must meet the IEC 61000-3-2 Class D specifications;
(2) The S2ICS converter should have low bulk capacitor voltage stress in order to mini-mize the component ratings;
(3) The circuit structure should be simple to maintain lower cost for this converter than it is with the two-stage approach;
(4) The converter should have low switch current stress and good efficiency as well as keep Vb below 450 V in a wide line voltage range.
In summary, the major challenges of the S2ICS research includes meeting current
har-monic specifications, limiting bulk capacitor voltage stress, reducing switch current stress, dealing with the universal-line input voltage range, all with minimum additional cost. How to understand, analyze, optimize and improve these S2ICS converters has been a very interesting
har-monic specifications, limiting bulk capacitor voltage stress, reducing switch current stress, dealing with the universal-line input voltage range, all with minimum additional cost. How to understand, analyze, optimize and improve these S2ICS converters has been a very interesting