CHAPTER 3. ANALYSIS OF THE PROPOSED ICS TECHNIQUES AND
3.7 Comparison of the Two Proposed AC-DC Flyback Converters
To evaluate the impact of Lb, we compare the performance of the two proposed flyback converters shown in Figs. 3.3 and 3.16, respectively, in the same input voltage range (90–130 Vrms). The measured data including the bulk capacitor voltage and conversion efficiency are shown in Fig. 3.22. From Fig. 3.22(a), it can be found that the use of Lb is favorable to sup-press the voltage stress across Cb. This is because Lb can resist iLb to charge Cb and thus
the conversion efficiency. The reason is explained as follows. When Lb is used, the bulk ca-pacitor voltage becomes lower so that the duty ratio must increase to maintain constant output voltage and thus the power loss on main switch increases too. Even though using Lb can lower the current flowing through N1 and thus decrease the recycling power. Experimental results shown in Fig. 3.22(b) reveal that the power consumption on active components has more sig-nificant effect on conversion efficiency.
0 50 100 150 200 250
90 100 110 120 130
Vac (Vrms)
Vb (Volt)
Proposed Flyback with Lb Proposed Flyback without Lb
86.5 87 87.5 88 88.5 89 89.5 90 90.5 91 91.5 92
90 100 110 120 130
Vac (Vrms)
Efficiency (%)
Proposed Flyback with Lb Proposed Flyback without Lb
(a) (b) Fig. 3.22 Comparison of the performance of two proposed flyback converters: (a) bulk
ca-pacitor voltage and (b) conversion efficiency.
Moreover, since the design without Lb is characterized by the rapidly rising Vb, it is sug-gested being operated in the applications with narrow input voltage range. The converter can be designed to be operated in low line input (90–135 Vrms) or high line input (180–260 Vrms) by properly adjusting the turns ratio n1/n3. Furthermore, since the boost inductor used in the conventional ICS cell is saved, it is possible to achieve higher power density in this converter.
3.8 Concluding Remarks
In this chapter, a novel ICS technique for single-stage AC-DC converters has been in-troduced. The detailed steady-state behavior of flyback-type implementation with the special ICS function has been studied and analyzed with performance characteristics. It has been
shown that by employing the proposed ICS technique, two key advantages are obtained. First, the ICS cell of the proposed converter is charged in the duty-off time so that the current stress across the main switch is alleviated. Second, the effective duty ratio of the ICS cell is modu-lated by the instantaneous line voltage. This yields the result that the average charging current of the boost inductor can effectively compensate the modulation effect of the boost inductor discharging time. Consequently, a nearly linear relationship between the line current and voltage through the conduction interval is achieved.
Owing to the ability to draw a near-sinusoidal line current waveform while keeping Vb
below a desirable value (Vb < 450 V), the proposed ICS technique is suitable for the universal line voltage applications (90–260 Vrms). Moreover, the design procedure for selecting the minimum n1/n3 has been presented to comply with the IEC 61000-3-2 Class D requirements.
Using the selected n1/n3 ratio, the maximum conversion efficiency of 91.3% can be obtained at full load. Experimental results have demonstrated the proposed line current correction func-tion by a well shaped current waveform and the low current harmonics complying with re-quirements of IEC 61000-3-2 Class D. Furthermore, the high conversion efficiency has veri-fied the effectiveness of the switch current stress alleviation and soft-switching function.
CHAPTER 4
ANALYSIS AND PERFORMANCE OF THE PROPOSED AC-DC FLYBACK-FORWARD CONVERTER
In general, for a conventional two-stage PFC converter, the input current waveform and the bulk capacitor voltage are well regulated. However, in the S2ICS converters, the compro-mise between the input current harmonics, bulk capacitor voltage stress and overall conver-sion efficiency becomes a very critical issue. A good design of the S2ICS converter must find a careful trade-off among them. This chapter is going to provide an advanced S2ICS design with the consideration for suppressing the bulk capacitor voltage stress and improving con-verter efficiency.
4.1 Analysis of the Proposed Converter
4.1.1 Circuit Derivation
Based on the literature review described in Section 2.3, it can be found that the approach of operating the DC-DC cell in DCM is the most effective and simplest since the addition of extra coupled winding or external circuits is not needed. However, the resulting high RMS current requires a high current-rating switch and reduces the efficiency, as compared with the CCM DC-DC design. This feature is particularly unfavorable for low-voltage high-current applications. To remedy the above drawback, a special combination of the flyback and for-ward topologies shown in Fig. 4.1 is adopted here [52]. This flyback-forfor-ward converter is used as the DC-DC cell in the proposed single-stage design. Moreover, the flyback and for-ward sub-converters are designed to operate in CCM and DCM, respectively. The design ob-jective is to deactivate the flyback sub-converter and keep the forward sub-converter
provid-ing the output power when the converter operates in the light load condition. Thus, it is possi-ble to achieve high conversion efficiency in the heavy load condition and suppress the bulk capacitor voltage stress in the light load condition.
Fig. 4.1 Basic flyback-forward converter [52].
4.1.2 Circuit Configuration
Fig. 4.2 shows the circuit configuration of the proposed single-stage AC-DC converter.
This converter is derived from a center-tapped flyback-forward converter with the addition of the auxiliary circuit. The auxiliary circuit forms the ICS cell and the center-tapped fly-back-forward converter forms the DC-DC cell. In the proposed converter, a multi-winding transformer Tr is employed. It includes four windings N1, N2, N3, and N4 with turns number n1, n2, n3, and n4, respectively, and the primary magnetizing inductance Lm. As marked by the shaded area in Fig. 4.2, the ICS circuit, consisting of the rectifier diode D1, boost inductor Lb, and auxiliary winding N1, is inserted between the full-bridge rectifier Dr and the bulk capaci-tor Cb. The purpose of this circuit is to force the boost inductor current to be discontinuous and AC modulated to achieve inherent PFC. The diode D1 is used to provide fast rectification and prevent the filter capacitor Cin from being charged by the reverse current of iLb. Different from the conventional ICS schemes, bulk capacitor Cb is intentionally connected to the undot-ted end of winding N1. Through the winding N1 with enough large turns, the coupled voltage
4 1 n n Vo⋅
− across winding N1 can force to charge Lb during the duty-off time. Therefore, the
Fig. 4.2 Proposed single-stage soft-switching AC-DC converter.
The ICS cell is then followed by an active-clamp flyback-forward circuit which provides isolation and post-regulation function. Cr represents the sum of the parasitic capacitances con-tributed by main switch S1 and auxiliary switch S2. Lr represents the sum of the transformer leakage inductance and an external inductor, which forms a series resonant circuit with Cr to enable soft-switching function. The resonant inductor Lr, the clamping capacitor Cc, and the auxiliary switch S2 form the main part of the active-clamp circuit for limiting the turn-off voltage spike of S1. The combination of forward (primary and upper secondary of Tr) and fly-back (primary and lower secondary of Tr) circuits in a single unit by using a center-tapped transformer ensures that the energy is always transferred to the load even when the main switch S1 is turned off. Moreover, with the use of transformer Tr, the magnetization energy stored in Lm is split into two portions in duty-off time. One portion is directly delivered to the output load by the flyback sub-converter; the rest is delivered to the auxiliary winding N1 for generating iLb and charging the bulk capacitor Cb. In addition, the flyback sub-converter is de-signed to operate in CCM for providing a reflected voltage vN1 from the output voltage during the duty-off time. The forward sub-converter is designed to operate in DCM all the time even in light load condition while the flyback sub-converter is deactivated. Furthermore, the control circuit can be implemented by a simple control loop, a common PWM controller, and a driver circuit.
4.1.3 Principle of Operation
To simplify the analysis, the following assumptions are made:
(i) The switching and conduction losses of the components are neglected;
(ii) The rectified line voltage |vac| is considered constant during a switching period;
(iii) The bulk capacitor voltage Vb and the output capacitor voltage Vo are ripple-free DC in each half of a line cycle;
(iv) The leakage inductances of the transformer are neglected.
In each half line cycle, the converter has two operation modes, M1 and M2, as shown in Fig. 4.3. In mode M1, the rectified line voltage |vac| is lower than Vb −Vo⋅n1 n4; thus, diode D1 is reverse biased and no line current Iac is formed. In this circumstance, the converter sim-ply operates as an active-clamp flyback-forward DC-DC converter. While |vac| is higher than
4 1 n n V
Vb− o⋅ , the converter operates in mode M2, in which Lb can provide the voltage-boost function and thus the line current is established. From the definition of operation modes, the boundary angle θb between modes M1 and M2 can be obtained as
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛ − ⋅
= −
) (
4 1 1
sin
pk ac
o b
b V
n n V
θ V (4.1)
Furthermore, Fig. 4.4 illustrates that the topological states of the converter during one switch-ing period. Referrswitch-ing to the symbol definitions, topological states, and key waveforms shown in Figs. 4.2, 4.4, and 4.5, respectively, the detailed operation is explained as follows.
4 1 n n V Vb− o⋅
Fig. 4.3 Operation modes in a half line cycle.
(a) (b) (c)
Cb Lb
Cr S1
D2
iLr
|vac|
Lr
S2 Lm
Co Cc
Lo D3
D4
RL D1
(d) (e) (f)
Cb Lb
Cr S1
D2
iLr
|vac|
Lr
S2 Lm
Co Cc
Lo D3
D4
RL D1
(g) (h) (i)
(j) (k) (l) Fig. 4.4 Topological states of the proposed converter: (a) State 1 for mode M1, (b) State 1
for mode M2, (c) State 2, (d) State 3, (e) State 4, (f) State 5 for mode M1, (g) State 5 for mode M2, (h) State 6 for mode M1, (i) State 6 for mode M2, (j) State 7 for mode M1, (k) State 7 for mode M2, and (l) State 8.
M1
v
GS1v
GS2v
cri
D2i
Lbi
Lr1
State 2 5 7
i
S1v
ci
D4DTs t0 t1t2 t4
v
N23
t3
4
t6
i
Lmi
D3M2
v
GS1v
GS2v
cri
D2i
Lbi
Lr1
State 2 5 7
i
S1v
ci
D4t0 t1t2 t4 t6
v
N23
t3
4
t7
i
Lmi
D38
t8
Ds8Ts t7
DTs
6
t5
6
t5
(a) (b)
Fig. 4.5 Steady-state waveforms of the proposed converter in (a) mode M1 and (b) mode M2.
State 1 [Fig. 4.4(a) or 4.4(b), t0≤t<t1]:
In this state, switch S1 is on and switch S2 is off. From KVL, the bulk capacitor voltage Vb equals the sum of the voltage across resonant inductor Lr and the voltage across the pri-mary winding N2. The positive voltage across winding N2 induces a positive voltage across the secondary winding N3. Thus, the output inductor current flows through the diode D2 and di-odes D3 and D4 are reverse biased. Since Vb is approximately constant, both the magnetizing
inductance Lm and resonant inductor Lr are linearly magnetized. The voltage and current at the transformer primary side can be obtained as
m o shown in Appendix E. In this state, since the large positive voltage presents across winding N1, no current flows through Lb. the secondary side diodes D2 and D3 conduct and the output inductor current is decreasing linearly. The resonant tank in this state consists of Lr and Cr. Solving the resonant network gives the current and voltage as
( ) ( ) ( ( ) ) ( ) (
1(
2At t3, vCr rises to a value that makes the body diode of S2 conduct. Since the clamp ca-pacitor Cc is much greater than the resonant capacitor Cr, the resonant tank primarily consists of Lr and Cc. Solving the resonant network yields
Consequently, the diode current iD2 keeps decreasing till iD2 = 0 and contrarily the diode cur-rent iD3 increases until iD3 = iLo. Before iD2 decreases to zero, the primary side voltage vN2 is still kept zero value.
State 5 [Fig. 4.4(f) or 4.4(g), t4 ≤t <t5]:
At t4, iD2 = 0 and iD3 = iLo. After time t4, the fast varying current iLr decreases to a value that is smaller than iLm; thus, the winding current iN2 turns to negative. According to Ampere’s law, the winding current iN4 will be induced correspondingly. The fact that diode D4 conducts results in the voltage vN2 being clamped at −Vo⋅n2 n4. Shortly, S2 is turned on before iLr
resonates to the negative direction; thus, ZVS of S2 is achieved. The resonant tank is formed by Lr and Cc. The resonant inductor current and clamp capacitor voltage can be found as
( ) ( ) ( ( ) ) ( )
mode M2 operation, the current iLb will be generated and is given by( ) ( ) (
4re-duces to zero, this state is ended. Meanwhile, the DCM operation of Lo is achieved and D2 and D3 are reverse biased.
State 6 [Fig. 4.4(h) or 4.4(i), t5 ≤t<t6]:
This circuit analysis in this state is the same as that in State 5 except the output inductor current is zero.
State 7 [Fig. 4.4(j) or 4.4(k), t6 ≤t<t7]:
At t6, S2 is turned off. Cc is disconnected and Lr and Cr form a new high frequency reso-nant circuit. The transformer primary side current iLr resonates in the negative direction to discharge Cr; therefore, vCr decreases from vc(t6)+Vb to zero and then vN2 turns to positive. At t7, iD4 decreases to zero and after then D4 becomes reverse biased. Since the down-slope of diD4/dt is determined by the resonant speed, D4 can be designed to switch softly to reduce the rectifier switching loss. The resonant inductor current and resonant capacitor voltage can be expressed as
( ) ( ) ( ( ) ) ( )
For the mode M2 case, the current iLb is increasing linearly with the same slope as expressed in (4.12).
State 8 [Fig. 4.4(l), t7 ≤t<t8]:
At t7, the body diode of S1 begins to conduct. Shortly after time t7, while the body diode of S1 is conducting, S1 is turned on to achieve ZVS operation. Since |vac| is smaller than vN1+Vb, the boost inductor current iLb linearly decreases and becomes zero at time t8 ( = t0 ). The above operation gives
( ) ( )
7 1,7(
t t7where
The derivation of (4.16) is shown in Appendix F. It is worth mentioning that the output power is fed directly from the line input by the utilization of winding N1 in this state. In addition, when the converter operates in mode M1, this state does not exist.
4.1.4 Steady-State Analysis
Based on the circuit analysis of the proposed converter introduced in the previous sub-section, States 2-4 and 7 can be neglected in the steady-state analysis because these four in-tervals are very short as compared with the total switching period. By employing the volt-age-second balance across Lm, one can obtain the following equation.
( ) (
1)
2,7 8 0Similarly, by employing the voltage-second balance across Lr and neglecting the small oscil-lation term of Vc, one can obtain
Also, the voltage-second balance across Lb gives
(
1)
2,7 8 0According to (4.19), the time function of Ds8 in mode M2 is obtained as
Adding (4.17) to (4.18), the clamp capacitor voltage can be expressed as
b According to (4.18) and (4.21), the clamp capacitor voltage in mode M2 can be further ex-pressed as
( ) ( )
Thus, from (4.22) and (4.23), the time function of the duty ratio in mode M2 is given by
( ) ( )
So far, the steady-state analysis for the full load condition has been carried out. The steady-state analysis for the light load condition is then derived as follows.
When the output load decreases, the DC-DC cell of the proposed converter degenerates to an active-clamp forward circuit. Due to the DCM operation of Lo, one can obtain
( )
where iLo(pk) is the peak current of output inductor. By employing the voltage-second balance across Lm and neglecting the small oscillation term of vN2 in State 5, one can obtain the fol-lowing equation.
(
8)
2,4(
1)
2,7 8 0Similarly, the voltage-second balance across Lr gives
(
Vb −vN2,t0)
⋅(
D−Ds8)
−(
Vc+vN2,t4)
⋅(
1−D)
+(
Vb −vN2,t7)
⋅Ds8 =0. (4.27) And the voltage-second balance across Lb gives(
1)
2,7 8 0Adding (4.26) to (4.27), the clamp capacitor voltage can be found as (4.22). From (4.26), one can obtain
( )
Substituting (4.29) and (4.30) into (4.28), Ds8 can be obtained as
( )
4.2 Design Considerations
The design specifications of the proposed converter are given as follows: the input volt-age range Vac = 90–260 Vrms (60 Hz), output voltage Vo = 20 V, rated output power Po = 100 W, and switching frequency fs = 100 kHz. To maximize the conversion efficiency, the duty ratio range is designed to from 0.15 to 0.4. The conversion efficiency η is assumed to be 0.85.
With the consideration of the voltage limitation of a commercially available electrolytic
according to the empirical rule, the moderate value of Vb usually ranges between 1.1 and 1.2 times as high as Vac(pk). However, when Vac = 260 Vrms, the possible maximum value of Vb
equals 260× 2×1.2=441 and the value extremely approaches 450 V. Therefore, in the following design, the target maximum value of Vb, Vb,max, is chosen to be 1.15 time as high as Vac(pk) at 260 Vrms line input. To ensure the proposed converter operating properly, the con-verter parameters including n2/n3, n2/n4, n1/n4, Lr, Lm, Lo, and Lb are determined as follows.
(1) Determining the Turns Ratio n2/n3
Let , thus the voltage vN2,t0 is approximated to be Vb. By using the voltage con-version ratio theory of the simple forward circuit operating in CCM, the primary to secondary turns ratio n2/n3 can be approximately expressed as
r
m L
L >>
o b
V D V n
n ,min max
3
2 = . (4.32)
(2) Determining the Turns Ratio n2/n4
The proposed converter is designed to operate the forward sub-converter in DCM and flyback sub-converter in CCM. With this design, the bulk voltage can be easily suppressed in the worse case, i.e. the high line input with light load condition, by deactivating the flyback sub-converter. The above function can be achieved by manipulating the voltage of Vc. In the high line with light load case, since D becomes smaller, lower Vc and –vN2 will be formed.
Thus, the induced voltage across N4, –vN4, can be designed to be insufficient to forward bias D4 so that the flyback sub-converter is deactivated. Based on the above concept, the following condition must be satisfied.
o
c n n V
V,min⋅ 4 2 < . (4.33) By substituting (4.22) into (4.33), the ratio of n2/n4 can be found:
min
(3) Determining the Turns Ratio n1/n4
The design objective of determining n1/n4 is to find its minimum value with which the input current harmonics can meet the IEC 61000-3-2 Class D requirements. According to (4.1), the selection of n1/n4 is equivalent to the selection of the boundary angle. Thus, the design ob-jective becomes finding the maximum acceptable boundary angle. Since IEC 61000-3-2 Class D gives the requirements of the acceptable harmonics, to find the maximum acceptable boundary angle, each input current harmonic should be computed. Since the line current is an analogous sinusoid waveform, the line current during [θb, π–θb] can be expressed as
( ) ( )
⎟⎟ where ω is the angular frequency of the line voltage. Thus, the nth harmonic component In can be calculated by Fourier analysis:( )
where n = 1, 3, 5...39. Since the Class D limits are defined as the ratio of the current harmonic to fundamental-frequency component, In/I1. From (4.36), we can obtain the normalized value of each harmonic as a function of the boundary angle as drawn in Fig. 3.10. Fig. 3.10 shows that the most critical harmonic is the fifth for complying with the Class D requirements since its acceptable boundary angle is smaller than all the others. Therefore, the maximum allow-able boundary angle is 1.005 rad ( = 57.58o). Next, the turns ratio n1/n4 can be obtained by re-arranging (4.1):
o In the proposed converter, a higher line input voltage causes a larger boundary angle. Thus, we must make sure that the design satisfies the requirements of the Class D especially at the nominal high line input, that is 230 Vrms. Substituting Vb = 1.15．Vac(pk) in (4.37), we obtain n1/n4 = 4.97 when Vac = 230 Vrms and θb = 1.005 rad. In other words, n1/n3 = 4.97 is the boundary of compliance with Class D limits.
(4) Determining the Resonant Inductor Lr
According to the operating principle of State 7, to ensure the ZVS turn-on for S1, the en-ergy stored in the resonant inductor Lr must be greater than the energy stored in the resonant capacitor Cr. Thus, for the given Cr contributed by the parasitic capacitances of S1 and S2, the following relationship should be guaranteed.
(
1, 1( )
6)
2(5) Determining the Transformer Primary Magnetizing Inductance Lm
With the design consideration that the flyback sub-converter is deactivated at high line and light load condition, the output power provided by the sub-converter at 260 Vrms and full load situation is designed to be lower than Po/2. Meanwhile, this sub-converter is designed to always operate in CCM at full load. Thus, the inductance Lm must satisfy the following condi-tion:
(6) Determining the Output Inductor Lo
According to the design criterion mentioned above, the output power provided by the forward sub-converter at 260 Vrms should be greater than Po/2. To fulfill this design and en-sure that Lo always operates in DCM, the following relationship should be guaranteed.
⎟⎟
(7) Determining the Boost Inductor Lb
To achieve the self-PFC property, the boost inductor must operate in DCM over the en-tire line cycle. Thus, the design must satisfy the condition of Ds8 < D in the whole line cycle.
To achieve the self-PFC property, the boost inductor must operate in DCM over the en-tire line cycle. Thus, the design must satisfy the condition of Ds8 < D in the whole line cycle.