Concluding Remarks

A review of existing S²ICS AC-DC converters is given in this chapter. For further com-paring the system configuration and characteristics of the familiar S²ICS converters, we summarize the classification of the representative reported single-stage circuits as shown in Table 2.1.

In addition, main issues such as high current stress, high voltage stress and low conver-sion efficiency in current S²ICS AC-DC approaches are also presented and discussed in this chapter. To alleviate switch current stress, a new ICS technique is presented in Chapter 3. The proposed ICS scheme not only alleviates switch current stress in the duty-on time, but also provides a well current shaping function. Moreover, to suppress bulk capacitor voltage stress, a hybrid operated DC-DC converter is adopted in Chapter 4. This circuit can simultaneously achieve two functions including bulk capacitor voltage suppression while light load and high conversion efficiency while heavy load.

Table 2.1 Classification of the representative reported S²ICS converters Basis of classification Category Representative Circuits

Cascade [15], [31], [32]

Power processing structure

Parallel [22]-[28]

2-terminal [20], [29], [30]

Topology configuration of ICS cell

3-terminal [21], [23]-[28], [31]-[41]

DCM [15], [21]-[23], [25]-[35], [51]

Input boost inductor current waveform

CCM [24], [36]-[41]

CS-S²ICS [36]-[39]

Topology configuration of

ICS cell VS-S²ICS [40], [41]

CHAPTER 3

ANALYSIS OF THE PROPOSED ICS TECHNIQUE AND THE APPLICAION TO FLYBACK CONVERTERS

For the single-stage designs with boost-type ICS cells, the line current actually being the average (or filtered) boost inductor current is composed of two components. The average charging current of the boost inductor has linear relation to the instantaneous line voltage, while the average discharging current of the boost inductor primarily has a quadratic charac-teristic against the instantaneous line voltage. Thus, the resultant input i-v characcharac-teristic curves are nonlinear as shown in Fig. 3.1(a) and the corresponding line currents have the de-formed shapes as shown in Fig. 3.1(b), where M represents the ratio of the bulk capacitor volt-age Vb to the peak line voltage Vac(pk). To improve this drawback, it is found that Vb should be designed to be as high as possible [11]. However, this will produce high voltage stress on the switch and the bulk capacitor. To remedy the problems described above, the charging time of the boost inductor in the proposed converter is designed to be inversely modulated by the line voltage, so that the i-v curve of the average charging current presents an opposite deformation characteristic to that presented by the i-v curve of the average discharging current. Conse-quently, the line current has the waveform analogous to the line voltage waveform.

In addition, since the ICS cell and DC-DC cell are driven by one common switch, both the boost inductor current and the transformer current simultaneously flow through the switch in the duty-on time, as shown in Fig. 3.2(b). As a result, the switch current stress is relatively high when compared with the conventional two-stage scheme. High current stress not only accompanies with increased power loss, but also brings about annoying EMI issues. To over-come this drawback, we adopt the concept of “interleaved operation” in the design of

sin-gle-stage AC-DC converters. Unlike the conventional sinsin-gle-stage designs, the proposed ICS scheme is intentionally arranged to be charged in the duty-off time, as shown in Fig. 3.2(c).

With this design, the switch current stress in the duty-on time can be significantly reduced and correspondingly conduction loss can be relieved. This special ICS function can be imple-mented by using the technique of multi-winding of power transformer.

0 0.2 0.4 0.6 0.8 1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Normalized line current amplitude

Normalized line voltage amplitude

0 0.5 1 1.5 2 2.5 3

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Normalized line current amplitude

Line angle (rad)

(a) (b) Fig. 3.1 The line current distortion caused by the modulation effect of the boost inductor

discharging time, where M = Vb/Vac(pk) and the dead angle of the line current is considered: (a) the input i-v characteristic curves and (b) the corresponding line current waveforms.

On the other hand, the common drawback of using the single-stage circuits is that the switching components often suffer from the relatively high voltage and current stress during switching, which increases the component rating and introduces more switching loss too. To further improve the performance of the proposed single-stage AC-DC converter, an ac-tive-clamp circuit with zero-voltage-switching (ZVS) function is added to the adopted con-verter. This circuit can lead to noticeable improvement on voltage spikes across the switches and significant reduction of electromagnetic noise generation [42]-[48].

Fig. 3.2 Comparison of switch current stress: (a) PWM control signal of the switch, (b) switching current waveforms of the conventional ICS scheme and (c) switching current wave-forms of the proposed ICS scheme.

3.1 Analysis of the Proposed Converter

3.1.1 Circuit Derivation and Configuration

Fig. 3.3 shows the circuit configuration of the proposed single-stage AC-DC converter.

The proposed converter is based on a conventional active-clamp DC-DC converter with skilled modification in order to satisfy harmonic regulations and cost-effective consideration.

In this converter, a multi-winding transformer Tr is employed. It includes three windings N1, N2, and N3 with turns number n1, n2, and n3, respectively, and the primary magnetizing induc-tance Lm. As shown in Fig. 3.3, the converter contains an ICS cell, mainly composed of the rectifier diode D1, boost inductor Lb, winding N1, and resonant inductor Lr. The diode D1 is used to provide fast rectification and prevent the filter capacitor Cin from being charged by the reverse current of iLb. It is worth mentioning that the proposed converter has a special ICS

de-sign in which the undotted end of winding N1 is intentionally connected to node X instead of node Y. There are two objectives for this design: charging the boost inductor in the duty-off time and reducing the size of the boost inductor. Through the winding N1 with enough large turns, the voltage vN1 can force to charge Lb during the duty-off time since vN1 turns to nega-tive. Therefore, only the transformer current flows through the main switch S1 in the duty-on time and correspondingly the switch current stress can be reduced. Meanwhile, the resonant inductor Lr is arranged in the charging path of Lb so that Lr and Lb can provide the volt-age-boost function together. Consequently, a small inductance for Lb is sufficient to achieve the DCM operation and it can be implemented by either an external inductor or leakage in-ductance of the transformer.

The ICS cell is then followed by an active-clamp DC-DC circuit which provides isolation and post-regulation function, as defined by the dotted-line box in Fig. 3.3. The DC-DC cell is designed to operate in CCM and can be implemented by a flyback or forward circuit. Cr

represents the sum of the parasitic capacitances of main switch S1 and auxiliary switch S2. Lr

represents an external inductor, which forms a series resonant circuit with Cr to enable soft-switching function. The resonant inductor Lr, the clamping capacitor Cc, and the auxiliary switch S2 form the main part of the active-clamp circuit for limiting the turn-off voltage spike of S1.

The control circuit can be implemented by a simple control loop, a common PWM con-troller, and a driver circuit. Moreover, main and auxiliary switches are driven complementary with small dead time in between to allow for ZVS.

Fig. 3.3 Proposed single-stage soft-switching AC-DC converter.

3.1.2 Principle of Operation

In this subsection, the detailed operation of a flyback-type implementation with the pro-posed ICS scheme is introduced. To simplify the analysis, the following assumptions are made:

(i) The switching and conduction losses of the components are neglected;

(ii) The rectified line voltage |vac| is considered constant during a switching period;

(iii) The bulk capacitor voltage Vb and the output capacitor voltage Vo are ripple-free DC in each half of a line cycle;

(iv) The leakage inductances of the transformer are neglected;

(v) An external inductor is employed for Lb.

According to the instantaneous magnitude of the rectified line voltage |vac|, the operation of the converter can be divided into two modes during a half line cycle, as shown in Fig. 3.4.

When |vac| is smaller than the boundary voltage VBD, the converter operates in mode M1, and during the remaining time it operates in mode M2. Fig. 3.5 illustrates that five topological states exist in a switching period. Referring to the symbol definitions, topological states, and key waveforms shown in Figs. 3.3, 3.5, and 3.6, respectively, the detailed operation is

ex-plained as follows.

Fig. 3.4 Operation modes in a half line cycle.

(a) (b) (c)

(d) (e) (f)

Fig. 3.5 Topological states of the proposed converter based on flyback topology:

(a) State 1, (b) State 2, (c) State 3 for mode M1, (d) State 3 for mode M2, (e) State 4, and (f) State 5.

v

_GS1

v

_GS2

v

_DS1

i

_N3

i

N1

i

_Lr

t0 t1 t2 t3t4

M1 M2

t5

1

State 2 3 4 5

i

_S1

v

_DS2

v

_c

i

Lm

v

_GS1

v

_GS2

v

_DS1

i

_N3

i

N1

i

_Lr

1

State 2 3 4 5

i

_S1

v

_DS2

v

_c

i

Lm

1

D_s5Ts

DTs DTs

D_s5Ts

t₀ t1 t2 t3t4 t5

v

_N2

v

_N2

(a) (b)

Fig. 3.6 Steady-state waveforms of the proposed converter in (a) mode M1 and (b) mode M2.

State 1 [Fig. 3.5(a), t₀≤t<t₁]:

At t0, S1 is on and S2 is off. The output rectifier D2 is reverse biased. Both Lm and Lr are linearly magnetized as operating in a conventional flyback converter. This current flowing

( ) ( ) ( ) ( )

₀

(

^{t t}₀ current flowing through Lb is zero.

State 2 [Fig. 3.5(b), t₁ ≤t<t₂]: dura-tion, the transformer secondary voltage vN3 is sufficient to forward bias D2. Therefore, the transformer primary voltage vN2 is clamped at −V_o⋅n₂ n₃. Shortly, S2 is turned on before ip

resonates to the negative direction; thus, ZVS of S2 is achieved. In mode M1, the line voltage is not large enough to generate iLb; thus, the resonant tank only includes Lr and Cc when ne-glecting the small Cr. The voltage and current along the resonant loop can be obtained by

( )

^{t i}

( )

^{t A}₁ ^cos

(

₁

(

^{t t}₂

) )

^B₁ ^sin

(

₁

(

^{t t}₂

) )

More concisely,

( )

^{t =C}₁^⋅cos

(

^ω₁

(

^t−t₂

)

^−ϕ₁

)

i_P (3.6)

and by the secondary winding N3, so the magnetizing current iLm decreases linearly as given by

( ) ( ) (

₂ And by employing Ampere’s law, we can obtain that

3 0 Moreover, according to Fig. 3.3, the primary winding current iN2 can be obtained by

( )

t i

( )

t i

( )

t

i_N2 = _P − _Lm . (3.10) Employing (3.9), one can find the secondary winding current in mode M1:

( )

i

( )

t In mode M2, the line voltage is higher than the boundary voltage VBD and causes the cur-rent iLb to be generated. Therefore, the resonant tank is formed by Lr, Lb, and Cc. In such a de-sign, the negative vN1 results in a partial energy of Lm being sent back to Cb through winding N1. According to the topological state shown in Fig. 3.5(d), we obtain

( )

^{t = A}₂^⋅cos

(

^ω

(

^t−t₂

) )

^+B₂^⋅sin

(

^ω

(

^t−t₂

) )

^=C₂^⋅cos

(

^ω

(

^t−t₂

)

^−ϕ₂

)

(3.13)

The detailed derivation of the above equations is shown in Appendix A. So far, by ap-plying the operating principle obtained in State 3, the average charging current of the boost inductor in one switching period can be calculated. First, the boost inductor current iLb can be expressed as

( ) ( ) ( ) ( ( )

_⎥ where Po is the output power. The detailed derivation of (3.15) is shown in Appendix B. By integrating (3.14) through the duty-off time and then dividing (3.14) by Ts, the average charg-ing current of the boost inductor over one switchcharg-ing period is given by

( ) ( ) ( ) (

_⎥

em-ploying (3.9): Employing KCL, the current iLr can be obtained as

( ) ( ) ( ) ( ) ( )

_⎥ neighboring oscillation intervals of States 2 and 4 are very short as compared to the switching period.

State 4 [Fig. 3.5(e), t₃ ≤t <t₄]:

At t3, S2 is turned off. Cc is disconnected and Lr, Lb, and Cr form a new high frequency resonant circuit. The transformer primary side current ip resonates in the negative direction to discharge Cr; therefore, vDS1 decreases from vc(t3)+Vb to zero. Within this state, vN2 turns to positive and results in D2 being cut off. Since the down-slope of diN3/dt is determined by the resonant speed, D2 can be designed to switch softly to reduce the rectifier switching loss.

Based on the operations shown in Fig. 3.5(e), we can obtain

( )

t =A₃⋅cos

(

ω₃

(

t−t₃

) )

+B₃⋅sin

(

ω₃

(

t−t₃

) )

=C₃⋅cos

(

ω₃

(

t−t₃

)

−ϕ₃

)

r

And the details of the above equations are shown in Appendix C. In this duration, iN2 and iN3

have the same expressions as (3.10) and (3.17), respectively. Besides, iLm is given by

( ) ( ) (

₃ Integrating the voltage across Lr yields

( ) ( ) ( ) ( )

Subtracting (3.22) from ip yields

( ) ( ) ( ) ( ( ) )

It should be noted that, for mode M1, the current iLb is built up only in this short interval.

Thus, the induced input current is much smaller than that induced in mode M2. State 5 [Fig. 3.5(f), t₄ ≤t<t₅]:

At t4, the body diode of S1 begins to conduct. Shortly after time t4, while the body diode of S1 is conducting, S1 is turned on to achieve ZVS operation. The bulk capacitor voltage Vb, much higher than vN2, causes iLr to increase linearly. Simultaneously, since |vac| is smaller than vN1+vN2, the boost inductor current iLb linearly decreases and becomes zero at time t5 ( = t0 ).

The above operation gives

( ) ( )

₄

( )

¹

( )

²

( ) (

t t₄ The derivation of (3.25) is shown in Appendix D. It is worth mentioning that the output power is fed directly from the line input by the utilization of winding N1 in this state. By integrating (3.24) through the Ds5Ts interval and then dividing (3.24) by Ts, the average discharging cur-rent of the boost inductor over one switching period is given by

( ) ( )

3.1.3 Steady-State Analysis

Based on the circuit analysis of the proposed converter introduced in subsection 3.1.2, States 2 and 4 can be neglected in the steady-state analysis because these two intervals are very short as compared with the total switching period. By employing the voltage-second balance across Lm, one can obtain the following equation:

( ) (

1

)

_{2 5} 0

Similarly, the voltage-second balance across Lr gives

( ) (

¹

) (

₂

)

₅ ⁰

In mode M1, since the Ds5 is very small and can be neglected in the circuit analysis, the duty ratio in mode M1 can be obtained from (3.28):

o

Adding (3.28) to (3.29), the clamp capacitor voltage in mode M1 can be derived as

b Moreover, according to (3.13), we can obtain the approximated expression of the clamp ca-pacitor voltage in mode M2 by neglecting the small oscillation term:

( ) ( )

_⎟⎟

Substitute (3.32) into (3.29) to replace Vc; thus, the addition of (3.28) and (3.29) yields

( )

V

(

D

In addition, the boundary between modes M1 and M2 occurs just as |vac(t)| is large enough to charge the boost inductor during State 3. Thus, from Figs. 3.5(c) and 3.5(d) and KVL, the

boundary voltage of modes M1 and M2, VBD, is determined by The boundary angle θb shown in Fig. 3.4 can be calculated from (3.36):

⎟⎟

where |Vac(pk)| is the peak rectified line voltage.

3.2 Design Considerations

The design specifications of the proposed converter are given as follows: input voltage range Vac = 90–260 Vrms (60 Hz); output voltage Vo = 48 V; rated output power Po = 100 W;

switching frequency fs = 100 kHz; conversion efficiency η =0.85.

The bulk capacitor voltage Vb is dependent on the line voltage and the output load. Ac-cording to the empirical rule, the moderate value of Vb usually ranges between 1.1 and 1.2 times as high as Vac(pk). Moreover, to maximize the conversion efficiency, the duty ratio should be from 0.4 to 0.5 at low line since the low line is considered the critical case in this design.

To ensure the proposed converter operating properly, the converter parameters are determined as follows.

(1) Determining the Turns Ratio n2/n3

Let . By using the same operation theory applied to a simple flyback circuit operating in CCM, the primary to secondary turns ratio n2/n3 can be approximately obtained as

(2) Determining the Transformer Primary Magnetizing Inductance Lm

To ensure that the flyback cell always operates in CCM, the inductance Lm must satisfy the following condition:

( )

(3) Determining the Clamp Capacitor Cc

The resonant frequency determined by Cc and Lr should be sufficiently low so that the half resonant period π L_rC_c is greater than the duty-off time. Thus, the minimum value of Cc can be obtained as:

According to the design specifications and (3.38), (3.39) and (3.40), the parameters n2/n3, Lm, and Cc are selected as 2.3, 318.4 μH, and 0.22 μF, respectively. Furthermore, the other converter parameters with special function, including Lb and Lr, are determined as follows.

(4) Determining the Boost Inductor Lb

To achieve self-PFC, the boost inductor must operate in DCM over the entire line cycle.

Thus, the design must satisfy the condition of Ds5 < D in the whole line cycle. Since the criti-cal boundary condition of CCM and DCM occurs at the lowest peak input voltage, the maxi-mum boost inductance can be determined from (3.35):

1

where

Vac=90 Vrms, Lr=25uH, n2/n3=2.3

Fig. 3.7 The maximum boost inductance Lb,max versus turns ratio n1/n3.

(5) Determining the Resonant Inductor Lr

According to the operating principle of State 4, to ensure the ZVS turn-on for S1, the en-ergy stored in the parallel of resonant inductor Lr and boost inductor Lb must be greater than the energy stored in the resonant capacitor Cr. Thus, for the given Cr contributed by the para-sitic capacitances of S1 and S2, the following relationship should be guaranteed:

( ( ) ) ( ( ) )

3.3 Analysis of the Line Current Waveform

As shown in Fig. 3.3, the low pass filter Lf–Cf will filter out the switching frequency components and harmonics of iLb. Thus, the rectified line current |iac(t)| is the average value of iLb(t) within a switching period, namely, |iac| = iLb,ch(ave) + iLb,dis(ave). Moreover, the expression of iLb,dis(ave) in (3.27) can be rearranged as follows by substituting (3.35) into (3.27):

( ) ( ( ) )

plotted in Fig. 3.8, in which only mode M2 is considered. Moreover, based on (3.34) and (3.35), the curves of and Ds5 for mode M2 can be drawn in Fig. 3.9. These curves are sketched by using the following parameters: Lr = 27.5 μH, Lb = 10 μH, Lm = 318.4 μH, n1: n2: n3 = 2.3: 2.3: 1, Vac = 110 Vrms, Vb = 1.15．Vac(pk), Ts = 10 μs, Vo = 48 V, and Po = 100 W.

Although the determination of turns ratio n1/n3 is somewhat arbitrary at present, the detailed selection criterion of n1/n3 will be discussed in the next section for satisfying the harmonic requirements.

(

1−D

)

As shown in Fig. 3.8(a), the i-v curve of iLb,ch(ave) can be designed to bend convexly while that of iLb,dis(ave) still bends concavely. Since these two bent curves have remarkable

compensa-tion to each other, the i-v curve of |iac| has very good linear characteristics. The special charg-ing mechanism of iLb,ch(ave) is explained as follows. When |vac(t)| increases, Ds5 also increases correspondingly. Moreover, the charging voltage of Lm in the Ds5Ts duration is smaller than that in the duration, as illustrated in Fig. 3.6(b). Smaller charging voltage pro-duces less magnetizing energy injected in Lm and consequently lower output voltage is formed.

To maintain the constant output voltage, the controller will increase the duty ratio D under output voltage feedback control. Thus,

(

D−D_s5

)

T_s

(

1−D

)

, or named the effective duty ratio of the ICS cell, will be inversely proportional to the instantaneous rectified line voltage with DC offset, as shown in Fig. 3.9. The AC modulation effect on

(

1−D

)

makes iLb,ch(ave)(t) convexly vary with |vac(t)|. The compensation produces a result in which the second derivative əiac2/ə²vac is very small and ranges between -1.1×10^-4 and 2.2×10^-4. This result shows that the relationship between |iac| and |vac| is nearly linear and can be expressed as

( )

terms nonlinear negligible

− +

=

eq BD ac

ac R

V

i v (3.44)

where Req is the equivalent input resistance. The linear result can be seen clearly from Fig.

3.8.

0 50 100 150

0 0.5 1 1.5 2 2.5

Voltage (V)

Current (A) |iac|

VBD

iLb,ch(ave)

iLb,dis(ave)

0 0.5 1 1.5 2 2.5 3

0 0.5 1 1.5 2 2.5

Line angle (rad)

Current (A)

(a) (b) Fig. 3.8 Comparison of iLb,ch(ave), iLb,dis(ave), and |iac| drawn by the proposed converter in a half

line cycle at 110 Vrms: (a) the currents as a function of instantaneous line voltage and (b) the current waveforms as a function of line angle.

0 0.5 1 1.5 2 2.5 3 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Line angle (rad)

Fig. 3.9

(

1−D

)

and Ds5 versus line angle for 110 Vrms in a half line cycle.

3.4 Designing the ICS Cell to Meet IEC 61000-3-2 Requirements

Equation (3.37) shows that a larger n1/n3 will cause a smaller boundary angle and lower current harmonics. However, a larger n1/n3 also causes more energy of Lm to redundantly cir-culate to Cb through winding N1. Thus, the design objective of determining n1/n3 is to find its minimum value with which the input current harmonics can meet the IEC 61000-3-2 Class D requirements. Note that since n2/n3 has been determined in Section 3.2, the selection of n1/n3 is equivalent to the selection of the boundary angle. Thus, the design objective becomes finding the maximum acceptable boundary angle.

Since IEC 61000-3-2 Class D gives the requirements of the acceptable harmonics, to find the maximum acceptable boundary angle, each input current harmonic should be computed.

According to the conclusion of (3.44) and Fig. 3.8(b), the mathematical expression of the line current during [θb, π–θb] can be expressed as

( ) ( )

_⎟⎟

⎠

⎜⎜ ⎞

⎝

⎛

⋅ −

−

⎟⋅

⎠

⎜ ⎞

⎝

= ⎛

b b

ac

ac t i t

i π θ

θ π π ω

ω sin 2

2 (3.45) where ω is the angular frequency of the line voltage. Thus, the nth harmonic component In can

be calculated by Fourier analysis:

where n = 1, 3, 5...39. Since the Class D limits are defined as the ratio of current harmonic to fundamental-frequency component, In/I1. From (3.46), we can obtain the normalized value of each harmonic as a function of the boundary angle as drawn in Fig. 3. 10. Fig. 3.10 shows that the most critical harmonic is the fifth for complying with the Class D requirements since its acceptable boundary angle is smaller than all the others. Therefore, the maximum allowable boundary angle is 1.005 rad ( = 57.58^o). It should be noted that since (3.45) is derived in

where n = 1, 3, 5...39. Since the Class D limits are defined as the ratio of current harmonic to fundamental-frequency component, In/I1. From (3.46), we can obtain the normalized value of each harmonic as a function of the boundary angle as drawn in Fig. 3. 10. Fig. 3.10 shows that the most critical harmonic is the fifth for complying with the Class D requirements since its acceptable boundary angle is smaller than all the others. Therefore, the maximum allowable boundary angle is 1.005 rad ( = 57.58^o). It should be noted that since (3.45) is derived in

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