CHAPTER 3. ANALYSIS OF THE PROPOSED ICS TECHNIQUES AND
3.6 Topology Refinement
3.6.1 Proposed Circuit and Operating Principles
As can be seen in Fig. 3.3, since winding N1 is in the charging path of Lr, the inductor Lr
can be used to provide both the boost ICS function operating in DCM and the soft-switching function for the DC-DC cell. Thus, the boost inductor can be saved and the volume and weight of magnetic components are reduced. Based on the above concept, a new single-stage soft-switching AC-DC flyback converter, shown in Fig. 3.16, is proposed. Like the fly-back-type implementation of the topology shown in Fig. 3.3, the new flyback converter can also provide the two following key functions. First, the ICS cell of the converter is charged in the duty-off time; therefore, the current stress on the main switch S1 is alleviated. Second, the charging time of the ICS cell is designed to be inversely modulated by the line voltage, so that the i-v curve of the average charging current presents a opposite deformation characteristic to that of the average discharging current. Therefore, the average charging current of the ICS cell can effectively compensate the line current distortion caused by the modulation of the ICS inductor discharging time. To sum up briefly, this converter combines the advantages of sim-ple topology, line current waveform correction, and switch current stress reduction.
Fig. 3.16 Proposed single-stage soft-switching AC-DC converter.
The basic operating principles of this converter can be referred to subsection 3.1.2. But the expressions of the average charging current and the average discharging current of the ICS cell are different from (3.16) and (3.27), respectively. To evaluate the line current shaping performance, we derive the related equations as follows.
Using the operating principle obtained in State 3, the average charging current of the ICS cell in one switching period can be calculated. First, by employing Ampere’s law, the current iN1 in this state is given by
3 1 3 2 1 2
1 N N
N i
n i n n
i =−n ⋅ − ⋅ . (3.48)
From Fig. 3.16 and KCL, the following equation is given:
2
1 Lr P Lm N
N i i i i
i + = = + . (3.49) Substitute (3.49) into (3.48) to replace iN2, the integration of (3.48) through the duty-off time can be obtained as:
( )
( )
( ) ( ) ( )
( )
( )
( )
( )
∫
∫
∫
−DTsiN t dt=−nn ⋅ −DTs iN t +iLr t −iLm t dt−nn ⋅ 01−DTsiN3 t dt 11 3
0 1
1 1 2
0 1 . (3.50)
Replacing the time functions of iLr, iLm, and iN3 with their corresponding voltage expressions yields
( )
( )
Averaging (3.51) over a switching period, the average charging current of the ICS cell can be obtained as follows:
( ) ( ) ( )
Moreover, the discharging current of the ICS cell in one switching period can be calcu-lated as follows. By employing Ampere’s law and KCL, the expression of iN1 in State 5 can be given by The substitution of (3.54) and (3.55) into (3.53) to replace iLr and iLm yields
( ) ( )
tBy integrating (3.56) through the Ds5Ts interval, the average discharging current of the ICS cell can be given as
3.6.2 Steady-State Analysis
The steady-state analysis of this converter is similar to the analysis introduced in subsec-tion 3.1.3 and performed as follows. By employing the voltage-second balance across Lm, one can obtain the following equation:
( ) ( )
0Similarly, the voltage-second balance across Lr gives
( ) ( )
0Since the Ds5 in mode M1 is very small and can be neglected in the circuit analysis, from (3.58), the duty ratio in mode M1 can be approximated as:
o
Moreover, we assume that the transformer almost has ideal coupling, thus the clamp capacitor voltage in mode M2 can be obtained from KVL along Cin-D1-N1-N2-S2-Cc-Cb. Substitute (3.61) into (3.59) to replace Vc; thus, the addition of (3.58) and (3.59) yields
( ) (
1)
5 0From (3.62), the time function of the duty ratio in mode M2 can be obtained as
( )
ac( )
o By substituting (3.63) into (3.58), the time function of Ds5 in mode M2 can be obtained as( ) ( ( ) ) ( )
(3.32), (3.34), and (3.35), respectively, in which if Lb is neglected. Additionally, for this con-verter, the clamp capacitor voltage Vc and the boundary angle θb have the same expressions as those of the flyback-type implementation of the converter shown in Fig. 3.3.3.6.3 Analysis of the Line Current Waveform
For a quantitative evaluation of the ICS function of the proposed converter, the charac-teristic curves of iN1,ch(ave), iN1,dis(ave), and |iac| should be sketched. First, by substituting (3.64) into (3.57), the expression of iN1,dis(ave) can be rearranged as follows:
( ) ( ( ) ) ( )
plotted in Fig. 3.17, in which only mode M2 is considered. These curves are sketched by using the same parameters as those in Section 3.3 for Vac = 110 Vrms and Vb = 1.15．Vac(pk).0 0.5 1 1.5 2 2.5 3 0
0.5 1 1.5 2 2.5 3
Line angle (rad)
Current (A)
(a) (b) Fig. 3.17 Comparison of iN1,ch(ave), iN1,dis(ave), and |iac| drawn by the proposed converter in a
half line cycle at 110 Vrms: (a) the currents as a function of instantaneous line voltage and (b) the current waveforms as a function of line angle.
As shown in Fig. 3.17(a), the i-v curve of iN1,ch(ave) can be designed to vary convexly while that of iN1,dis(ave) still varies concavely. It is apparent that iN1,ch(ave) and iN1,dis(ave) have re-markable distortion cancellation result. The special operation mechanism of iN1,ch(ave) is the same as that of iLb,ch(ave) introduced in Section 3.3. In this design example, the second partial derivative əiac2/ə2vac ranges between -2.4×10-5 and 2.9×10-4. Therefore, the relationship be-tween |iac| and |vac| has been verified to be nearly linear and can be concluded as (3.44).
Meanwhile, the converter also can draw almost sinusoidal line current from the AC line in mode M2, as shown in Fig. 3.17(b).
3.6.4 Experimental Results
To verify the discussed features of the proposed topology, a hardware prototype has been built and tested under the same specifications described in Section 3.2 and the input voltage range is 90–135 Vrms. The circuit components for the experimental prototype are the same as listed in Table 3.1 Fig. 3.18 shows the measured waveforms of the line voltage and line
cur-3.19 shows that the detailed harmonic contents of the line current well satisfy the require-ments of IEC 61000-3-2 Class D. It is worth mentioning that the harmonic components are extremely low except for the third harmonic caused by the limited boundary angle. Fig. 3.20 shows the maximum efficiency at full load is 91.7%. Fig. 3.21 shows that the bulk capacitor voltages for different input voltages range between 1.1–1.2 times as high as the peak line voltage. It also demonstrated that the proposed converter can obtain a well shaped line current waveform while M (ratio of Vb/Vac(pk)) is only from 1.1 to 1.2.
Fig. 3.18 Measured line voltage and current waveforms at Vac = 110 Vrms and 48 V/100 W output.
0 0.2 0.4 0.6 0.8 1 1.2
3 5 7 9 11 13 15
Harmonic order
Normalized harmonic current Class D limits
110 Vrms
Fig. 3.19 Measured line current harmonics distribution at full load.
87.5 88 88.5 89 89.5 90 90.5 91 91.5 92
90 100 110 120 130 135
Vac (Vrms)
Efficiency (%)
Fig. 3.20 Conversion efficiency versus input voltage.
0 50 100 150 200 250
90 100 110 120 130 135
Vac (Vrms)
Vb (Volt)
Measured Vb 1.1*Vac(pk) 1.2*Vac(pk)
Fig. 3.21 Bulk capacitor voltage versus input voltage.