CHAPTER 4. ANALYSIS AND PERFORMANCE OF THE PROPOSED
4.3 Mechanism for Suppressing Bulk Capacitor Voltage Stress
To clarify the mechanism for suppressing bulk capacitor voltage stress in the proposed converter, the analysis of the boost inductor currents at heavy load and light load is performed as follows. Fig. 4.6 shows the relation of both the duty-on time change of S1 and the boost in-ductor current change in a switching period under the load variation. At the rated condition, both the forward and flyback sub-converters work normally. Therefore, the boost inductor is charged by the voltage vac +Vo ⋅n1 n4 −Vb since the voltage vN1 is reflected from the output side during the duty-off time, as shown by the dashed lines of Fig. 4.6. When the load de-creases, the bulk capacitor voltage increases due to the power imbalance between the input and output. Meanwhile, the duty ratio decreases correspondingly to keep the constant output voltage in CCM operation. When the load decreases further, the reduced clamp capacitor voltage Vc caused by the decreased duty ratio can not induce the voltage –vN4 higher enough to forward bias D4. Thus, the flyback sub-converter is deactivated and only the forward sub-converter keeps supplying the output power. In this condition, the voltage vN1 is reflected from the clamp capacitor voltage instead of the output voltage. Therefore, the boost inductor Lb is charged by the approximate voltage of vac +Vc⋅n1 n2 −Vb, as shown by the solid lines of Fig. 4.6, where Vc is determined by the duty ratio as shown in (4.22). Since the value of
1 2
V n nc⋅ is smaller than that of V n no⋅ 1 4, the solid triangle will have a small area and a re-duced boost inductor current is prore-duced. With the proper arrangement of turns ratios between N1, N2, and N4, the reduced quantity of input current can yield the result that Vb is suppressed at light load.
b
Fig. 4.6 The gate voltage of S1 and the boost inductor current for different loads.
To examine the effect of suppressing the voltage stress on the bulk capacitor, it is intu-itional to calculate the value of Vb. In steady state, the energy absorbed by the converter should be equal to the output energy, the bulk capacitor voltages at full and light loads can be expressed as shown in (4.43) and (4.44), respectively.
( ) ( )
analytically. Thus, instead of directly calculating the value of Vb, we examine the change of input power under load variation. Fig. 4.7 shows the variations of instantaneous input power for different load conditions under the assumption of constant bulk capacitor voltage. These curves are sketched by using the parameters obtained in Section 4.2 for Vac = 260 Vrms and Vb = 1.15．Vac(pk). From Fig. 4.7, it can be seen that the input power always decreases as the load is reduced. After the calculation, the change rate of ΔPin(ave)/ΔPo(ave) can be obtained as 1.06 when the load is changed from Io to (3/4)Io, and the value of ΔPin(ave)/ΔPo(ave) is 2.55when the load is changed from (3/4)Io to (1/2)Io. Since the reduction amount of Pin(ave) is greater than that of Po(ave), the actual bulk capacitor voltage must decrease to maintain the in-put and outin-put average power balance. Meanwhile, the actual bulk capacitor voltage has a gradual decrease with the reduction of load current.
0 0.5 1 1.5 2 2.5 3
0 100 200 300 400 500 600
Line angle (rad)
Instantaneous input power (W)
Fig. 4.7 The variations of instantaneous input power for different loads.
4.4 Analysis of the Line Current Waveform
To investigate the line current waveform drawn by the proposed converter, the input i-v characteristic curves should be examined. As shown in Fig. 4.2, since the low pass filter Lf–Cf
will filter out the switching frequency components and harmonics of iLb, the rectified line cur-rent |iac(t)| mathematically approximates to the average value of iLb(t) within a switching pe-riod, namely, |iac| = iLb,ch(ave) + iLb,dis(ave). By using (4.12), (4.15), (4.21), (4.23), and (4.24), the expressions of iLb,ch(ave) and iLb,dis(ave) can be calculated as follows:
( ) ( ( ) ) ( )
2 1
4 1 2
2 )
(
, ⎟⎟⎠
⎜⎜ ⎞
⎝
⎛ + −
− ⋅
= ac o b
b s M
ave ch
Lb V V
n t n L v
T t t D
i (4.45)
( ) ( ( ) ) ( )
can be obtained as plotted in Fig. 4.8. Moreover, based on (4.20), (4.21) and (4.24), the curves of and Ds5 can be drawn in Fig. 4.9. These curves are sketched by using the parame-ters obtained in Section 4.2 for Vac = 110 Vrms and Vb = 1.15．Vac(pk). According to (4.15), when |vac(t)| increases, the discharging voltage across Lb decreases. Thus, Ds8 increases corre-spondingly as shown in Fig. 4.9. Moreover, the charging voltage of energy-storage inductor, i.e. Lm or Lo, in the Ds8Ts duration is smaller than that in the(
1−D)
(
D−Ds8)
Ts duration, as illus-trated in Fig. 4.5. Smaller charging voltage produces less magnetizing energy injected in en-ergy-storage inductors and consequently lower output voltage is formed. To maintain the con-stant output voltage, the controller will increase the duty ratio D under output voltage feed-back control. Thus, (1–D) will decreases with the increase of instantaneous rectified line voltage, as shown in Fig. 4.9. From the above result and (4.45), it can be found that the AC modulation effect on (1–D) makes iLb,ch(ave)(t) convexly vary with |vac(t)|, as shown in Fig.4.8(a). Thus, the waveform of iLb,ch(ave) can compensate the line current distortion caused by iLb,dis(ave). Although the slope of iac-vac curve is not definitely constant and still consists of small high order terms, the second derivative əiac2/ə2vac is small and ranges between -2.2×10-4 and 5.5×10-4. This result shows that the relationship between |iac| and |vac| is nearly linear and can be expressed as
( )
where Req is the equivalent input resistance. The linear result can be seen clearly from Fig.
0 50 100 150 0
0.5 1 1.5 2 2.5
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5
(a) (b) Fig. 4.8 Comparison of iLb,ch(ave), iLb,dis(ave), and |iac| drawn by the proposed converter in a half
line cycle at 110 Vrms: (a) the currents as a function of instantaneous line voltage and (b) the current waveforms as a function of line angle.
0 0.5 1 1.5 2 2.5 3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Line angle (rad)
Fig. 4.9
(
1−D)
and Ds8 versus line angle for 110 Vrms in a half line cycle.4.5 Experimental Results
To verify the feasibility and performance of the proposed topology, experimental tests were performed under the specifications described in Section 4.2. The circuit components used for the experiment are listed in Table 4.1.
Fig. 4.10 shows the measured line voltage and line current waveforms at Vac = 110 Vrms.
It can be seen that the current waveform has a near-sinusoidal shape in mode M2. Fig. 4.11 shows that the detailed current harmonics measured from the experimental prototype operat-ing in the nominal high and low line inputs both can satisfy the requirements of IEC 61000-3-2 Class D. Fig. 4.12 shows that the conversion efficiency at full load is 87–91.3%.
Fig. 4.13 shows that the bulk capacitor voltages are maintained within a desirable range (1.1–1.2 times as high as the peak line voltage) for the universal line voltage range (90–260 Vrms). Fig. 4.14 shows the bulk capacitor voltages with load variation at 260 Vrms line input.
The measured data indicate that the maximum bulk capacitor voltage is 418 V, so the com-mercially available 450V-rated capacitor can be used safely.
Table 4.1 Component values for the prototype circuit Component Device Description
S1, S2 SPA11N60C3
D1 U08A100
D2, D3, D4 U08A20C
Lb 105 μH
Lr 15 μH
Lm 329 μH
Lo 20 μH
n1: n2: n3: n4 35: 24: 9: 7
Cb 300 μF/450 V
Cr 780 pF
Cc 0.6 μF/400 V
Co 2000 μF/50 V
PWM controller UC3843
High-side switch driver IR2110
0 0.2 0.4 0.6 0.8 1 1.2
3 5 7 9 11 13 15
Harmonic order
Normalized harmonic current Class D limits
110 Vrms 230 Vrms
Fig. 4.11 Measured line current harmonics comparison at full load.
84 85 86 87 88 89 90 91 92
90 110 130 150 170 190 210 230 250 260 Vac (Vrms)
Efficiency (%)
Fig. 4.12 Conversion efficiency versus input voltage.
0 50 100 150 200 250 300 350 400 450 500
90 110 130 150 170 190 210 230 250 260 Vac (Vrms)
Vb (Volt)
Measured Vb 1.1*Vac(pk) 1.2*Vac(pk)
Fig. 4.13 Bulk capacitor voltage versus input voltage.
385 390 395 400 405 410 415 420
20 40 60 80 100
Output power (W) @ 260 Vrms
Vb (Volt)
Fig. 4.14 Bulk capacitor voltage versus output power at 260 Vrms line input.
4.6 Concluding Remarks
In this chapter, a novel S2ICS AC-DC converter for universal line and wide load range applications has been proposed based on an active-clamp flyback-forward topology. The ICS scheme is the two-terminal implementation of that proposed in Chapter 3. By employing the proposed ICS technique, two key advantages are obtained. First, during the duty-on time, the current stress across the main switch is alleviated. Second, the fact that the effective duty ratio of the ICS cell,
(
1−D)
, is modulated by the instantaneous line voltage results in a better lin-ear relationship between the line current and voltage through the conduction interval. More-over, by the intentional arrangement of deactivating the flyback sub-converter of the DC-DC cell at light load, the voltage stress across Cb is suppressed effectively because only the DCM forward sub-converter is operated and the slope of the boost inductor charging current is ad-justed by the duty ratio.Experimental results show that the maximum bulk capacitor voltage is 418 V in a wide range of output load at 260 Vrms line input. Owing to the ability to keep Vb below a desirable value (Vb < 450 V) under wide line and load variations, the proposed converter is very suit-able for the universal line voltage applications.
CHAPTER 5
CONCLUSIONS AND SUGGESTIONS FOR FURTHUR WORK
5.1 Conclusions
The original S2ICS concept comes from the integration of the DCM boost rectifier and PWM DC-DC converter by using one common switch. Thus, conventional S2ICS converters usually suffer from the relatively high switch current stress and line current waveform distor-tion caused by the voltage-follower control. To obtain better performance and achieve the cost-effective objective simultaneously, this dissertation explores advanced techniques for S2ICS AC-DC converters.
First, a novel ICS technique for single-stage AC-DC converters is introduced. Unlike the conventional single-stage designs, the proposed ICS scheme is intentionally arranged to be charged in the duty-off time. With this design, the switch current stress in the duty-on time is significantly reduced and accordingly the power loss is reduced. Moreover, this design pro-duces AC modulation effect on the charging time of the ICS cell so that the waveforms of the average charging current and average discharging current of the boost inductor can compen-sate each other automatically. Consequently, the input i-v curve has nearly linear relationship.
The proposed ICS scheme is then employed in an active-clamp DC-DC converter. In the flyback-type implementation, the resonant inductor Lr is arranged in the charging path of the boost inductor Lb so that Lr and Lb can provide the voltage-boost function together. Therefore, a small inductance for Lb is sufficient to achieve the DCM operation and the size reduction of magnetic material is allowable. Moreover, by programming the turns ratio between the addi-tional and secondary windings, the proposed converter can be guaranteed to comply with the IEC 61000-3-2 Class D specifications at as high efficiency as possible. Meanwhile, the bulk
capacitor voltages can be maintained within a desirable range, 1.1–1.2 times of the peak line voltage, even though the converter operates in a wide range of input voltage, 90–260 Vrms.
Experimental results have demonstrated the proposed line current correction function by a well shaped current waveform and the low current harmonics complying with requirements of IEC 61000-3-2 Class D. Furthermore, the high conversion efficiency around 90% has verified the effectiveness of the switch current stress alleviation and soft-switching function. In addi-tion, by saving the boost inductor, a refined topology can be obtained, which is suitable for narrow input voltage (90–135 Vrms or 180–260 Vrms) and higher power density applications.
Another key issue of S2ICS technique is the high bulk capacitor voltage stress. The bulk capacitor voltage Vb is not regulated and varies with the line voltage and the output load. To limit the bulk capacitor voltage stress below the tolerance of commercially available electro-lytic capacitors, this dissertation proposes a novel S2ICS AC-DC converter for universal line and wide load range applications based on an active-clamp flyback-forward topology. In the proposed topology, the flyback and forward sub-converters are operated in CCM and DCM, respectively, to achieve the hybrid operation mode with DCM while light load and CCM while heavy load. Thus, by deactivating the flyback sub-converter and keeping the forward sub-converter supplying the output power, the bulk capacitor voltage at light load condition can be suppressed effectively. Experimental results show that the maximum bulk capacitor voltage is 418 V in a wide range of output load at 260 Vrms line input. Moreover, owing to the center-tapped flyback-forward configuration, the energy is continuously transferred from the DC-DC cell to load irrespective of the state of main switch S1. Hence, this converter can be adopted in the applications with high output current and/or high output power.
In conclusion, the dissertation provides a practical solution to implement simple, reliable, efficient and cost-effective AC-DC converters.
5.2 Suggestions for Further Work
The dissertation employs the technique of using a multi-winding transformer to integrate a boost PFC rectifier and an active-clamp DC-DC circuit. Based on the proposed converters, the suggested further work is to realize magnetic integration circuits by integrating the exter-nal inductors and the power transformer with single magnetic core. This implementation will result in smaller size, lighter weight and lower cost as well as more attraction for low power applications.
To further promote the conversion efficiency of the proposed converters, several topics could be the potential further work for this objective. Since the active-clamp circuit can only provide turn-on ZVS for the main switch, the suggested further work is to replace the ac-tive-clamp circuit with advanced soft-switching technique, such as zero-voltage-transition (ZVT) circuit or zero-current-transition (ZCT) circuit, etc. These techniques can effectively achieve soft-switching and voltage spike suppression at turn-off of the power switch. More-over, although this dissertation employs the flyback-forward converter to facilitate the power delivery, there still exists a part of input power is processed two times before reaching final output. The part of input power is first transferred to bulk capacitor via the additional winding N1 and then transferred to output port via the DC-DC cell. Thus, another suggested further work is to achieve the power transfer process in one time delivery from input terminal to out-put port.
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