Future Work

Some future works are made up as follows:

1. For higher frequency applications, more accurate RF CMOS models must be built up in advanced, especially spiral inductor models for exact matching.

2. All parasitic effects, not only parasitic capacitance but also parasitic resistance and inductance, must be considered and included more carefully, especially for complicated and large chip area circuits at higher frequency. A more accurate procedure or EDA tool for extracting these parasitic effects is greatly urgency.

3. Because lack of mature noise measurement system and accurate calibration procedure, the noise performances of mixers have not been done in this thesis.

Th

de, ESD (Electrostatic di

precise predictions of circuit performances for future SOC total solutions.

erefore, to set up an accurate noise measurement system with correct calibration procedure for mixers will be also a greatly urgent work.

4. Since all circuits we have designed in this thesis can be integrated with other blocks on a single chip, on-chip bias networks and on-chip gain control mechanisms have to be designed and integrated for future SOC implementations.

5. As rapidly growth in CMOS technology with thinner gate oxi

scharge) protection circuits must be designed and involved in the RF IC.

6. The SPICE circuit simulator conjunction with 3-D simulator will make more

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