Chapter 5 New RF CMOS MICROMIXER design and implement
5.3 Simulation and Measurement of New CMOS MICROMIXER
5.3.1 Layout and Simulation Results
A new RF CMOS MICROMIXER by previous architecture is designed and optimized using 0.25μm CMOS technology. The final layout of it is shown in Fig.
5.3.1. All elements are fully integrated on a chip including spiral inductors, MIM capacitors, multi-finger RF NMOS transistors, poly resistors, and decouple MOS capacitors. The total chip size including the pads is about 1150umx1400um. It has been fabricated using TSMC 0.25μm mixed-signal CMOS process. Similarly, we also take advantage of shielded signal PAD as described in Section 3.4.1 to reduce coupling noise from the noisy Silicon substrate. We will show its final simulation and measurement performances latter.
The RF and L Hz and 2.44GHz,
respectively. The fact that LO frequency is lower than the center of desired band is called “low-side injection“. To minimize LO frequency will facilitate the design of oscillator. The output mixing IF signal thus falls at 10MHz. Because this work is designed for PCB on-board testing, the parasitic effects of bond-wires and bond-pads will greatly influence the impedance matching of all ports. For all outside 50Ω instruments, only input power of generators can be delivered into the chip or output
power of the circuit nts more efficiently
O signal frequencies are designed at 2.45G
can be received by measurement instrume
with good input or output impedance matching. Therefore, these parasitic effects must be included and considered throughout all simulation procedure very carefully.
Fig. 5.3.1 Layout of Proposed New MICROMIXER
The SPICE post simulation performances including all parasitic effects are shown in Fig. 5.3.2-9. Fig. 5.3.2 shows RF port input matching to 50ohm with input return loss of 17.5dB at 2.45GHz and Fig. 5.3.3 shows LO port input matching to 50ohm with input return loss of 14.1dB at 2.44Hz, while LO input power is –11dBm and RF input power is –35dBm. Fig. 5.3.4 shows voltage gain vs. RF input power swept from -50dBm to 0dBm with -11dBm LO input power and 1MΩ load. It exhibits high voltage gain of 11.0dB and V1dB of –10.0dBm. Fig. 5.3.5 shows voltage gain vs. LO input power swept from -30dBm to 0dBm with -35dBm RF input power and 1MΩ load. We can see that the maximum voltage gain is obtained while LO input power is –11dBm. Fig. 5.3.6 shows power gain vs. RF input power swept from -50dBm to 0dBm with -11dBm LO input power and 50Ω load. It exhibits power gain
of 1.6dB and P1dB of -20.0dBm. Fig. 5.3.7 shows power gain vs. LO input power sweep from -20dBm to 0dBm with -35dBm RF input power and 50Ω load. The maximum power gain is also obtained while input LO power is close to –11dBm. Fig.
5.3.8 presents its NF performance of 11.6dB. Finally, Fig. 5.3.9 shows two-tone test IIP3 simulation result of +1.1dBm and it exhibits quite good linearity of this circuit.
Besides, above results will also lead to quite a wide dynamic range. The simulation performances including corner affections are summarized in Table 5.3.1.
The proposed new MIXROMIXER not only dissipates very low power of 3.7mW (not including power dissipation of output buffer, 4.7mW) from a 2.5V power supply voltage but also provides very good performance. According to above results, we can conclude that the proposed modified circuit actually exhibits much higher gain, lower noise, higher linearity, wider dynamic range, and lower power consumption than the conventional basic one in CMOS technology.
Fig. 5.3.2 RF Port Input Matching Fig. 5.3.3 LO Port Input Matching
Fig. 5.3.4 Voltage Gain vs. RF Power Fig. 5.3.5 Voltage Gain vs. LO Power
Fig. 5.3.6 Power Gain vs. RF Power Fig. 5.3.7 Power Gain vs. LO Power
Fig. 5.3.8 Noise Figure Fig. 5.3.9 Two-tone Intermodulation
Specification TT FF SS
RF Input RL (dB) 17.5 16.1 17.5
LO Input RL (dB) 14.1 14.6 13.0
IF Output RL (dB) 11.6 12.9 10.5
Power Gain (dB) 1.6 5.4 -1.7
Voltage Gain (dB) 11.0 14.1 8.1
NF (dB) 11.8 10.6 13.0
P1dB (dBm) -20.0 -24.0 -17.5
V1dB (dBm) -10.0 -13.4 -7.1
IIP3 (dBm) +1.1 -3.7 +5.7
LO-to-RF Isolation (dB) > 50 >50 >50 Power
Consumption (mW)
Buffer: 4.7 Core: 3.7 Total: 8.4
Buffer: 5.0 Core: 4.4 Total: 9.4
Buffer: 4.4 Core: 3.3 Total: 7.7 Table 5.3.1 Post Simulation Performance Summary
5.3.2 Measurement Consideration
The simplified block diagram of the PCB on-board testing for our design is illustrated in Fig. 5.3.10. Because of differential LO input structure, one extra Balun is required to transform differential pair into single-ended port for common single-ended measurement systems. Here, we take advantage of one rat-race (1800 ring hybrid) as shown in Fig. 5.3.11 to act as such a Balun. The ideal S-parameter of rat-race is shown as follows:
It can split the input power from port 4 into output port 2 and port 3 with equal half power and 1800-phase difference. However, the real S-parameter of rat-race we have designed and implemented is as follows:
⎢⎢
Althou result sti little error, it is very close to that of ideal case and satisfied for our requirement
PCB layout and practical FR4 PCB circuit conjunction with SMA connectors for this work are shown in Fig. 5.3.12 and Fig. 5.3.13, respectively. One important thing must be taken care in the design of PCB layout, the width of RF and LO signal paths must be drawn as 50 atching. This chip is adhered to
PCB his ch then bonde PCB via bond-wires. The
die photograph of this chip including bond wires is shown in Fig. 5.3.14. Throughout all measurem cedures, we re ex ignal generators, one
spectrum analy xiliary devices,
⎥⎥
gh this experimental ll has .
Ω-line width for impedance m first and all I/O pads on t ip are d to
ent pro still requi tra three s
zer, one network analyzer, one oscilloscope and other au
such as cables, 50Ω terminals ,and power combiners. Since we have finished the prior preparations for PCB on-board testing, the measurements can now be proceeding according to arrangements in Fig.5.3.10. It should be noted that the losses of cable, Balun, Combiner, SMA connectors, and PCB board itself must be taken account for calibration and measurements.
Fig. 5.3.10 Simplified Block Diagram of PCB on-board Testing
Fig. 5.3.11 The Photograph of LO Port Rat-race
For DC Blocking Capacitors
Fig. 5.3.12 PCB Layout
50Ω Line
RF IN LO IN
IF OUT
Fig. 5.3.13 Photograph of Practical FR4 PCB circuit
Fig. 5.3.14 Die Photograph of New CMOS MICROMIXER
There are some RF parameters that we new RF CMOS MICROMIXER. These p ters include RF & LO input return loss, conversion gain, P1dB, and two-tone linea IIP3. We have used RFIC measurement systems in CIC and our laboratory to finish these parameter measurements. The simplified block diagrams of each m asurement setup for each parameter are illustrated in Fig. 5.3.15. In addition, an ex ltage-division circuit as described in Section 4.4.2 is also used to provide the desired stable dc bias voltages for these measurements.
have to measure in our design of arame
rity test of
e tra vo
(a)
(b)
(c)
Fig. 5.3.15 Simplified Block Diagram of Each Measurement Setup for (a) Conversion Gain (b) Two-tone IIP3 Test (c) Input Return Loss
5.3.3 Measurement Results
Upon previous measurement considerations and arrangements, we have made all PCB on-board tests for our design in CIC and our Laboratory. In 50Ω measurement system, Fig. 5.3.16 shows the measured RF port input matching and Fig. 5.3.17 shows the measured LO port input matching fro GHz to 5GHz. It exhibits both good RF port input return loss (RL) of 15.4dB at 2.45GHz and good LO port input RL of 16.1dB at 2.44GHz. The measurement and FF-corner simulation results of power gain versus LO input power swept from -20dBm to 0dBm are compared and shown in Fig.
5.3.18, where RF input power is fixed with –35dBm. We can see that the maximum measured power gain of 6.8dB can be obtained while LO input power is -11dBm. The measurement and FF-corner simulation results of power gain vs. RF input power swept from -40dBm to -8dBm are compared and shown in Fig. 5.3.19 where LO input power is fixed with -11dBm both in measurement and FF-corner simulation. It exhibits high measured power gain of 6.8dB and P1dB of -15dBm. Fig. 5.3.20 shows
m 0.5
the measurement result of two-tone test IIP3 that is -1.0dBm. It also exhibits much high linearity and wide dynamic range. Finally, IF output waveform is also measured by oscilloscope (1M Ω equivalent load), instead of spectrum analyzer (50 Ω equivalent load). Fig. 5.3.21 shows that the measured peak-to-peak voltage of IF output waveform is about 60.6mV while RF and LO input power is –35dBm and –11dBm, respectively. Through simple mathematics transformation, this circuit actually performs quite high voltage gain of 14.6dB. All simulation and measurement performances are summarized in Table 5.3.2.
This proposed new RF CMOS MICROMIXER dissipates total power of 10.5mW,
includ ower
supply volta er
simulation result in the part of core circuit but close to that of FF-corner simulation.
However, power dissipation of measurement almost coincides with that of simulation resul
5.3.4 Comparison and Discussion
ing 5.5mW in mixer core and 5.0mW in output buffer, from a 2.5V p ge. Power dissipation of measurement is more than that of TT-corn
t in the part of output buffer. This means that the process condition is now falling at the vicinity of FF-corner. Since the process condition is falling at the vicinity of FF-corner, Table 5.3.2 also contains the simulation results of FF-corner and we will make any comparison and discussion based on above measurements and FF-corner simulations in next section.
According to performance comparison result shown in Fig. 5.3.19, we can see that power gain of measurement is 1.4dB better than that of FF-corner simulation.
This is, in fact, because of more current drawing in mixer core circuit as compared to FF-corner simulation. As derived in Section 5.2, we know that IF port output voltage is proportional to square of the transconductance of NMOS transistors in the RF input drive stage of MICROMIXER core. Besides, in the same 50Ω input source resistor
and output load, power gain is also equal to square of voltage gain. An approximation is derived to explain above result as follows:
D
(2) With the same RF input power, we know that:
D
(3) According to (1), we can obtain that:
(4) To simplify, since process condition is at vicinity of FF-corner and we just estimate it approximately, so that we assume the variation ratio of process parameters is close to unity. Thus,
(
n ox)
FF−corner ≈1(5) Finally, the deviation of power gain in dB unit is obtained as follows:
V I
Above final result is very close to experimental deviation of power gain, 1.4dB.
In fact, process parameters variation ratio is a little more than unity. However, above approximation is actually a very useful estimation and explanation and it has
PDC _FF corner ⎠
⎝ −
demonstrated the root cause of this incremental power gain reasonably and obviously.
In addition, the P1dB value of measurement is much better than that of FF-corner simulation. Although the simulator underestimated the performance of dynamic range for our proposed new RF CMOS MICROMIXER, this result actually has demonstrated the good characteristic of wide dynamic range in a bisymmetric Class-AB RF stage topology.
From comparison results in Table 5.3.2, we can see that its good linearity performance of measured IIP3 is close to that of simulation result. However, although LO-to-RF isolation is much lower than the overestimated simulation result, it works r practical circuit application. Besides, from Fig. 5.3.18, we can also find that the measured maximum power gain occurs at almost the same LO input power as simulation result. It also has demonstrated that the
inpu
of on n the future.
In summary, although process condition is deviated from TT-corner and it causes a little more power consumption than what we expected, all of measurement performances are almost coincided with those of FF-corner simulation, even better. In other words, we actually reach the major purposes of our modification in original
wer and still maintain good linearity. Finally, we can conclude that our proposed modified new RF CMOS MICROMIXER actually works very well and exhibits much higher gain, higher linearity, better isolation, and wider dynamic range with acceptable low power consumption than the conventional basic MICROMIXER architecture in CMOS technology.
very well and meets the requirements fo
modified new MICROMIXER we proposed is indeed required only very low LO t power to drive the commutating pairs. Furthermore, it will facilitate the design
-chip oscillator for the integration i
MICROMIXER architecture, to achieve high gain with acceptable low po
-15.5dB
Fig. 5.3.16 Measured RF Port Input Matching
-16.1dB
Fig. 5.3.17 Measured LO Port Input Matching
Fig. 5.3.18 Power Gain vs. LO Input Power Comparison
Fig. 5.3.19 Power Gain vs. RF Input Power Comparison
Fig. 5.3.20 Two-tone Test Measurement Result
Fig. 5.3.21 IF Output Waveform Measured by Oscilloscope
Specification Simulation (TT) Simulation (FF) Measurement
RF Input RL (dB) 17.5 16.1 15.4
LO Input RL (dB) 14.1 14.6 16.1
IF Output RL (dB) 11.6 12.9 NA
Power Gain (dB) 1.6 5.4 6.8
Voltage Gain (dB) 11.0 14.1 14.6
NF (dB) 11.8 10.6 NA
P1dB (dBm) -10 -13.4 -15
IIP3 (dBm) +1.1 -3.7 -1.0
LO-to-RF Isolation (dB) > 50 > 50 32 Power
Consumption (mW
Buffer: 4.7 (1.9mA) Core: 3.7 (1.5mA)
Buffer: 5.0 (2.0mA) Core: 4.4 (1.8mA)
Buffer: 5.0 (2.0mA) Core: 5.5 (2.2 A)
0.5 (4.2mA) m ) Total: 8.4 (3.4mA) Total: 9.4 (3.8mA) Total: 1
Table 5.3.2 Simulation and Measurement Performance Summary
Chapte
nclusi and Futu Work
r 6
Co on re
6.1 Conclusion
This thesis contents three works. The first work is a novel full
concurrent triple-band CMOS LNA 8GHz, 2.45GHz, and 5.25GHz. The second
work is a ed CMO r
work CM R ll n
performa n
bricated using TSMC 0.25-µm CMOS process through CIC. In this thesis, we have resented the design concepts, simulation results, experimental results, and advanced omparisons & discussions for these three works.
.1.1 Concurrent Triple-Band CMOS LNA
y integrated for 1.
modifi S double-balance mixer merged LNA fo WCDMA. The last is a new RF OS MICROMIXE for 2.45GHz. A of the simulatio
nces were finished through Eldo-RF simulator. These three ICs all have bee fa
p c
6
A novel fully integrated concurrent triple-band CMOS LNA has been designed nd presented in this thesis. All measurements were finished through on-wafer testing t NDL. The measured input matching for lower dual frequency bands (1.8GHz and .45GHz) is nearly falling at desired frequencies and achieves better matching than mulation. But the input matching for higher frequency band (5.25GHz) is shifted to wer frequency at 4.5GHz. The major reason is that the parasitic inductances are not onsidered and included in our design procedure. The measured output matching is early broadband matching but still has the trend of concurrent triple-band matching.
his is because the original additive feedback capacitors are chosen too small to ontrol exactly and have great deviations after fabrications. Besides, the power gain and noise figure performances do not meet our anticipation in this architecture. Three a
major factors also have been ex 4. However, this LNA design can achieve better dynamic range and linearity of P1dB and IIP3 parameters in measurement tha
In fact, the models of the spiral inductors applied at higher frequency (5.25GHz) are not as accurate as those applied at lower frequency. So that they will also cause misma
that is first proposed.
d LNA
plained in Section 3.5.n those in simulation.
tches between simulation and measurement results. In summary, to design a concurrent multi-band LNA or even other RF circuits with better performances, not only the parasitic effects have to be considered more carefully but the more accurate models designed and optimized for all desired frequencies must be involved, especially for complicated and large chip area circuits at higher frequency.
Although the measured performances in S-parameters and noise figure are not as good as that in simulation results, we actually have demonstrated our novel circuit design concepts of the concurrent triple-band LNA
6.1.2 CMOS Double-Balanced Mixer Merge
A modified CMOS double-balanced merged LNA has been design and presented in this thesis. All measurements were finished through PCB on-board testing at CIC and our laboratory. The process condition has been shifted between TT and SF-corner.
The power gain of measurement is about 1.5dB lower than that of TT-corner simulation. And the maximum measured power gain occurs at higher LO input power than TT-corner simulation result. Besides, the linearity performance of the two-tone test IIP3 is very close to the simulation result and the measured P1dB is better than the TT-corner simulated one. All factors to cause these measurement results have been explained in Section 4.4.4. Finally, although LO-to-RF isolation is much lower than the overestimated simulation result, it works very well and meets the requirements for practical circuit application.
In summary, although some performances are a little degraded as compared to the simulation results, our proposed modified merged LNA & Mixer circuit actually works very well and exhibits much higher gain, higher linearity, better isolation, and wider
6.1.3 New RF CMOS MICROMIXER
dynamic range with acceptable low power consumption than the conventional cascade LNA & Mixer architecture in CMOS technology.
A modified New RF CMOS MICROMIXER has been designed and presented in this thesis. All measurements were also finished through PCB on-board testing at CIC and our laboratory. The process condition has been moved toward FF-corner. The powe
in has been demonstrated and explained through a very useful approximate estimation. In addition, the P1dB value of measurement is much better than that of FF-corner simulation. This resul
r gain of measurement is about 1.4dB better than that of FF-corner simulation.
This is because of more current drawing in mixer core circuit as compared to FF-corner simulation. The root cause of this incremental power ga
t actually has demonstrated the good characteristic of wide dynamic range in a bisymmetric Class-AB RF stage topology.
Besides, the circuit performs good linearity of high measured IIP3 that is close to that of simulation result. However, although LO-to-RF isolation is much lower than the overestimated simulation result, it works very well and meets the requirements for practical circuit application. We can also find that the measured maximum power gain occurs at almost the same low LO input power as simulation result. It will facilitate the design of on-chip oscillator for the integration in the future.
In summary, although process condition is deviated from TT-corner and it causes a little more power consumption than what we expected, we actually reach the major
purp
ption than the conventional basic MICROMIXER architecture in CMOS technology.
oses of our modification in original MICROMIXER architecture, to achieve high gain with acceptable low power and still maintain good linearity. Finally, we have demonstrated that our proposed modified new RF CMOS MICROMIXER actually works very well and exhibits much higher gain, higher linearity, better isolation, and wider dynamic range with acceptable low power consum
6.2 Future Work
Some future works are made up as follows:
1. For higher frequency applications, more accurate RF CMOS models must be built up in advanced, especially spiral inductor models for exact matching.
2. All parasitic effects, not only parasitic capacitance but also parasitic resistance and inductance, must be considered and included more carefully, especially for complicated and large chip area circuits at higher frequency. A more accurate procedure or EDA tool for extracting these parasitic effects is greatly urgency.
3. Because lack of mature noise measurement system and accurate calibration procedure, the noise performances of mixers have not been done in this thesis.
3. Because lack of mature noise measurement system and accurate calibration procedure, the noise performances of mixers have not been done in this thesis.