Chapter 1 Introduction …
1.3 Thesis Organization
This thesis contains six chapters. In addition to Chapter 1, the introduction of our circuit design motivations and associated recent works for wireless communication systems, other chapters are organized as follows:
In Chapter 2, we will introduce some basic CMOS technology applied to RF integrated circuits. We will also briefly describe some basic on-chip components and models, such as MOSFET, MIM capacitors, and spiral inductors, which can be applied to RF front-end circuit.
In Chapter 3, we will present the design and implementation of a concurrent triple-band (1.8GHz, 2.45GHz and 5.25GHz) CMOS LNA. We will also introduce the concepts of concurrent triple-band receiver topology.
In Chapter 4, we will present the design and implementation of a CMOS double-balanced mixer merged LNA for WCDMA.
In Chapter 5, we will present the design and implementation of a new RF CMOS MICROMIXER for 2.45GHz.
In the final Chapter 6, we will make a conclusion and discuss the future works.
Chapter 2
RF IC Components and Models In CMOS Technology
2.1 Choice of Technology for RF Circuits
The viable IC technology for RF circuits continues to grow up. Performance, cost, and time to market are three critical factors influencing the choice of technologies in the competitive RF industry. Besides, the issues such as level of integration, form factor, and prior experience also play an important role in the decisions made by the designers. At present, a lot of technologies constitute the major section of the RF market, including GaAs, silicon bipolar, SiGe, CMOS, BiCMOS, and so on. [9] Usually viewed as low-yield, high power, high cost options, GaAs field-effect and heterojunction devices nonetheless have maintained a strong presence in RF products, especially in power amplifiers and front-end switches.
While GaAs processes offer useful features such as higher breakdown voltage, higher cutoff frequency, semi-insulating substrate, and high-quality inductors and capacitors, silicon devices in a VLSI technology can potentially provide both higher levels of integration and lower overall cost, as demonstrated in complex circuits such as frequency synthesizers. In fact, all building blocks of typical transceivers are available in silicon bipolar technologies from many manufactures. [25]
Although silicon bipolar and SiGe can provide good performance for RF ICs, CMOS technology still predominates over RF IC markets due to its advantages of lower cost, higher integration, more flexible size-scaling, superior linearity, and wider dynamic range. Besides, with rapidly developments in semiconductor process and
fabrication, scaling-down CMOS devices have achieved higher transit frequencies, such as tens of gigahertz in the 0.18-µm generation, and have fulfilled the requirements for RF IC applications. Furthermore, another noticeable advantage over the CMOS technology is that CMOS RF IC can be easily integrated with other mature base-band or mixed-signal parts for system-on-a-chip (SOC), supported by the enormous momentum of the digital market. However, this advantage of CMOS technology will inevitably face a lot of difficulties for its SOC applications.
“CMOS RF IC” has suddenly become the topic of active research. CMOS technology must nevertheless resolve a number of practical issues, such as substrate coupling, parameter variation with temperature and process, and device modeling for RF operation. COMS technology is inborn for logic application, so that the high frequency unpredictable characteristic will be a challenge for designer. To achieve better performance, it is necessary to build up more accurate and reliable RF models toward active and passive devices.
2.2 Active Device and RF Model
MOSFET is the most important and widely used among all of devices in RF CMOS technology. The structure and RF small signal model based on the sub-circuit approach are given in Fig. 2.2.1(a-b). This small signal model includes all parasitic components at the gate, source, drain, and substrate of transistor. The values of these parasitic components strongly depend on the layout and process fabrication of MOSFET. It can be used to model the MOSFET nonlinear characteristics at radio frequency. The intrinsic core model is based on the SPICE BSIM3v3 model. In this BSIM3v3 model, it has built in thermal noise characteristics as shown in Fig. 2.2.1(c).
[10] However, this BSIM3v3 model is actually not an accurate noise model for radio frequency applications, so that the simulation results of noise parameters using this
RF equivalent model are just approximations and can not be convinced completely.
Therefore, a more accurate RF noise model is indeed required to be built up in advanced for precise RF noise performance estimation.
(a)
(b)
(c)
Fig. 2.2.1 (a) Cross-section view of MOSFET structure (b) Schematic of the equivalent circuit model for RF MOSFET (c) The equivalent sub-circuit
including noise characteristics in the BSIM3v3 core model
As described previously, the physical layout is strongly associated with the parasitic components in the equivalent MOSFET model at high frequency. Since the foundry usually provides some standard physical layouts corresponding to separate equivalent circuit models extracted from testkey measurements, the physical layout of MOSFET must fit in with the choice of circuit model in the original circuit design procedure. Fig. 2.2.2 shows a case of MOSFET standard layout provided by foundry.
It is found that the multi-finger structure can uniform signal or current paths and largely decrease gate resistance. In addition, many significant issues, such as current endurance, heat distribution, and ac signal coupling etc, must be considered carefully in a practical circuit layout to achieve desired good performance.
Gate Bulk
Source Source Source Source Source
Drain Drain Drain Drain
Fig. 2.2.2 Layout of Multi-finger RF MOSFET
2.3 Passive Device and RF Model
In the design of analog or RF IC, the passive devices, such as the poly resisters, MIM or POLY capacitors, and spiral inductors, always play significant roles toward circuit performance. They are usually used for dc bias, dc or RF blocking, impedance matching, and gain enhancement etc. For this reason, to realize and build up accurate
models of passive devices is an inevitable work for CMOS IC designers. Two passive devices, MIM capacitor and spiral inductor, are especially important and suitable for CMOS RF IC applications and thus are described in subsequent sections.
2.3.1 De-embedding Procedure
Before the formal descriptions of passive device models, an important method called “de-embedding procedure” must be introduced first. It is very useful for the testkey design and device modeling. In high frequency measurement, the purpose of de-embedding is to exclude the parasitic effects that are not associated with the device itself, such as those in pads. A simplified diagram of de-embedding procedure is shown in Fig. 2.3.1. When we design a “whole” testkey of device to build up its equivalent circuit model, the testkies of “open” and “through” must be also involved to completely exclude all parasitic effects. However, in general, if the operating frequency for device modeling is lower than 6GHz, the only dominant parasitic effect is in “open” pad. Consequently, we usually just consider the effect of “open” pad while neglecting the effects of “through” and “short” in the de-embedding procedure.
Furthermore, a simplified procedure of de-embedding can be proceeding as follows: First, transform the measured S-parameters of “whole” testkey and its “open”
pad to Y-parameters. Here, the transformation to Y-parameters will greatly facilitate the calculations of de-embedding because both of their equivalent circuits are in parallel. Second, subtract the Y-parameter of “open” pad (Yopen) from that of “whole”
testkey (Ytotal) and have Yde. Finally, transform Yde back to the de-embedded S-parameter (Sde) we desired. The simplified expression is as follows:
[ ]
de opentotal
de S Y Y SY
S = [ − ]=
Thus, we can build up accurate device models using these de-embedded S-parameters.
Fig. 2.3.1 Simplified block diagram of de-embedding procedures
2.3.2 MIM Capacitors
The most linear on-chip capacitors are in metal-insulator-metal (MIM) structures and are so called MIM capacitors as shown in Fig. 2.3.2. In the 1P5M (one POLY and five Metal layers) 0.25-µm CMOS technology, MIM capacitor consisted of Metal 4 layer as bottom plate and an additional layer, called CTM (Capacitor Top Metal), as top plate is one of two-port parallel plate’s structures, where CTM layer is connected out via Metal 5 layer and the thin oxide dielectric layer is placed in between CTM and Metal 4 layer. The principle of parallel plate capacitors is applied to MIM capacitors and thus its capacitance can be approximately estimated by the formula:
d L W d
C ≈ε A =ε ⋅
where ε is the dielectric constant, A is the overlapping area between CTM and Metal 4 layers calculated by multiplication of width W and length L, and d is the distance between top and bottom plate. [11] In theory, if fixed ε and d, we can get any desired capacitances flexibly by adjusting W and L. However, although the capacitance is proportional to the area of MIM capacitor, the larger area will decrease the Q (Quality factor) value of it due to fringing effects and the smaller area will also cause more
deviations in capacitance value due to process variations in practical fabrication.
Typically, the capacitance of MIM capacitor is designed in the range of 0.2pF to 10pF and the Q value of it is in the range of 20 to 80 that is strongly depended on the area and operating frequency. Finally, Fig. 2.3.3 shows the equivalent circuit model for MIM capacitor that is capable of correctly modeling its RF characteristics. It includes the undesired effects from the lossy silicon substrate and other parasitic effects. In this equivalent circuit model, the inter-metal dielectric capacitance Cs is the main element of the capacitor, Rs and Ls are the parasitics existing in the electrodes, interconnections, metal plates, and dielectric loss, Cp and Rp are parasitics that represent the capacitance and resistance to ground between bottom plate metal and substrate.
Fig. 2.3.2 (a) Layout top view (b) Cross section view of MIM capacitor
Fig. 2.3.3 Equivalent circuit model of MIM capacitor
2.3.3 Spiral Inductors
From the view point of RF circuits, the lack of a good inductor is by far the most conspicuous shortcoming of standard IC processes. In general, three types of inductors, including active inductor, bond wire inductor, and spiral inductor, have been used for RF IC applications. Although active circuits can sometimes synthesize the equivalent of an inductor, they always have higher noise, distortion, and power consumption than real passive inductors made with some number of turns of wire.
However, although bond wire inductors permit a high quality factor to be achieved, their inductance values are constrained and can be rather sensitive to production fluctuations. Typically, the inductance of bond wire inductor is about 1nH per 1mm length and Q of it is about 60 near GHz frequency. Furthermore, the only widely used on-chip inductor is spiral inductor, a square version of which is shown in Fig. 2.3.4.
One thing must be noticed that any device underneath inductor was forbidden due to magnetic flux penetrate into the silicon substrate. It will affect the device behavior when the device is under spiral inductor. In addition, on-chip spiral inductor has become one of the critical components and plays a significant role for implementing modern low-cost and high-integration RF ICs such as a low-noise amplifier, a voltage-controlled oscillator, and an impedance matching network etc.
Fig. 2.3.4 Square planar spiral inductor
The values of inductance (L), quality factor (Q), and self-resonant frequency (SRF) are three major indexes for the design of a spiral inductor. A good spiral inductor must provide desired accurate inductance value, high quality factor, and high SRF with acceptable area. One of the most important parameters is the quality factor, which is mainly limited by the loss due to inductor metal resistance, substrate resistance, and that associated with induced eddy current below the inductor metal trace. For the CMOS RF IC applications, the realization of high Q spiral inductors is an important task to be solved imperatively, but this task is confronted with the challenge of high frequency performance degradation due to higher silicon substrate losses and thickness limitations of metal lines.
Recently, considerable efforts have gone into the design and modeling of spiral inductor implementations. A simple equivalent circuit model for spiral inductor is shown in Fig. 2.3.5. In this model, Ls represents the major spiral inductance, Rs is the series parasitic resistance which represents the energy losses due to the skin effect in the spiral interconnect structure and the induced eddy current in any conductive media close to the inductor, Cs represents the parasitic capacitance overlapped between the spiral and the center-tap underpass, Cox represents the oxide capacitance between the spiral and the substrate, Rsi represents the ohmic loss which signifies the energy dissipation in the silicon substrate, and Csi represents parasitic capacitance in the silicon substrate. While a lot of methods have been developed to estimate for the inductance of spiral inductor, one of the most useful expressions is analytical formulas for the inductance calculation proposed in [12]. The Q value of spiral inductor is defined as:
sycle
The single-ended Q value can be simply derived form the image part over the real part
of the input impedance while port 2 is short to ground, that is:
[ ] [ ]
R X Zin Q= Zin =Re Im
Typically, the Q value of spiral inductor is about in the range of 4 to10 with the appropriate design of geometrical sizes.
Fig. 2.3.5 Equivalent circuit model for spiral inductor
There are a lot of methods that can be used to improve the Q value of spiral inductors. Since the Q value depends on the real part of input impedance, so we can improve the Q value by reducing the resistance. Although increasing metal width (W) will reduce the resistance and thus increase the Q value in the lower frequency range, it will lower the self-resonance frequency. Another simple useful method is to take advantage of double metal layers in parallel to decrease the real part of input impedance and thus improve the Q value. Fig. 2.3.6 shows the simplified diagram of the single metal layer and double metal layer inductor structures in 1P5M 0.25-µm CMOS technology.
Throughout this thesis, in addition to square spiral inductors, we also take advantage of double metal layer circular spiral inductors, one case of them as shown in Fig. 2.3.7. In general, circular spiral inductors have the advantage of higher quality factor than other geometries with the same inductance value. Besides, it can also be realized with smaller inductance suitable for higher frequency applications.
Metal5
(a) (b) Figure 2.3.6 (a) Cross section view of a single metal layer spiral inductor (b) Cross section view of a double metal layer spiral inductor
Fig. 2.3.7 Circular spiral inductor Metal4
SiO2
SiO2
via
Metal5
Metal4 Metal3 via
via
Substrate
Chapter 3
Concurrent Triple-Band CMOS LNA Design and Implementation
3.1 Architecture of Concurrent Multi-Band Receiver
Standard receiver architectures, such as super-heterodyne or zero-IF receivers, achieve high selectivity and sensitivity by narrow-band operation at a single input frequency. [13] Such operation modes always limit available bandwidth and robustness to channel variation and functionality of system. On the other hand, general wideband operations are more sensitive to out-of-band unwanted signals due to nonlinearity of transistors, even for new generation of ultra wideband system (UWB). These out-of-band blockers can severely degrade receiver’s sensitivity. [14]
However, modern wireless applications necessitate communication systems with more wideband, functionality and flexibility. Besides, for low cost and high integration consideration, the CMOS process has become one of the most popular technologies to provide excellent integration with other base-band blocks. Therefore, multi-standard RF receiver systems which integrated using CMOS technology are predicted to play a critical role in the future wireless communication system. Recently, multi-band receivers have been introduced to achieve these goals by switching between multiple bands to receive one band at a time [15-17], such as a simplified block diagram of the conventional dual-band WLAN receiver for IEEE802.11a/b/g shown in Fig. 3.1.1.
Although it improves the receiver’s versatility, it is not sufficient in the case of a multi-functionality receiver where more than one band needs to be received simultaneously. Besides, using conventional receiver architectures, simultaneous
operation at different frequency bands can only be achieved by building multiple independent signal paths with an inevitable increase in the cost, footprint, and power dissipation.
2.4GHz band receiver
Fig. 3.1.1 Conventional dual-band receiver architecture If we can combine two or m
of si
ore single-path RF receivers into one that is capable multaneous operation at different frequencies without dissipating as much power or a significant increase in cost and footprint, it will much reduce cost & power dissipation and improve integration in advanced. This observation leads to a compact and efficient front-end for a concurrent multi-band receiver, such as a simplified block diagram of the concurrent dual-band receiver shown in Fig. 3.1.2, which consists of a dual-band antenna, a monolithic dual-band filter, and a concurrent dual-band low noise amplifier (LNA) that provides simultaneous gain and matching at two bands. [2]
It should be noted that the concurrent multi-band receiver does not need any multi-band switch or diplexer, because simultaneous reception at both bands is desired. However, a suitable LNA must be designed and realized before implementing a multi-standard receiver. This kind of novel LNA called concurrent multi-band band LNA [1] have to provide simultaneous narrow-band input matching and gain at multiple frequency bands, while maintaining low noise. A detailed approach to the design of such a multi-band LNA will be described in the subsequent sections.
BPF LNA BPF
Base band 1
LO1 LO2
SwSwiittcchhiingng BaBanndd
Base band 2 5.2GHz band receiver
BPF’ LNA’ BPF’
LO1’ LO2’
BPF LNA BPF
BPF’ LNA’ BPF’
Fig. 3.1.2 Concurrent dual-band receiver architecture
3.2 Review of Concurrent Dual-Band LNA Architecture
As the wireless communication system becomes mature and widespread, the requ
design detai
irement of a LNA for the system has become a lot more sophisticated. Besides, LNA is one of the most critical building blocks in modern integrated RF transceivers for wireless communications. Recently, many researches about dual-band LNA have been studied and reported. [2-5] However, the concurrent triple-band LNA is rarely cited and studied. In this work, a new fully integrated high linearity concurrent triple-band CMOS LNA is first proposed that is capable of simultaneous operation at all three different frequency bands (1.8GHz, 2.45GHz, and 5.25GHz) without dissipating triple as much power or a significant increase in cost and footprint.
To provide some background and knowledge, before explaining the
ls of concurrent triple-band LNA, it is helpful to review some basic design guidance and architecture of concurrent dual-band LNA. Similar to the single-band LNA, being the first active element of the receiver chain, the noise figure (NF) of a
dual-band LNA also plays a significant role in the overall NF of the dual-band receiver. Fig. 3.2.1 (a) shows the general model for transistor amplifier in common source configuration with arbitrary gate impedance (Z )g , source impedance (Z )s , load
impedance ( ), gate-source impedance ( and gate-drain impedance ( . Fig.
3.2.1(b) also shows its equivalent circu that includes the inherent ctance components (C &gs C ) of the transistor. We can use this equivalent model to achieve gd simultaneous er d noise matching in a concurrent multi-band LNA. Assume that Zgd is much larger than the other impedances and the effects of C and its gd associated Miller effect can be neglected, the input impedance can be simplified as:
ZL Z )gs ,
This expression can be used to design multi-band input matching network with
This expression can be used to design multi-band input matching network with